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revision date: feb 22 , 2005 16 h8s/2639, h8s/2638,h8s/2636, h8s/2630, h8s/2635 group hardware manual renesas 16-bit single-chip microcomputer h8s family/h8s/2600 series rev. 6.00 rej09b0103-0600
rev. 6.00 feb 22, 2005 page ii of lx 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 6.00 feb 22, 2005 page iii of lx preface this lsi has the internal 32-bit h8s/2600 cpu and includes a variety of peripheral functions necessary for a system configuration. it serves as a high-performance microcomputer. the on-chip peripheral devices include a 16-bit timer pulse unit (tpu), a programmable pulse generator (ppg), a watchdog timer unit (wdt), a serial communication interface (sci), an a/d converter, a motor control pwm timer (pwm), a pc brake controller and i/o ports. it also has an internal data transfer controller (dtc), which performs high-speed data transfer without using the cpu, thus enabling the use of the lsi as an embedded microcomputer in various advanced control systems. two types of internal rom are available: flash memory (f-ztat? * ) and mask rom. the lsi can be used flexibly in a wide range of applications from applied equipment with varied specifications and early production models to full-scale mass-produced products. notes: the h8s/2635 and h8s/2634 are not equipped with a ppg, a pc brake controller, or a dtc. * f-ztat is a trademark of renesas technology corp. target users: this manual was written for users who will be using the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 in the design of application systems. members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 to the above audience. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. ? in order to understand the details of the cpu's functions read the h8s/2600 series, h8s/2000 series progra mming manual. ? in order to understand the details of a register when its name is known the addresses, bits, and initial values of the registers are summarized in appendix b, internal i/o registers. example: bit order: the msb is on the left and the lsb is on the right.
rev. 6.00 feb 22, 2005 page iv of lx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635 group manuals: document title document no. h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635 hardware manual this manual h8s/2600 series, h8s/2000 series programming manual rej09b0139 user?s manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimized linkage editor user's manual rej10b0058 h8s, h8/300 series simulator/debugger (for windows) user's manual ade-702-037 h8s, h8/300 series high-performance embedded workshop user's manual ade-702-201 application notes: document title document no. h8s family technical q & a rej05b0397
rev. 6.00 feb 22, 2005 page v of lx main revisions in this edition item page revision (see manual for details) all h8s/263 5 and h8s/2634 added preface iii note amended note s : the h8s/2635 and h8s/2634 are not equipped with a ppg, a pc brake controller, or a dtc. * f-ztat is a trademark of renesas technology corp. target users: this manual was written for users who will be using the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/26 35 , and h8s/2634 in the design of application systems. ? 1.1 overview 1 description amended the h8s/2636, h8s/2638, h8s/2639 , h8s/2630, h8s/2635 , and h8s/2634 are microcomputers (mcus: microcomputer units), built around ? on-chip rom is available as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte flash memory (f-ztat tm * version), and as 128-kbyte, 192-kbyte, 256-kbyte, and 384- kbyte mask rom. ? the features of the h8s/2636, h8s/2638, h8s/2639 , h8s/2630, h8s/263 5 , and h8s/2634 are shown in table 1-1. note s: the h8s/2635 and h8s/2634 are not equipped with a dtc, a ppg, or a d/a converter. * f-ztat is a trademark of renesas technology corp. table 1-1 overview 2 item in table 1-1 amended pc break controller (this function is not implemented in the h8s/2635 group) data transfer controller (dtc) (this function is not implemented in the h8s/2635 group) 3 programmable pulse generator (ppg) (this function is not implemented in the h8s/2635 group) controller area network (hcan) 2 channels (the h8s/2635 group has one hcan channels) d/a converter (this function is not implemented in the h8s/2635 group) 4memory product name rom ram h8s/2630 * 384 kbytes 16 kbytes h8s/2635 192 kbytes 6 kbytes h8s/2634 128 kbytes
rev. 6.00 feb 22, 2005 page vi of lx item page revision (see manual for details) 1.1 overview table 1-1 overview 4 item in table 1-1 amended interrupt controller ? 49 interrupt sources (45 sources in h8s/2635) 5 clock pulse generator ? input clock frequency h8s/2636, h8s/2638, h8s/2630: 4 to 20 mhz h8s/2639 , h8s/2635, h8s/2634: 4 to 5 mhz product lineup model name mask rom version f-ztat version subclock functions i 2 c bus interface rom/ ram (bytes) packages hd6432630f hd64f2630f no no hd6432630uf (u-mask version) hd64f2630uf (u-mask version) yes no 384 k/ 16 k hd6432630wf (w-mask version) hd64f2630wf (w-mask version) yes yes hd6432635f hd64f2635f yes no 192 k/ 6 k hd6432634f ? yes no 128 k/ 6 k note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the u-mask and w-mask versions , and h8s/2635 group, but are not in the other versions. 1.2 internal block diagram figure 1-1 (c) internal block diagram of h8s/2635 group 8 figure added 1.3.1 pin arrangement figure 1-2 pin arrangement of h8s/2636 group (fp-128b: top view) 9 note added notes: ppg and d/a converter pin functions not implemented. 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). ? figure 1-3 pin arrangement of h8s/2638 group and h8s/2630 group (fp-128b: top view) 10 notes: the ppg and d/a converter pin functions not implemented. 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). ?
rev. 6.00 feb 22, 2005 page vii of lx item page revision (see manual for details) 1.3.1 pin arrangement figure 1-5 pin arrangement of h8s/2635 group (fp-128b: top view) 12 figure 1-5 added 1.3.2 pin functions in each operating mode table 1-2 pin functions in each operating mode 14 table amended, note * 4 added pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 27 pe7/d7 pe7/d7 pe7/d7 pe7 28 pe6/d6 pe6/d6 pe6/d6 pe6 29 pe5/d5 pe5/d5 pe5/d5 pe5 30 pe4/d4 pe4/d4 pe4/d4 pe4 31 pe3/d3 pe3/d3 pe3/d3 pe3 32 pe2/d2 pe2/d2 pe2/d2 pe2 33 pe1/d1 pe1/d1 pe1/d1 pe1 34 pe0/d lwr / adtrg / irq3 0 pe0/d0 pe0/d0 pe0 42 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ adtrg / irq3 16 pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 89 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0 90 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0 91 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka 92 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb 93 p1 irq0 irq1 irq1 irq1 irq1 irq0 irq0 irq0 4/po12 * 4 /tioca1/ p14/po12 * 4 /tioca1/ p14/po12 * 4 /tioca1/ p14/po12 * 4 /tioca1/ 94 p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc 95 p16/po14 * 4 /tioca2/ p16/po14 * 4 /tioca2/ p16/po14 * 4 /tioca2/ p16/po14 * 4 /tioca2/ 96 p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd 109 p46/an6/da0 * 4 p46/an6/da0 * 4 p46/an6/da0 * 4 p46/an6/da0 * 4 110 p47/an7/da1 * 4 p47/an7/da1 * 4 p47/an7/da1 * 4 p47/an7/da1 * 4 17 notes amended notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group. ... the h8s/2639 and h8s/2635 groups have no osc1 and osc2 pins. 4. the ppg output, da0, and da1 are not supported in h8s/2635 group.
rev. 6.00 feb 22, 2005 page viii of lx item page revision (see manual for details) 1.3.3 pin functions table 1-3 pin functions 18 name and function amended xtal crystal: connects to a crystal oscillator. ? extal external clock: connects to a crystal oscillator. ? 21 avcc analog power supply: a/d converter and d/a converter power supply pin. ? avss analog ground: ground pin for a/d converter and d/a converter. ? vref analog reference power supply: a/d converter and d/a converter reference voltage input pin. ? 18, 20, 21 table 1-3 amended htxd1 * 3 hrxd1 * 3 po15 to po8 * 4 da1, da0 * 5 22 notes amended notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group. ... the h8s/2639 and h8s /2635 groups have no osc1 and osc2 pins. 3. the htxd1 and hrxd1 pins are not supported in the h8s/2635 group. 4. the po15 to 8 output are not supported in the h8s/2635 group. 5. the da1 and da0 output are not supported in the h8s/2635 group. 1.4 differences between h8s/2636, h8s/2638, h8s/2639 , h8s/2630, h8s/2635 , and h8s/2634 23 1.4 title amended
rev. 6.00 feb 22, 2005 page ix of lx item page revision (see manual for details) 1.4 differences between h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 table 1-4 comparison of product specifications 23 table 1-4 amended product specifications product type model rom ram subclock function i 2 c bus interface hcan dtc, pbc, ppg, dac power-down modes hd64f2636f no see section 23a, power- down modes hd64f2636uf 128-kbyte on-chip flash memory yes no see section 23b, power- down modes hd6432636f no see section 23a, power- down modes h8s/2636 hd6432636uf 128-kbyte mask rom 4-kbyte sram yes no see section 23b, power- down modes hd64f2638f no see section 23a, power- down modes hd64f2638uf no hd64f2638wf 256-kbyte on-chip flash memory yes yes see section 23b, power- down modes hd6432638f no see section 23a, power- down modes hd6432638uf no h8s/2638 hd6432638wf 256-kbyte mask rom 16-kbyte sram yes yes 2 channels yes see section 23b, power- down modes 24 product specifications product type model rom ram subclock function i 2 c bus interface hcan dtc, pbc, ppg, dac modes hd64f2639uf no hd64f2639wf 256-kbyte on-chip flash memory yes hd6432639uf no h8s/2639 * 1 hd6432639wf 256-kbyte mask rom 16-kbyte sram yes yes see section 23b, power- down modes hd64f2630f no see section 23a, power- down modes hd64f2630uf no hd64f2630wf 384-kbyte on-chip flash memory yes yes see section 23b, power- down modes hd6432630f no see section 23a, power- down modes hd6432630uf no h8s/2630 * 1 * 1 * 2 * 2 hd6432630wf 384-kbyte mask rom 16-kbyte sram yes yes 2 channels yes hd64f2635f 192-kbyte on-chip flash memory h8s/2635 hd6432635f 192-kbyte mask rom h8s/2634 hd6432634f 128-kbyte mask rom 6-kbyte sram yes no 1 channel no see section 23b, power- down modes power-down
rev. 6.00 feb 22, 2005 page x of lx item page revision (see manual for details) 3.3.1 mode 4 85 description amended ports 1, a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. 3.3.2 mode 5 85 description amended ports 1, a, b, and c function as an address bus, port d function as a data bus, and part of port f carries bus control signals. 3.3.3 mode 6 85 description amended ports 1, a, b, and c function as input port pins immediately after a reset. address output can be performed by setting the corresponding ddr (data direction register) bits to 1. 3.5 address map in each operating mode figure 3-4 memory map in each operating mode in the h8s/2635 91 figure 3-4 added figure 3-5 memory map in each operating mode in the h8s/2634 92 figure 3-5 added 4.1.1 exception handling types and priority 93 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... table 4-1 exception types and priority 93 note 4 amended note: 4. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 4.1.3 exception vector table table 4-2 exception vector table 95 note 3 amended note: 3. ... subclock functions are available in the u-mask and w-mask versions , and h8s/2635 group only. 4.4 interrupts 100 note added note: the dtc, pbc, and iic are not implemented in the h8s/2635 group. figure 4-4 interrupts sources and number of interrupts 100 note * 3 added hcan (4) * 3 note: 3. 2 sources in the h8s/2635 group.
rev. 6.00 feb 22, 2005 page xi of lx item page revision (see manual for details) 5.1.1 features 105 note * added ? dtc control * ... note: * the h8s/2635 group is not equipped with a dtc. 5.2 register descriptions 108 note added note: the h8s/2635 group is not equipped with a dtc, a pc brake controller, or an hcan1. 5.2.2 interrupt priority registers a to h, j to m (ipra to iprh, iprj to iprm) table 5-3 correspondence between interrupt sources and ipr setting 109 note * 3 added dtc * 3 pc break * 3 hcan channel 1 * 3 note: 3. the pc break, dtc, and hcan channel 1 are reserved in the h8s/2635 group. 5.3 interrupt sources 114 notes added notes: the h8s/2635 group is not equipped with a dtc, a pc break controller, or an hcan1. the h8s/2635 has 45 sources of internal interrupt. 117 note * 3 added dtc * 3 pc break controller * 3 5.3.3 interrupt exception handling vector table table 5-4 interrupt sources, vector addresses, and interrupt priorities 120 hcan * 3 note: 3. the dtc, pc break, and hcan1 interrupts are reserved in the h8s/2635 group. 5.6 dtc activation by interrupt 133 note added note: the dtc is not implemented in the h8s/2635 group. section 6 pc break controller (pbc) 137 note added note: the h8s/2635 group is not equipped with a pbc. 7.1 overview 149 note added note: the dtc is not implemented in the h8s/2635 group. 7.8 bus arbitration 187 note added note : the h8s/2635 group is not equipped with a dtc. section 8 data transfer controller (dtc) 189 note added n ote: the h8s/2635 group is not equipped with a dtc.
rev. 6.00 feb 22, 2005 page xii of lx item page revision (see manual for details) notes * 2, * 3 added port description pins mode 4 mode 5 mode 6 mode 7 port 3 6-bit i/o port open-drain output capability schmitt- triggered input (p35, p32) p3 irq4 irq4 irq5 irq5 5/sck1/scl0 * 1 / p34/rxd1/sda0 * 1 p33/txd1/scl1 * 1 p32/sck0/sda1 * 1 / p31/rxd0 p30/txd0 6-bit i/o port also functioning as sci (channel 0, 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1), interrupt input pins ( , ), iic (channel 0, 1) i/o pins (scl0, sda0, scl1, sda1) * 1 224 port (before) port 1 (after) port 1 * 2 (before) port 4 (after) port 4 * 3 table 9-1 port functions 226 note added note s: 1. i 2 c bus interface ? and h8s/2630. 2. the ppg output is not implemented in the h8s/2635 group. 3. the da output is not implemented in the h8s/2635 group. 9.2 port 1 227 note added note: the ppg output is not implemented in the h8s/2635 group. 9.2.3 pin functions 229 note added note: the ppg output is not implemented in the h8s/2635 group. 9.4 port 4 248 note added note: the da output is not implemented in the h8s/2635 group. section 10 16-bit timer pulse unit (tpu) 295 note added note: the h8s/2635 group is not equipped with a dtc or ppg. 10.5.2 dtc activation 369 note added note: the dtc is not implemented in the h8s/2635 and h8s/2634. 10.6.2 interrupt signal timing 377 status flag clearing timing note * added dtc * note: * the dtc is not implemented in the h8s/2635 and h8s/2634.
rev. 6.00 feb 22, 2005 page xiii of lx item page revision (see manual for details) 10.7 usage notes figure 10-56 contention between overflow and counter clearing 386 figure 10-56 amended counter clear signal tcnt input clock tcnt tgf prohibited tcfv h'ffff h'0000 figure 10-57 contention between tcnt write and overflow 387 figure 10-57 amended tcfv flag prohibited 387 interrupts and module stop mode note * added dtc * note: * the dtc is not implemented in the h8s/2635 and h8s/2634. section 11 programmable pulse generator (ppg) 389 note added note: the h8s/2635 group is not equipped with a ppg. 12.1.1 features 415 notes amended notes: 1. other than the u-mask and w-mask versions , and h8s/2635 group have eight types of counter input clock as well as wdt0. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... the h8s/2639 , h8s/2635 groups have no osc1 and osc2 pins. 12.1.2 block diagram figure 12-1 (a) block diagram of wdt0 416 note 2 amended note: 2. in the u-mask and w-mask versions , and h8s/2635 group, in subactive and subsleep modes operates as sub.
rev. 6.00 feb 22, 2005 page xiv of lx item page revision (see manual for details) 12.1.2 block diagram figure 12-1 (b) block diagram of wdt1 417 note 2 amended note: 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. 12.2.2 timer control/status register (tcsr) 420 tscr1 note 2 amended note: 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. 423 bits 2 to 0 ? clock select 2 to 0 (cks2 to cks0) note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 424 wdt0 input clock select note 2 amended note: 2. in the u-mask and w-mask versions , and h8s/2635 group, in subactive and subsleep modes operates as sub. 425 wdt1 input clock select note 2 amended note: 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 12.3.1 watchdog timer operation 429 12.5.2 changing value of pss * and cks2 to cks0 434 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... section 13 serial communication interface (sci) 435 note added note: the h8s/2635 group is not equipped with a dtc. 13.2.2 receive data register (rdr) 440 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ...
rev. 6.00 feb 22, 2005 page xv of lx item page revision (see manual for details) 13.2.4 transmit data register (tdr) 441 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 13.2.7 serial status register (ssr) 449 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 13.5 usage notes 497 note * added restrictions on use of dtc * note: * the dtc is not implemented in the h8s/2635 and h8s/2634. operation in case of mode transition ? transmission ... operation should also be stopped ... before making a transition from transmission by dtc * transfer to module stop mode, ... . to perform transmission with the dtc * after the relevant mode is cleared, ... and start dtc * transmission. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. section 14 smart card interface 503 note added note: the h8s/2635 group is not equipped with a dtc. 14.1.1 features 503 ? three interrupt sources note * added ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) * to execute data transfer note: * the dtc is not implemented in the h8s/2635 and h8s/2634. 14.3.6 data transfer operations 523 serial data transmission (except block transfer mode) note * added ... if the dtc * is activated by a txi request, the number of bytes set in the dtc can be transmitted automatically, including automatic retransmission. ... note: * the dtc is not implemented in the h8s/2635 and h8s/2634.
rev. 6.00 feb 22, 2005 page xvi of lx item page revision (see manual for details) 527 serial data reception (except block transfer mode) note * added dtc * note: * the dtc is not implemented in the h8s/2635 and h8s/2634. 14.3.6 data transfer operations 528, 529 data transfer operation by dtc * note * added note: * the dtc is not implemented in the h8s/2635 and h8s/2634. 14.4 usage notes 533 retransfer operations (except block transfer mode) ? retransfer operation when sci is in receive mode note * added [4] ... if dtc * data transfer by an rxi source is enabled, ... when the rdr data is read by the dtc * , the rdrf flag is automatically cleared to 0. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. 534 ? retransfer operation when sci is in transmit mode note * added [9] ... if data transfer by the dtc * by means of the txi source is enabled, ... when data is written to tdr by the dtc * , the tdre bit is automatically cleared to 0. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. 599, 600 ? notes on arbitration lost in master mode description added 15.4 usage notes ?? notes on loss of arbitration description deleted section 16 controller area network (hcan) 601 note added notes: the h8s/2635 group is not equipped with a dtc. only a single hcan channel, hcan0, is implemented in the h8s/2635 group.
rev. 6.00 feb 22, 2005 page xvii of lx item page revision (see manual for details) 16.1.3 pin configuration table 16-1 hcan pins 604 note * added channel 1 * notes: * the hcan1 is not supported by the h8s/2635 and h8s/2634 . 16.1.4 register configuration table 16-2 hcan registers 605 to 608 note * 2 added address * 1 channel 1 * 2 notes: 1. lower 16 bits of the address. 2. the hcan1 is not supported by the h8s/2635 and h8s/2634 . 16.2.20 module stop control register c (mstpcrc) 640 note * added mstpc2 * note: * the mstpc2 is not available and is reserved in the h8s/2635 and h8s/2634. 640 bit 2 ? module stop (mstpc2) * note: * the mstpc2 is not available and is reserved in the h8s/2635 and h8s/2634. 16.3.8 dtc interface * 665 note * added note: * the dtc is not implemented in the h8s/2635 and h8s/2634. section 17 a/d converter 671 note added note: the h8s/2635 group is not equipped with a dtc. section 18 d/a converter 695 note added note: the h8s/2635 group is not equipped with a d/a converter.
rev. 6.00 feb 22, 2005 page xviii of lx item page revision (see manual for details) section 19 motor control pwm timer 703 note added note: the h8s/2635 group is not equipped with a dtc. 19.2.2 pwm output control registers 1 and 2 (pwocr1, pwocr2) 710 19.2.3 pwm polarity registers 1 and 2 (pwpr1, pwpr2) 711 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 19.2.4 pwm counters 1 and 2 (pwcnt1, pwcnt2) 712 19.2.5 pwm cycle registers 1 and 2 (pwcyr1, pwcyr2) 713 19.2.6 pwm duty registers 1a, 1c, 1e, 1g (pwdtr1a, 1c, 1e, 1g) 714 19.2.7 pwm buffer registers 1a, 1c, 1e, 1g (pwbfr1a, 1c, 1e, 1g) 716 19.2.8 pwm duty registers 2a to 2h (pwdtr2a to pwdtr2h) 717 19.2.9 pwm buffer registers 2a to 2d (pwbfr2a to pwbfr2d) 719 19.5 usage note 725 note * added buffer register rewriting must be completed before automatic transfer by the dtc * (data transfer controller), ... note: * the dtc is not implemented in the h8s/2635 and h8s/2634. section 20 ram 727 note added note: the h8s/2635 group is not equipped with a dtc.
rev. 6.00 feb 22, 2005 page xix of lx item page revision (see manual for details) 20.1 overview 727 description amended the h8s/2636 has 4 kbytes, and h8s/2638, h8s/2639, and h8s/2630 have 16 kbytes of on-chip high-speed static ram. the h8s/2635 group has 6 kbytes of on-chip ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. 20.1.1 block diagram figure 20-1 (c) block diagram of ram (h8s/2635 group) 729 figure 20-1 (c) added 20.3 operation 730 description amended when the rame bit is set to 1, accesses to addresses h'ffe000 to h'ffefbf (for the h8s/2636), h'ffb000 to h'ffefbf (for the h8s/2638, h8s/2639, and h8s/2630) , h'ffd800 to h'ffefbf (for the h8s/2635 group), or h'ffffc0 to h'ffffff in the chip are directed to the on-chip ram. ... 20.4 usage notes 731 reserved areas description amended addresses h'ffb000 to h'ffdfff in the h8s/2636 and h'ffb000 to h'ffd7ff in the h8s/2635 group are reserved areas that cannot be read or written to. ... 21a.8.1 boot mode figure 21a-9 ram area in boot mode 758 figure amended h'ffefbf h'ffe000 h'ffe7ff h'ffe800 programming control program area (1.9 kbytes) boot program area (2 kbytes) 759 note on use of boot mode description amended ? before branching to the programming control program (ram area h'ffe 800), the chip terminates ...
rev. 6.00 feb 22, 2005 page xx of lx item page revision (see manual for details) 21a.16 note on switching from f-ztat version to mask rom version table 21a-27 registers present in f- ztat version but absent in mask rom version 796 table 21a-27 amended register abbreviation address flash memory control register 1 flmcr1 h'ff a8 flash memory control register 2 flmcr2 h'ff a9 erase block register 1 ebr1 h'ff aa erase block register 2 ebr2 h'ff ab 21b.1 overview 797 description amended the h8s/2638 and h8s/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes or 384 kbytes of on-chip mask rom. 21b.16 note on switching from f-ztat version to mask rom version table 21b-27 registers present in f- ztat version but absent in mask rom version 862 table 21b-27 amended register abbreviation address flash memory control register 1 flmcr1 h'ff a8 flash memory control register 2 flmcr2 h'ff h'ff h'ff a9 erase block register 1 ebr1 aa erase block register 2 ebr2 ab section 21c rom (h8s/2635 group) 863 to 928 section 21c added section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) 941 section 22b title amended 22b.3.2 external clock input figure 22b-6 external clock input (examples) 947 note * added (b) complementary clock input at xtal pin * note: * in the case of the h8s/2635 group, do not input a complementary clock to the xtal pin.
rev. 6.00 feb 22, 2005 page xxi of lx item page revision (see manual for details) section 23a power- down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] 951 section 23a title amended section 23b power- down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf , hd6432635f, hd64f2635f, hd6432634f] 973 note added note: the dtc, pbc, ppb, and d/a converter are not implemented in the h8s/2635 and h8s/2634.
rev. 6.00 feb 22, 2005 page xxii of lx item page revision (see manual for details) 23b.1 overview 973 description amended ... the chip operating modes are as follows: (3) subactive mode * (u-mask, w-mask version , h8s/2635 group only) ... (5) subsleep mode * (u-mask, w-mask version , h8s/2635 group only) ... (6) watch mode * (u-mask, w-mask version , h8s/2635 group only) ... 974 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... table 23b-2 lsi internal states in each mode (h8s/2639 group , h8s/2635 group) 976 note * 3 added dtc * 3 pbc * 3 ppg * 3 d/a0, 1 * 3 note: 3. the dtc, pbc, ppb, da0, and da1 are not implemented in the h8s/2635 and h8s/2634. 23.2.3 low-power control register (lpwrcr) 983 note * amended note: * bits 7 to 3 in lpwrcr are valid in the u-mask and w- mask versions , and h8s/2635 group; they are reserved bits in all other versions. 23.2.4 timer control/status register (tcsr) 985 note * amended note: 2. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions , and h8s/2635 group. in versions other than the u-mask and w-mask versions , and h8s/2635 group, however, the pss bit ... 986 bit 4 ? prescaler select (pss) note 2 amended note: 2. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions , and h8s/2635 group. in versions other than the u-mask and w-mask versions , and h8s/2635 group, however, the pss bit ...
rev. 6.00 feb 22, 2005 page xxiii of lx item page revision (see manual for details) 23b.5.1 module stop mode table 23b-5 mstp bits and corresponding on-chip supporting modules 991 note * 3 added register bit module mstpcra mstpa6 data transfer controller (dtc) * 3 mstpa5 16-bit timer pulse unit (tpu) mstpa3 programmable pulse generator (ppg) * 3 mstpa2 d/a converter (channel 0, 1) * 3 mstpcrc mstpc4 pc break controller (pbc) * 3 mstpc3 hcan0 mstpc2 hcan1 * 3 note: 3. the dtc, ppg, d/a converter, pbc, and hcan1 are not implemented in the h8s/2635 and h8s/2634. mstpa6, mstpa3, mstpa2, mstpc4, and mstpc2 are readable/ writable bits, but only 1 should be written to them. 23b.5.2 usage notes 992 note added note: the dtc is not implemented in the h8s/2635 group. 23b.6.3 setting oscillation stabilization time after clearing software standby mode 993 using a crystal oscillator description added 1. setting for h8s/2636, h8s/2638, h8s/2639, h8s/2630 set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 23b-6 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 23b-6 oscillation stabilization time settings 994 table 23b-6 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 5 mhz 4 mhz unit 0008192 states 0.410.510.680.81.01.31.62.0ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 3.2 4.1 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 6.5 8.2 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 13.1 16.4 100131072 states6.68.210.913.116.421.826.232.8 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 52.4 65.6 1 0 reserved ???????? s 1 16 states (setting prohibited) 0.8 1.0 1.3 1.6 2.0 2.6 3.2 4.0 : recommended time setting
rev. 6.00 feb 22, 2005 page xxiv of lx item page revision (see manual for details) 23b.6.3 setting oscillation stabilization time after clearing software standby mode 994 2. setting for h8s/2635, h8s/2634 set bits sts2 to sts0 so that the standby time is at least 12 ms (the oscillation stabilization time). table 23b-7 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 23b-7 oscillation stabilization time settings table 23b-7 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz unit 0008192 states 0.410.510.81.01.62.0ms 1 16384 states 0.82 1.0 1.6 2.0 3.2 4.1 1 0 32768 states 1.6 2.0 3.3 4.1 6.5 8.2 1 65536 states 3.3 4.1 6.6 8.2 13.1 16.4 100131072 states6.68.2 13.116.426.232.8 1 262144 states 13.1 16.4 26.2 32.8 52.4 65.6 1 0 reserved ??????s 1 16 states (setting prohibited) 0.8 1.0 1.6 2.0 3.2 4.0 : recommended time setting 23b.8 watch mode (u-mask, w-mask version, h8s/2635 group only) 997 23b.8 title amended 23b.9 subsleep mode (u-mask, w-mask version, h8s/2635 group only) 999 23b.9 title amended 23b.10 subactive mode (u-mask, w- mask version, h8s/2635 group only) 1000 23b.10 title amended 23b.11 direct transitions (u-mask, w-mask version, h8s/2635 group only) 1001 23b.11 title amended 23b.12 clock output disabling function table 23b-8 pin state in each processing state 1002 note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ...
rev. 6.00 feb 22, 2005 page xxv of lx item page revision (see manual for details) 23b.13 usage notes 1003 description amended 5. (h8s/2639 group, h8s/2635 group only) the subclock ( sub) is ... 24.1.4 ac characteristics table 24-4 clock timing 1012 symbol of subclock ( sub ) cycle time amended (before) f sub (after) t sub 24.2.4 ac characteristics table 24-15 clock timing 1029 symbol of subclock ( sub ) cycle time amended (before) f sub (after) t sub 24.3 h8s/2639 group , h8s/2635 group electrical characteristics 1038 note * added input voltage (xtal * , extal) note: * in the case of the h8s/2635 group, do not input a signal to the xtal pin. 24.3.3 dc characteristics table 24-24 dc characteristics 1040 table 24-24 amended, notes * 7, * 8 added hrxd1 * 7 htxd1 * 7 during a/d and d/a * 7 conversion item symbol min. typ. max. unit test conditions output high voltage pwm1a to pwm1h, pwm2a to pwm2h pwmv cc ? 0.5 ?? i oh = ? 15 ma three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 * 7 ? i tsi ? ? ? 1.0 a v in =0.5 v to v cc ? 0.5 v
rev. 6.00 feb 22, 2005 page xxvi of lx item page revision (see manual for details) 24.3.3 dc characteristics table 24-24 dc characteristics 1042 table 24-24 amended, notes * 7, * 8 added item symbol min. typ. max. unit test conditions mos input pull-up current ports a to e ? i p 50 ? 300 av in = 0 v normal operation i cc * 4 ? 75 90 ma f = 20 mhz sleep mode ? 65 80 current dissipation * 2 (h8s/2639 group) all modules stopped ? 57 ? ma f = 20 mhz (reference value) medium- speed mode ( /32) ? 49 ? subactive mode ? 0.7 1.0 ma subsleep mode ? 0.7 1.0 subclock (using 4.19 mhz crystal oscillator) watch mode ? 0.6 1.0 ? 2.0 5.0 a t a 50 c standby mode * 3 ?? 20 50 c < t a normal operation i cc * 8 ? 60 65 sleep mode ? 50 55 ma f = 20 mhz current dissipation * 2 (h8s/2635 group) all modules stopped ? 40 ? medium- speed mode ( /32) ? 45 ? ma f = 20 mhz (reference value) subactive mode ? 0.35 0.4 subsleep mode ? 0.3 0.35 watch mode ? 0.25 0.3 ma subclock (using 5.0 mhz crystal oscillator) ? 2.0 5.0 a t a 50 c standby mode ? ? 20 50 c < t a 1043 notes 7, 8 added note: 7. the hdxd1, hrxd1 pins, and d/a converter are not available in the h8s/2635 group. 8. i cc depends on v cc and f as follows: i cc (max.) = 17 ( ma ) + 0.43 ( ma /(mhz v)) v cc f (normal operation) i cc (max.) = 17 ( ma ) + 0.34 ( ma /(mhz v)) v cc f (sleep mode)
rev. 6.00 feb 22, 2005 page xxvii of lx item page revision (see manual for details) 24.3.4 ac characteristics table 24-27 clock timing 1047 table 24-27 amended condition 20mhz item symbol min. max. unit test conditions clock oscillator settling time in software standby (crystal) (h8s/2639 group) t osc2 8 ? ms figure 23a-3 figure 23b-3 clock oscillator settling time in software standby (crystal) (h8s/2635 group) 12 ? external clock output stabilization delay time t dext 2 ? ms figure 24-10 subclock oscillator frequency f sub 31.25 39.6 khz subclock ( sub ) cycle time t sub 25.6 32.0 s table 24-30 timing of on-chip supporting modules 1050, 1051 note * 1 added ppg * 1 hcan * 2 note s: 1. the ppg output is not available in the h8s/2635 group. 2. the hcan input signal is asynchronous. ... 24.3.6 d/a conversion characteristics * 1053 note * added note: * the d/a conversion is not implemented in the h8s/2635 and h8s/2634. 24.4 h8s/2630 group electrical characteristics 1056 to 1073 ?preliminary? deleted 24.4.3 dc characteristics table 24-36 dc characteristics 1059 table 24-36 amended item symbol min. typ. max. unit test conditions output high voltage pwm1a to pwm1h, pwm2a to pwm2h v oh pwmv cc ? 0.5 ?? vi oh = ? 15 ma three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 ? i tsi ? ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v 1060 item symbol min. typ. max. unit test conditions mos input pull-up current ports a to e ? i p 50 ? 300 av in = 0 v 24.4.4 ac characteristics table 24-39 clock timing 1065 symbol of subclock ( sub ) cycle time amended (before) f sub (after) t sub
rev. 6.00 feb 22, 2005 page xxviii of lx item page revision (see manual for details) 24.5.4 on-chip supporting module timing figure 24-20 ppg output timing * 1081 note * added note: * the ppg output is not implemented in the h8s/2635 and h8s/2634. 1089 note * 4 added ldm * 4 stm * 4 a.1 instruction list table a-1 instruction set 1108 note: 4. only register er0 to er6 should be used when using the stm/ ldm instruction. 1117, 1122 note * 3 added ldm * 3 stm * 3 a.2 instruction codes table a-2 instruction codes 1123 note: 3. only register er0 to er6 should be used when using the stm/ ldm instruction. 1149, 1154 note * 9 added ldm.l (ern-ern+1) * 9 ldm.l (ern-ern+2) * 9 ldm.l (ern- ern+3) * 9 @sp * 9 a.5 bus states during instruction execution table a-6 instruction execution cycles 1155 note: 9. only register er0 to er6 should be used when using the stm/ ldm instruction. b.1 address 1162, 1169 to 1180, 1182, 1183 note * 7 added dtc * 7 hcan1 * 7 pbc * 7 ppg * 7 iic0 * 4 iic1 * 4 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fec0 ipra ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int 8 h'fec1 iprb ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec2 iprc ????? ipr2 * 7 ipr1 * 7 ipr0 * 7 h'fec3 iprd ? ipr6 ipr5 ipr4 ???? h'fec4 ipre ? ipr6 * 7 ipr5 * 7 ipr4 * 7 ? ipr2 ipr1 ipr0 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ffa8 flmcr1 fwe swe esu psu ev pv e p flash 8 h'ffa9 flmcr2 fler ??????? h'ffaa ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffab ebr2 ?? eb13 * 8 eb12 * 8 eb11 * 6 eb10 * 5 eb9 eb8 h'ffac flpwcr pdwnd * 2 ???????
rev. 6.00 feb 22, 2005 page xxix of lx item page revision (see manual for details) b.1 address 1183 notes amended notes: 1. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions , and h8s/2635 group. in versions other than the u-mask and w-mask versions , and h8s/2635 group, however, the pss bit ... 2. subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the u- mask and w-mask versions , and h8s/2635 group. subclock functions may be used with the u-mask and w-mask versions , and h8s/2635 group. 3. bits dton, lson, nesel, and substp in lpwrcr are valid in the u-mask and w-mask versions , and h8s/2635 group. in versions other than the u-mask and w-mask versions , and h8s/2635 group, however, ... 5. this bit is reserved in the h8s/2636. 6. this bit is reserved in the h8s/2636 and h8s/2635. 7. these bits are not available in the h8s/2635 and h8s/2634. 8. these bits are reserved in the h8s/2636, h8s/2638, h8s/2639, and h8s/2635. these bits are valid in the h8s/2630 only. b.2 functions 1185 to 1201 mra h'ebc0 dtc * to lafmh1 h'fa1e hcan1 * note * added dtc * hcan1 * note: * this register is not available in the h8s/2635 and h8s/2634. umsr0 h'f81a hcan0, umsr1 h'fa1a hcan1 * 1 note * 2 added 15 umsr7 0 r/(w) * 2 14 umsr6 0 r/(w) * 2 13 umsr5 0 r/(w) * 2 12 umsr4 0 r/(w) * 2 11 umsr3 0 r/(w) * 2 8 umsr0 0 r/(w) * 2 10 umsr2 0 r/(w) * 2 9 umsr1 0 r/(w) * 2 7 umsr15 0 r/(w) * 2 6 umsr14 0 r/(w) * 2 5 umsr13 0 r/(w) * 2 4 umsr12 0 r/(w) * 2 3 umsr11 0 r/(w) * 2 0 umsr8 0 r/(w) * 2 2 umsr10 0 r/(w) * 2 1 umsr9 0 r/(w) * 2 bit initial value read/write bit initial value read/write 1200 notes: 1. this register is not availabel in the h8s/2635 and h8s/2634 2. only 1 can be written, to clear the flag to 0.
rev. 6.00 feb 22, 2005 page xxx of lx item page revision (see manual for details) b.2 functions 1266 to 1329 mc0[1] h'fa20 hcan1 to md15[8] h'fb2f hcan1 note added note: these registers are not available in the h8s/2635 and h8s/2634. 1341 sckcr h'fde6 system note * amended note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions , and h8s/2635 group only. ... 1344 lpwrcr h'fdec system note * amended note: * bits in 7 to 3 in lpwrcr are valid in the u-mask and w-mask versions , and h8s/2635 group; they are reserved bits in all other versions. ... 1345 bara h'fe00 pbc, barb h'fe04 pbc note 2 added note s: 1. the bit configuration ob barb is the same as for bara. 2. these registers are not available in the h8s/2635 and h8s/2634. 1346 bcra h'fe08 pbc, bcrb h'fe09 pbc note 2 added note s: 1. the bit configuration of bcrb is the same as for bcra. 2. these registers are not available in the h8s/2635 and h8s/2634. 1349 to 1356 dtcera h'fe16 dtc to dtvecr h'fe1f dtc, pcr h'fe26 ppg to ndrl h'fe2f ppg note added note: this register is not available in the h8s/2635 and h8s/2634.
rev. 6.00 feb 22, 2005 page xxxi of lx item page revision (see manual for details) b.2 functions 1360 p3odr h'fe46 port figure amended 7 ? undefined ? 6 ? undefined ? 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value read/write paodr h'fe47 port figure amended 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value read/write 1361 pbodr h'fe48 port figure amended 7 pb7odr 0 r/w 6 pb6odr 0 r/w 5 pb5odr 0 r/w 4 pb4odr 0 r/w 3 pb3odr 0 r/w 0 pb0odr 0 r/w 2 pb2odr 0 r/w 1 pb1odr 0 r/w bit initial value read/write pcodr h'fe49 port figure amended 7 pc7odr 0 r/w 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 0 pc0odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w bit initial value read/write 1382 ipra h'fec0 int to iprm h'fecc int note * 3 added dtc * 3 pc break * 3 hcan channel 1 * 3 note: 3. the dtc, pc break , and hcan are not implemented in the h8s/2635 and h8s/2634. 1387 bcrl h'fed5 bus controller figure amended 0 ? 0 r/w 2 ? 0 r/w 1 wdbe 0 r/w
rev. 6.00 feb 22, 2005 page xxxii of lx item page revision (see manual for details) b.2 functions 1388 ramer h'fedb flash memory figure amended 7 ? 0 r 6 ? 0 r 5 ? 0 r/w 4 ? 0 r/w 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit initial value read/write ram select 0 emulation not selected program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled flash memory area selection ? h8s/2636 h'ffe000 ? h'ffe3ff h'000000 ? h'0003ff h'000400 ? h'0007ff h'000800 ? h'000bff h'000c00 ? h'000fff ram area 1 kb eb0 (1 kb) eb1 (1 kb) eb2 (1 kb) eb3 (1 kb) ram2 * 0 1 rams 0 1 addresses * : don't care * : don't care block name addresses block name ram1 * 0 1 0 1 ram0 * ? h8s/2638, h8s/2639, h8s/2630 h'ffd000 ? h'ffdfff h'000000 ? h'000fff h'001000 ? h'001fff h'002000 ? h'002fff h'003000 ? h'003fff h'004000 ? h'004fff h'005000 ? h'005fff h'006000 ? h'006fff h'007000 ? h'007fff ram area 4 kb eb0 (4 kb) eb1 (4 kb) eb2 (4 kb) eb3 (4 kb) eb4 (4 kb) eb5 (4 kb) eb6 (4 kb) eb7 (4 kb) rams 0 1 ram2 * 0 1 ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1 * : don't care addresses block name ? h8s/2635 h'ffd800 ? h'ffe7ff h'000000 ? h'000fff h'001000 ? h'001fff h'002000 ? h'002fff h'003000 ? h'003fff h'004000 ? h'004fff h'005000 ? h'005fff h'006000 ? h'006fff h'007000 ? h'007fff ram area 4 kb eb0 (4 kb) eb1 (4 kb) eb2 (4 kb) eb3 (4 kb) eb4 (4 kb) eb5 (4 kb) eb6 (4 kb) eb7 (4 kb) rams 0 1 ram2 * 0 1 ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1
rev. 6.00 feb 22, 2005 page xxxiii of lx item page revision (see manual for details) b.2 functions 1438 tcsr1 h'ffa2(w), h'ffa2(r) wdt1 figure amended bit initial value read/write 7 ovf 0 r/(w) * 1 6 wt/ it 0 r/w 5 tme 0 r/w 4 pss * 2 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w timer enable 0 tcnt is initialized to h'00 and halted tcnt counts 1 overflow flag 0 1 timer mode select 0 interval timer mode: wdt1 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows watchdog timer mode: wdt1 requests a reset or an nmi interrupt from the cpu when the tcnt overflows 1 prescaler select 0 the tcnt counts frequency-division clock pulses of the based prescaler (psm) the tcnt counts frequency-division clock pulses of the sub * -based prescaler (pss) 1 reset or nmi 0 nmi request internal reset request 1 clock select 2 to 0 /2 /64 /128 /512 /2048 /8192 /32768 /131072 sub/2 * 2 sub/4 * 2 sub/8 * 2 sub/16 * 2 sub/32 * 2 sub/64 * 2 sub/128 * 2 sub/256 * 2 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1 s 2 s 0 cks2 0 pss cks1 cks0 clock overflow period * 1 (where = 20 mhz) (where sub * 2 = 32.768 khz) 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 01 1 0 1 0 1 0 1 0 1 1 0 1 note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions, and in them the pss bit is reserved. only 0 should be written to this bit. [clearing conditions] ? write 0 in the tme bit (only applies to wdt1) ? read tcsr * when ovf = 1, then write 0 in ovf [setting condition] ? when tcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset ) notes: 1. an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only, but are not available in the other versions. notes: tcsr1 register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes o n register access. 1. only 0 can be written, to clear the flag. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only. note: * when interval timer interrupts are disabled and ovf is polled, read the ovf = 1 state at least twice. 1439 dadr0 h'ffa4 d/a0, 1, dadr1 h'ffa5 d/a0, 1 note added note: these registers are not available in the h8s/2635 and h8s/2634.
rev. 6.00 feb 22, 2005 page xxxiv of lx item page revision (see manual for details) b.2 functions 1440 dacr01 h'ffa6 d/a0, 1 note added note: this register is not available in the h8s/2635 and h8s/2634. 1443 ebr1 h'ffaa flash memory, ebr2 h'ffab flash memory figure amended 15 eb7 0 r/w 14 eb6 0 r/w 13 eb5 0 r/w 12 eb4 0 r/w 11 eb3 0 r/w 8 eb0 0 r/w 10 eb2 0 r/w 9 eb1 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 eb13 * 3 0 r/w 4 eb12 * 3 0 r/w 3 eb11 * 2 0 r/w 0 eb8 0 r/w 2 eb10 * 1 0 r/w 1 eb9 0 r/w bit initial value read/write ebr1 bit initial value read/write notes: 1. on the h8s/2636, these bits are reserved. 2. reserved in the h8s/2636 and h8s/2635. 3. reserved in the h8s/2638, h8s/2639, and h8s/2635. ebr2 specify the flash memory erase area block (size) ? h8s/2636 ? h8s/2638, h8s/2639 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) eb11 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff h'030000 to h'03ffff block (size) ? h8s/2635 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff block (size) ? h8s/2630 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) eb11 (64 kbytes) eb12 (64 kbytes) eb13 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff h'030000 to h'03ffff h'040000 to h'04ffff h'050000 to h'05ffff block (size) addresses eb0 (1 kbyte) eb1 (1 kbyte) eb2 (1 kbyte) eb3 (1 kbyte) eb4 (28 kbytes) eb5 (16 kbytes) eb6 (8 kbytes) eb7 (8 kbytes) eb8 (32 kbytes) eb9 (32 kbytes) h'000000 to h'0003ff h'000400 to h'0007ff h'000800 to h'000bff h'000c00 to h'000fff h'001000 to h'007fff h'008000 to h'00bfff h'00c000 to h'00dfff h'00e000 to h'00ffff h'010000 to h'017fff h'018000 to h'01ffff
rev. 6.00 feb 22, 2005 page xxxv of lx item page revision (see manual for details) c.1 port 1 block diagrams figure c-1 (a) port 1 block diagram (pins p10 and p11) to figure c-1 (f) port 1 block diagram (pin p17) 1448 to 1453 note * 2 added ppg module * 2 note s: 1. priority order: ... 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. c.3 port 4 block diagram figure c-3 (b) port 4 block diagram (pins p46, p47) 1460 note * added d/a converter module * notes: the d/a converter is not implemented in the h8s/2635 and h8s/2634. n = 6, 7 d.1 port states in each mode table d-1 i/o port states in each processing state 1479, 1480 table d-1 amended port name pin name pf6 hwr rd as / pf5/ pf4/ port na me pin name pf3 lwr /
rev. 6.00 feb 22, 2005 page xxxvi of lx item page revision (see manual for details) f. product code lineup table f-1 h8s/2636, h8s/2638, h8s/2639, and h8s/2630 product code lineup 1483 table f-1 amended product type product code mark code functions packages h8s/2630 f-ztat version hd64f2630 hd64f2630f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd64f2630uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd64f2630wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432630 hd6432630f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd6432630uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432630wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) h8s/2635 f-ztat version hd64f2635 hd64f2635f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432635 * hd6432635f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432634 * hd6432634f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) note: * under development g package dimensions figure g-1 fp-128b package dimensions 1484 figure g-1 replaced
rev. 6.00 feb 22, 2005 page xxxvii of lx contents section 1 overview ............................................................................................................. 1 1.1 overview.................................................................................................................... ....... 1 1.2 internal block diagram..................................................................................................... 6 1.3 pin description ............................................................................................................. .... 9 1.3.1 pin arrangement.................................................................................................. 9 1.3.2 pin functions in each operating mode ............................................................... 13 1.3.3 pin functions ....................................................................................................... 18 1.4 differences between h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 ....................................................................................................................... ... 23 section 2 cpu ...................................................................................................................... 25 2.1 overview.................................................................................................................... ....... 25 2.1.1 features................................................................................................................ 25 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu .................................. 26 2.1.3 differences from h8/300 cpu ............................................................................ 27 2.1.4 differences from h8/300h cpu ......................................................................... 28 2.2 cpu operating modes...................................................................................................... 28 2.3 address space............................................................................................................... .... 33 2.4 register configuration...................................................................................................... 34 2.4.1 overview.............................................................................................................. 34 2.4.2 general registers................................................................................................. 35 2.4.3 control registers ................................................................................................. 36 2.4.4 initial register values ......................................................................................... 38 2.5 data formats................................................................................................................ ..... 39 2.5.1 general register data formats............................................................................ 39 2.5.2 memory data formats......................................................................................... 41 2.6 instruction set............................................................................................................. ...... 42 2.6.1 overview.............................................................................................................. 42 2.6.2 instructions and addressing modes..................................................................... 43 2.6.3 table of instructions classified by function ...................................................... 45 2.6.4 basic instruction formats .................................................................................... 54 2.7 addressing modes and effective address calculation..................................................... 56 2.7.1 addressing mode................................................................................................. 56 2.7.2 effective address calculation ............................................................................. 59 2.8 processing states ........................................................................................................... ... 63 2.8.1 overview.............................................................................................................. 63 2.8.2 reset state ........................................................................................................... 64
rev. 6.00 feb 22, 2005 page xxxv iii of lx 2.8.3 exception-handling state .................................................................................... 65 2.8.4 program execution state ..................................................................................... 68 2.8.5 bus-released state .............................................................................................. 68 2.8.6 power-down state ............................................................................................... 68 2.9 basic timing ..................................................................................................................... 69 2.9.1 overview.............................................................................................................. 69 2.9.2 on-chip memory (rom, ram)......................................................................... 69 2.9.3 on-chip supporting module access t iming ...................................................... 71 2.9.4 on-chip hcan module access t iming ............................................................. 73 2.9.5 port h and j register access t iming .................................................................. 75 2.9.6 external address space access t iming .............................................................. 76 2.10 usage note ................................................................................................................. ...... 77 2.10.1 tas instruction ................................................................................................... 77 2.10.2 stm/ldm instructions ....................................................................................... 77 2.10.3 caution to observe when using bit manipulation instructions .......................... 77 section 3 mcu operating modes .................................................................................. 79 3.1 overview.................................................................................................................... ....... 79 3.1.1 operating mode selection ................................................................................... 79 3.1.2 register configuration......................................................................................... 80 3.2 register descriptions....................................................................................................... .80 3.2.1 mode control register (mdcr) ......................................................................... 80 3.2.2 system control register (syscr)...................................................................... 81 3.2.3 pin function control register (pfcr) ................................................................ 83 3.3 operating mode descriptions ........................................................................................... 85 3.3.1 mode 4................................................................................................................. 85 3.3.2 mode 5................................................................................................................. 85 3.3.3 mode 6................................................................................................................. 85 3.3.4 mode 7................................................................................................................. 86 3.4 pin functions in each operating mode ............................................................................ 86 3.5 address map in each operating mode............................................................................. 87 section 4 exception handling ......................................................................................... 93 4.1 overview.................................................................................................................... ....... 93 4.1.1 exception handling types and priority............................................................... 93 4.1.2 exception handling operation ............................................................................ 94 4.1.3 exception vector table ....................................................................................... 94 4.2 reset ....................................................................................................................... .......... 96 4.2.1 overview.............................................................................................................. 96 4.2.2 reset sequence .................................................................................................... 96
rev. 6.00 feb 22, 2005 page xxxix of lx 4.2.3 interrupts after reset............................................................................................ 98 4.2.4 state of on-chip supporting modules after reset release ................................. 99 4.3 traces...................................................................................................................... .......... 99 4.4 interrupts.................................................................................................................. ......... 100 4.5 trap instruction ............................................................................................................ .... 101 4.6 stack status after exception handling.............................................................................. 102 4.7 notes on use of the stack................................................................................................. 10 3 section 5 interrupt controller .......................................................................................... 105 5.1 overview.................................................................................................................... ....... 105 5.1.1 features................................................................................................................ 10 5 5.1.2 block diagram..................................................................................................... 106 5.1.3 pin configuration ................................................................................................ 107 5.1.4 register configuration......................................................................................... 107 5.2 register descriptions....................................................................................................... . 108 5.2.1 system control register (syscr)...................................................................... 108 5.2.2 interrupt priority registers a to h, j to m (ipra to iprh, iprj to iprm) ....... 109 5.2.3 irq enable register (ier) .................................................................................. 110 5.2.4 irq sense control registers h and l (iscrh, iscrl)..................................... 111 5.2.5 irq status register (isr).................................................................................... 112 5.3 interrupt sources........................................................................................................... .... 114 5.3.1 external interrupts ............................................................................................... 114 5.3.2 internal interrupts ................................................................................................ 116 5.3.3 interrupt exception handling vector table......................................................... 116 5.4 interrupt operation ......................................................................................................... .. 120 5.4.1 interrupt control modes and interrupt operation................................................ 120 5.4.2 interrupt control mode 0..................................................................................... 124 5.4.3 interrupt control mode 2..................................................................................... 126 5.4.4 interrupt exception handling sequence .............................................................. 128 5.4.5 interrupt response times .................................................................................... 129 5.5 usage notes ................................................................................................................. ..... 130 5.5.1 contention between interrupt generation and disabling..................................... 130 5.5.2 instructions that disable interrupts...................................................................... 131 5.5.3 times when interrupts are disabled ................................................................... 131 5.5.4 interrupts during execution of eepmov instruction ......................................... 132 5.5.5 irq interrupts...................................................................................................... 132 5.5.6 notes on use of nmi interrupt............................................................................ 132 5.6 dtc activation by interrupt............................................................................................. 133 5.6.1 overview.............................................................................................................. 133 5.6.2 block diagram..................................................................................................... 133
rev. 6.00 feb 22, 2005 page xl of lx 5.6.3 operation ............................................................................................................. 134 section 6 pc break controller (pbc) ........................................................................... 137 6.1 overview.................................................................................................................... ....... 137 6.1.1 features................................................................................................................ 13 7 6.1.2 block diagram..................................................................................................... 138 6.1.3 register configuration......................................................................................... 139 6.2 register descriptions....................................................................................................... . 139 6.2.1 break address register a (bara) ..................................................................... 139 6.2.2 break address register b (barb) ..................................................................... 140 6.2.3 break control register a (bcra) ...................................................................... 140 6.2.4 break control register b (bcrb) ...................................................................... 142 6.2.5 module stop control register c (mstpcrc) ................................................... 142 6.3 operation ................................................................................................................... ....... 143 6.3.1 pc break interrupt due to instruction fetch ....................................................... 143 6.3.2 pc break interrupt due to data access .............................................................. 144 6.3.3 notes on pc break interrupt handling................................................................ 144 6.3.4 operation in transitions to power-down modes ................................................ 145 6.3.5 pc break operation in continuous data transfer............................................... 146 6.3.6 when instruction execution is delayed by one state......................................... 147 6.3.7 additional notes.................................................................................................. 148 section 7 bus controller ................................................................................................... 149 7.1 overview.................................................................................................................... ....... 149 7.1.1 features................................................................................................................ 14 9 7.1.2 block diagram..................................................................................................... 150 7.1.3 pin configuration ................................................................................................ 151 7.1.4 register configuration......................................................................................... 151 7.2 register descriptions....................................................................................................... . 152 7.2.1 bus width control register (abwcr)............................................................... 152 7.2.2 access state control register (astcr) ............................................................. 153 7.2.3 wait control registers h and l (wcrh, wcrl).............................................. 154 7.2.4 bus control register h (bcrh) ......................................................................... 158 7.2.5 bus control register l (bcrl) .......................................................................... 160 7.2.6 pin function control register (pfcr) ................................................................ 161 7.3 overview of bus control.................................................................................................. 163 7.3.1 area partitioning.................................................................................................. 163 7.3.2 bus specifications ............................................................................................... 164 7.3.3 memory interfaces............................................................................................... 165 7.3.4 interface specifications for each area ................................................................ 166
rev. 6.00 feb 22, 2005 page xli of lx 7.4 basic bus interface ......................................................................................................... .. 167 7.4.1 overview.............................................................................................................. 167 7.4.2 data size and data alignment............................................................................. 167 7.4.3 valid strobes ....................................................................................................... 169 7.4.4 basic t iming ........................................................................................................ 170 7.4.5 wait control ........................................................................................................ 178 7.5 burst rom interface ........................................................................................................ 1 79 7.5.1 overview.............................................................................................................. 179 7.5.2 basic t iming ........................................................................................................ 179 7.5.3 wait control ........................................................................................................ 181 7.6 idle cycle.................................................................................................................. ........ 181 7.6.1 operation ............................................................................................................. 181 7.6.2 pin states during idle cycles .............................................................................. 185 7.7 write data buffer function .............................................................................................. 186 7.8 bus arbitration ............................................................................................................. .... 187 7.8.1 overview.............................................................................................................. 187 7.8.2 operation ............................................................................................................. 187 7.8.3 bus transfer t iming ............................................................................................ 187 7.9 resets and the bus controller........................................................................................... 188 section 8 data transfer controller (dtc) ................................................................... 189 8.1 overview.................................................................................................................... ....... 189 8.1.1 features................................................................................................................ 18 9 8.1.2 block diagram..................................................................................................... 190 8.1.3 register configuration......................................................................................... 191 8.2 register descriptions....................................................................................................... . 192 8.2.1 dtc mode register a (mra) ............................................................................ 192 8.2.2 dtc mode register b (mrb)............................................................................. 194 8.2.3 dtc source address register (sar).................................................................. 195 8.2.4 dtc destination address register (dar).......................................................... 195 8.2.5 dtc transfer count register a (cra) .............................................................. 195 8.2.6 dtc transfer count register b (crb)............................................................... 196 8.2.7 dtc enable registers (dtcer)......................................................................... 196 8.2.8 dtc vector register (dtvecr)........................................................................ 197 8.2.9 module stop control register a (mstpcra) ................................................... 199 8.3 operation ................................................................................................................... ....... 200 8.3.1 overview.............................................................................................................. 200 8.3.2 activation sources............................................................................................... 202 8.3.3 dtc vector table ............................................................................................... 204 8.3.4 location of register information in address space ............................................ 208
rev. 6.00 feb 22, 2005 page xlii of lx 8.3.5 normal mode....................................................................................................... 209 8.3.6 repeat mode........................................................................................................ 210 8.3.7 block transfer mode........................................................................................... 211 8.3.8 chain transfer ..................................................................................................... 213 8.3.9 operation t iming................................................................................................. 214 8.3.10 number of dtc execution states ....................................................................... 215 8.3.11 procedures for using dtc .................................................................................. 217 8.3.12 examples of use of the dtc............................................................................... 218 8.4 interrupts.................................................................................................................. ......... 221 8.5 usage notes ................................................................................................................. ..... 221 section 9 i/o ports .............................................................................................................. 223 9.1 overview.................................................................................................................... ....... 223 9.2 port 1...................................................................................................................... ........... 227 9.2.1 overview.............................................................................................................. 227 9.2.2 register configuration......................................................................................... 228 9.2.3 pin functions ....................................................................................................... 229 9.3 port 3...................................................................................................................... ........... 242 9.3.1 overview.............................................................................................................. 242 9.3.2 register configuration......................................................................................... 243 9.3.3 pin functions ....................................................................................................... 245 9.4 port 4...................................................................................................................... ........... 248 9.4.1 overview.............................................................................................................. 248 9.4.2 register configuration......................................................................................... 249 9.4.3 pin functions ....................................................................................................... 249 9.5 port 9...................................................................................................................... ........... 250 9.5.1 overview.............................................................................................................. 250 9.5.2 register configuration......................................................................................... 251 9.5.3 pin functions ....................................................................................................... 251 9.6 port a...................................................................................................................... .......... 252 9.6.1 overview.............................................................................................................. 252 9.6.2 register configuration......................................................................................... 253 9.6.3 pin functions ....................................................................................................... 256 9.6.4 pin functions ....................................................................................................... 258 9.6.5 mos input pull-up function .............................................................................. 259 9.7 port b...................................................................................................................... .......... 260 9.7.1 overview.............................................................................................................. 260 9.7.2 register configuration......................................................................................... 261 9.7.3 pin functions ....................................................................................................... 264 9.7.4 mos input pull-up function .............................................................................. 265
rev. 6.00 feb 22, 2005 page xliii of lx 9.8 port c...................................................................................................................... .......... 266 9.8.1 overview.............................................................................................................. 266 9.8.2 register configuration......................................................................................... 267 9.8.3 pin functions for each mode .............................................................................. 270 9.8.4 mos input pull-up function .............................................................................. 272 9.9 port d...................................................................................................................... .......... 273 9.9.1 overview.............................................................................................................. 273 9.9.2 register configuration......................................................................................... 274 9.9.3 pin functions ....................................................................................................... 276 9.9.4 mos input pull-up function .............................................................................. 277 9.10 port e ..................................................................................................................... ........... 278 9.10.1 overview.............................................................................................................. 278 9.10.2 register configuration......................................................................................... 279 9.10.3 pin functions ....................................................................................................... 281 9.10.4 mos input pull-up function .............................................................................. 283 9.11 port f ..................................................................................................................... ........... 284 9.11.1 overview.............................................................................................................. 284 9.11.2 register configuration......................................................................................... 285 9.11.3 pin functions ....................................................................................................... 287 9.12 port h..................................................................................................................... ........... 289 9.12.1 overview.............................................................................................................. 289 9.12.2 register configuration......................................................................................... 290 9.12.3 pin functions ....................................................................................................... 291 9.13 port j ..................................................................................................................... ............ 292 9.13.1 overview.............................................................................................................. 292 9.13.2 register configuration......................................................................................... 293 9.13.3 pin functions ....................................................................................................... 294 section 10 16-bit timer pulse unit (tpu) .................................................................. 295 10.1 overview................................................................................................................... ........ 295 10.1.1 features................................................................................................................ 2 95 10.1.2 block diagram..................................................................................................... 299 10.1.3 pin configuration ................................................................................................ 300 10.1.4 register configuration......................................................................................... 302 10.2 register descriptions...................................................................................................... .. 304 10.2.1 timer control register (tcr)............................................................................. 304 10.2.2 timer mode register (tmdr)............................................................................ 309 10.2.3 timer i/o control register (tior)..................................................................... 311 10.2.4 timer interrupt enable register (tier).............................................................. 325 10.2.5 timer status register (tsr)................................................................................ 328
rev. 6.00 feb 22, 2005 page xliv of lx 10.2.6 timer counter (tcnt)........................................................................................ 332 10.2.7 timer general register (tgr) ............................................................................ 333 10.2.8 timer start register (tstr) ............................................................................... 334 10.2.9 timer synchro register (tsyr) ......................................................................... 335 10.2.10 module stop control register a (mstpcra) ................................................... 336 10.3 interface to bus master.................................................................................................... . 337 10.3.1 16-bit registers ................................................................................................... 337 10.3.2 8-bit registers ..................................................................................................... 337 10.4 operation .................................................................................................................. ........ 339 10.4.1 overview.............................................................................................................. 339 10.4.2 basic functions.................................................................................................... 340 10.4.3 synchronous operation ....................................................................................... 346 10.4.4 buffer operation.................................................................................................. 348 10.4.5 cascaded operation ............................................................................................. 352 10.4.6 pwm modes........................................................................................................ 354 10.4.7 phase counting mode.......................................................................................... 360 10.5 interrupts................................................................................................................. .......... 367 10.5.1 interrupt sources and priorities ........................................................................... 367 10.5.2 dtc activation ................................................................................................... 369 10.5.3 a/d converter activation.................................................................................... 369 10.6 operation t iming .............................................................................................................. 370 10.6.1 input/output t iming ............................................................................................ 370 10.6.2 interrupt signal t iming ....................................................................................... 374 10.7 usage notes ................................................................................................................ ...... 378 section 11 programmable pulse generator (ppg) .................................................... 389 11.1 overview................................................................................................................... ........ 389 11.1.1 features................................................................................................................ 3 89 11.1.2 block diagram..................................................................................................... 390 11.1.3 pin configuration ................................................................................................ 391 11.1.4 registers .............................................................................................................. 39 2 11.2 register descriptions...................................................................................................... .. 393 11.2.1 next data enable registers h and l (nderh, nderl)................................... 393 11.2.2 output data registers h and l (podrh, podrl)............................................ 394 11.2.3 next data registers h and l (ndrh, ndrl).................................................... 395 11.2.4 notes on ndr access ......................................................................................... 395 11.2.5 ppg output control register (pcr) ................................................................... 397 11.2.6 ppg output mode register (pmr) ..................................................................... 399 11.2.7 port 1 data direction register (p1ddr)............................................................. 402 11.2.8 module stop control register a (mstpcra) ................................................... 402
rev. 6.00 feb 22, 2005 page xlv of lx 11.3 operation .................................................................................................................. ........ 403 11.3.1 overview.............................................................................................................. 403 11.3.2 output t iming ..................................................................................................... 404 11.3.3 normal pulse output ........................................................................................... 405 11.3.4 non-overlapping pulse output ........................................................................... 407 11.3.5 inverted pulse output .......................................................................................... 410 11.3.6 pulse output triggered by input capture............................................................ 411 11.4 usage notes ................................................................................................................ ...... 412 section 12 watchdog timer ............................................................................................. 415 12.1 overview................................................................................................................... ........ 415 12.1.1 features................................................................................................................ 4 15 12.1.2 block diagram..................................................................................................... 416 12.1.3 pin configuration ................................................................................................ 418 12.1.4 register configuration......................................................................................... 418 12.2 register descriptions...................................................................................................... .. 419 12.2.1 timer counter (tcnt)........................................................................................ 419 12.2.2 timer control/status register (tcsr)................................................................ 420 12.2.3 reset control/status register (rstcsr)............................................................ 426 12.2.4 notes on register access .................................................................................... 427 12.3 operation .................................................................................................................. ........ 429 12.3.1 watchdog timer operation ................................................................................. 429 12.3.2 interval timer operation ..................................................................................... 431 12.3.3 t iming of setting overflow flag (ovf) ............................................................. 431 12.3.4 t iming of setting of watc hdog timer overflow flag (wovf) ......................... 432 12.4 interrupts................................................................................................................. .......... 433 12.5 usage notes ............................................................................................................... ....... 433 12.5.1 contention between timer counter (tcnt) write and increment..................... 433 12.5.2 changing value of pss and cks2 to cks0 ....................................................... 434 12.5.3 switching between watchdog timer mode and interval timer mode................ 434 12.5.4 internal reset in watchdog timer mode............................................................. 434 12.5.5 ovf flag clearing in interval timer mode ........................................................ 434 section 13 serial communication interface (sci) .................................................... 435 13.1 overview................................................................................................................... ........ 435 13.1.1 features................................................................................................................ 4 35 13.1.2 block diagram..................................................................................................... 437 13.1.3 pin configuration ................................................................................................ 438 13.1.4 register configuration......................................................................................... 439 13.2 register descriptions...................................................................................................... .. 440
rev. 6.00 feb 22, 2005 page xlvi of lx 13.2.1 receive shift register (rsr) .............................................................................. 440 13.2.2 receive data register (rdr).............................................................................. 440 13.2.3 transmit shift register (tsr)............................................................................. 441 13.2.4 transmit data register (tdr) ............................................................................ 441 13.2.5 serial mode register (smr) ............................................................................... 442 13.2.6 serial control register (scr) ............................................................................. 445 13.2.7 serial status register (ssr) ................................................................................ 449 13.2.8 bit rate register (brr) ...................................................................................... 453 13.2.9 smart card mode register (scmr).................................................................... 460 13.2.10 module stop control register b (mstpcrb) ................................................... 461 13.3 operation .................................................................................................................. ........ 463 13.3.1 overview.............................................................................................................. 463 13.3.2 operation in asynchronous mode ....................................................................... 465 13.3.3 multiprocessor communication function ........................................................... 476 13.3.4 operation in clocked synchronous mode........................................................... 484 13.4 sci interrupts............................................................................................................. ....... 493 13.5 usage notes ................................................................................................................ ...... 494 section 14 smart card interface ..................................................................................... 503 14.1 overview................................................................................................................... ........ 503 14.1.1 features................................................................................................................ 5 03 14.1.2 block diagram..................................................................................................... 504 14.1.3 pin configuration ................................................................................................ 505 14.1.4 register configuration......................................................................................... 506 14.2 register descriptions...................................................................................................... .. 507 14.2.1 smart card mode register (scmr).................................................................... 507 14.2.2 serial status register (ssr) ................................................................................ 509 14.2.3 serial mode register (smr) ............................................................................... 511 14.2.4 serial control register (scr) ............................................................................. 513 14.3 operation .................................................................................................................. ........ 514 14.3.1 overview.............................................................................................................. 514 14.3.2 pin connections................................................................................................... 514 14.3.3 data format ......................................................................................................... 516 14.3.4 register settings .................................................................................................. 518 14.3.5 clock.................................................................................................................... 520 14.3.6 data transfer operations..................................................................................... 522 14.3.7 operation in gsm mode ..................................................................................... 529 14.3.8 operation in block transfer mode ...................................................................... 530 14.4 usage notes ................................................................................................................ ...... 531
rev. 6.00 feb 22, 2005 page xlvii of lx section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) ........................... 535 15.1 overview................................................................................................................... ........ 535 15.1.1 features................................................................................................................ 5 35 15.1.2 block diagram..................................................................................................... 536 15.1.3 input/output pins................................................................................................. 538 15.1.4 register configuration......................................................................................... 539 15.2 register descriptions...................................................................................................... .. 540 15.2.1 i 2 c bus data register (icdr)............................................................................. 540 15.2.2 slave address register (sar)............................................................................. 543 15.2.3 second slave address register (sarx) ............................................................. 544 15.2.4 i 2 c bus mode register (icmr) .......................................................................... 545 15.2.5 i 2 c bus control register (iccr) ........................................................................ 549 15.2.6 i 2 c bus status register (icsr) ........................................................................... 557 15.2.7 serial control register x (scrx)....................................................................... 563 15.2.8 ddc switch register (ddcswr)...................................................................... 564 15.2.9 module stop control register b (mstpcrb) ................................................... 565 15.3 operation .................................................................................................................. ........ 566 15.3.1 i 2 c bus data format............................................................................................ 566 15.3.2 initial setting ....................................................................................................... 568 15.3.3 master transmit operation.................................................................................. 568 15.3.4 master receive operation ................................................................................... 572 15.3.5 slave receive operation...................................................................................... 577 15.3.6 slave transmit operation .................................................................................... 582 15.3.7 iric setting t iming and scl control ................................................................ 585 15.3.8 operation using the dtc .................................................................................... 586 15.3.9 noise canceler..................................................................................................... 587 15.3.10 initialization of internal state .............................................................................. 587 15.4 usage notes ................................................................................................................ ...... 589 section 16 controller area network (hcan) ........................................................... 601 16.1 overview................................................................................................................... ........ 601 16.1.1 features................................................................................................................ 6 01 16.1.2 block diagram..................................................................................................... 603 16.1.3 pin configuration ................................................................................................ 604 16.1.4 register configuration......................................................................................... 605 16.2 register descriptions...................................................................................................... .. 609 16.2.1 master control register (mcr) .......................................................................... 609 16.2.2 general status register (gsr) ............................................................................ 610 16.2.3 bit configuration register (bcr) ....................................................................... 612
rev. 6.00 feb 22, 2005 page xlviii of lx 16.2.4 mailbox configuration register (mbcr) ........................................................... 614 16.2.5 transmit wait register (txpr) .......................................................................... 615 16.2.6 transmit wait cancel register (txcr).............................................................. 616 16.2.7 transmit acknowledge register (txack) ........................................................ 617 16.2.8 abort acknowledge register (aback) ............................................................. 618 16.2.9 receive complete register (rxpr).................................................................... 619 16.2.10 remote request register (rfpr) ....................................................................... 620 16.2.11 interrupt register (irr)....................................................................................... 621 16.2.12 mailbox interrupt mask register (mbimr) ....................................................... 626 16.2.13 interrupt mask register (imr) ............................................................................ 627 16.2.14 receive error counter (rec).............................................................................. 630 16.2.15 transmit error counter (tec) ............................................................................ 630 16.2.16 unread message status register (umsr)........................................................... 631 16.2.17 local acceptance filter masks (lafml, lafmh)........................................... 632 16.2.18 message control (mc0 to mc15) ....................................................................... 634 16.2.19 message data (md0 to md15) ........................................................................... 638 16.2.20 module stop control register c (mstpcrc) ................................................... 640 16.3 operation .................................................................................................................. ........ 641 16.3.1 hardware and software resets ............................................................................ 641 16.3.2 initialization after hardware reset ...................................................................... 644 16.3.3 transmit mode .................................................................................................... 649 16.3.4 receive mode ...................................................................................................... 655 16.3.5 hcan sleep mode.............................................................................................. 661 16.3.6 hcan halt mode................................................................................................ 663 16.3.7 interrupt interface ................................................................................................ 663 16.3.8 dtc interface ...................................................................................................... 665 16.4 can bus interface .......................................................................................................... . 666 16.5 usage notes ................................................................................................................ ...... 667 section 17 a/d converter ................................................................................................. 671 17.1 overview................................................................................................................... ........ 671 17.1.1 features................................................................................................................ 6 71 17.1.2 block diagram..................................................................................................... 672 17.1.3 pin configuration ................................................................................................ 673 17.1.4 register configuration......................................................................................... 674 17.2 register descriptions...................................................................................................... .. 675 17.2.1 a/d data registers a to d (addra to addrd) ............................................. 675 17.2.2 a/d control/status register (adcsr) ............................................................... 676 17.2.3 a/d control register (adcr) ............................................................................ 679 17.2.4 module stop control register a (mstpcra) ................................................... 680
rev. 6.00 feb 22, 2005 page xlix of lx 17.3 interface to bus master.................................................................................................... . 681 17.4 operation .................................................................................................................. ........ 682 17.4.1 single mode (scan = 0) .................................................................................... 682 17.4.2 scan mode (scan = 1)....................................................................................... 684 17.4.3 input sampling and a/d conversion time ......................................................... 686 17.4.4 external trigger input t iming ............................................................................. 687 17.5 interrupts................................................................................................................. .......... 688 17.6 usage notes ................................................................................................................ ...... 689 section 18 d/a converter ................................................................................................. 695 18.1 overview................................................................................................................... ........ 695 18.1.1 features................................................................................................................ 6 95 18.1.2 block diagram..................................................................................................... 696 18.1.3 input and output pins .......................................................................................... 697 18.1.4 register configuration......................................................................................... 697 18.2 register descriptions...................................................................................................... .. 698 18.2.1 d/a data registers 0, 1 (dadr0, dadr1) ....................................................... 698 18.2.2 d/a control register 01 (dacr01) ................................................................... 698 18.2.3 module stop control register a (mstpcra) ................................................... 700 18.3 operation .................................................................................................................. ........ 701 section 19 motor control pwm timer ........................................................................ 703 19.1 overview................................................................................................................... ........ 703 19.1.1 features................................................................................................................ 7 03 19.1.2 block diagram..................................................................................................... 704 19.1.3 pin configuration ................................................................................................ 706 19.1.4 register configuration......................................................................................... 707 19.2 register descriptions...................................................................................................... .. 708 19.2.1 pwm control registers 1 and 2 (pwcr1, pwcr2) .......................................... 708 19.2.2 pwm output control registers 1 and 2 (pwocr1, pwocr2) ........................ 710 19.2.3 pwm polarity registers 1 and 2 (pwpr1, pwpr2) .......................................... 711 19.2.4 pwm counters 1 and 2 (pwcnt1, pwcnt2) .................................................. 712 19.2.5 pwm cycle registers 1 and 2 (pwcyr1, pwcyr2) ....................................... 713 19.2.6 pwm duty registers 1a, 1c, 1e, 1g (pwdtr1a, 1c, 1e, 1g) ....................... 714 19.2.7 pwm buffer registers 1a, 1c, 1e, 1g (pwbfr1a, 1c, 1e, 1g) ..................... 716 19.2.8 pwm duty registers 2a to 2h (pwdtr2a to pwdtr2h) ............................. 717 19.2.9 pwm buffer registers 2a to 2d (pwbfr2a to pwbfr2d) ........................... 719 19.2.10 module stop control register d (mstpcrd) ................................................... 720 19.3 bus master interface....................................................................................................... .. 721 19.3.1 16-bit data registers........................................................................................... 721
rev. 6.00 feb 22, 2005 page l of lx 19.3.2 8-bit data registers............................................................................................. 721 19.4 operation .................................................................................................................. ........ 722 19.4.1 pwm channel 1 operation.................................................................................. 722 19.4.2 pwm channel 2 operation.................................................................................. 723 19.5 usage note ................................................................................................................. ...... 725 section 20 ram .................................................................................................................. 727 20.1 overview................................................................................................................... ........ 727 20.1.1 block diagram..................................................................................................... 727 20.1.2 register configuration......................................................................................... 729 20.2 register descriptions...................................................................................................... .. 730 20.2.1 system control register (syscr)...................................................................... 730 20.3 operation .................................................................................................................. ........ 730 20.4 usage notes ................................................................................................................ ...... 731 section 21a rom (h8s/2636 group) .......................................................................... 733 21a.1 overview.................................................................................................................. ..... 733 21a.1.1 block diagram.............................................................................................. 733 21a.1.2 register configuration ................................................................................. 733 21a.2 register descriptions .................................................................................................... 7 34 21a.2.1 mode control register (mdcr) .................................................................. 734 21a.3 operation................................................................................................................. ...... 734 21a.4 flash memory overview............................................................................................... 737 21a.4.1 features ........................................................................................................ 737 21a.4.2 block diagram.............................................................................................. 738 21a.4.3 mode transitions.......................................................................................... 739 21a.4.4 on-board progra mming modes ................................................................... 740 21a.4.5 flash memory emulation in ram ............................................................... 742 21a.4.6 differences between boot mode and user program mode .......................... 743 21a.4.7 block configuration ..................................................................................... 744 21a.5 pin configuration ......................................................................................................... . 745 21a.6 register configuration .................................................................................................. 74 6 21a.7 register descriptions .................................................................................................... 7 47 21a.7.1 flash memory control register 1 (flmcr1) ............................................. 747 21a.7.2 flash memory control register 2 (flmcr2) ............................................. 750 21a.7.3 erase block register 1 (ebr1) .................................................................... 751 21a.7.4 erase block register 2 (ebr2) .................................................................... 751 21a.7.5 ram emulation register (ramer) ........................................................... 752 21a.7.6 flash memory power control register (flpwcr)..................................... 753 21a.8 on-board programming modes .................................................................................... 754
rev. 6.00 feb 22, 2005 page li of lx 21a.8.1 boot mode.................................................................................................... 755 21a.8.2 user program mode ..................................................................................... 759 21a.9 flash memory programming/erasing ........................................................................... 761 21a.9.1 program mode .............................................................................................. 763 21a.9.2 program-verify mode .................................................................................. 764 21a.9.3 erase mode................................................................................................... 768 21a.9.4 erase-verify mode ....................................................................................... 769 21a.10 protection ............................................................................................................... ....... 771 21a.10.1 hardware protection ..................................................................................... 771 21a.10.2 software protection ...................................................................................... 772 21a.10.3 error protection ............................................................................................ 772 21a.11 flash memory emulation in ram................................................................................ 774 21a.12 interrupt handling when programming/erasing flash memory ................................... 776 21a.13 flash memory programmer mode ................................................................................ 777 21a.13.1 socket adapter and memory map................................................................ 777 21a.13.2 programmer mode operation ....................................................................... 778 21a.13.3 memory read mode..................................................................................... 779 21a.13.4 auto-program mode..................................................................................... 783 21a.13.5 auto-erase mode.......................................................................................... 785 21a.13.6 status read mode......................................................................................... 787 21a.13.7 status po lling ................................................................................................ 788 21a.13.8 programmer mode transition time ............................................................. 788 21a.13.9 notes on memory progra mming .................................................................. 789 21a.14 flash memory and power-down states ........................................................................ 790 21a.14.1 notes on power-down states ....................................................................... 790 21a.15 flash memory programming and erasing precautions ................................................. 791 21a.16 note on switching from f-ztat version to mask rom version .............................. 796 section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) .... 797 21b.1 overview.................................................................................................................. ..... 797 21b.1.1 block diagram.............................................................................................. 797 21b.1.2 register configuration ................................................................................. 798 21b.2 register descriptions .................................................................................................... 7 98 21b.2.1 mode control register (mdcr) .................................................................. 798 21b.3 operation................................................................................................................. ...... 798 21b.4 flash memory overview............................................................................................... 801 21b.4.1 features ........................................................................................................ 801 21b.4.2 block diagram.............................................................................................. 802 21b.4.3 mode transitions.......................................................................................... 803 21b.4.4 on-board progra mming modes ................................................................... 804
rev. 6.00 feb 22, 2005 page lii of lx 21b.4.5 flash memory emulation in ram ............................................................... 806 21b.4.6 differences between boot mode and user program mode .......................... 807 21b.4.7 block configuration ..................................................................................... 808 21b.5 pin configuration ......................................................................................................... . 809 21b.6 register configuration .................................................................................................. 81 0 21b.7 register descriptions .................................................................................................... 8 11 21b.7.1 flash memory control register 1 (flmcr1) ............................................. 811 21b.7.2 flash memory control register 2 (flmcr2) ............................................. 814 21b.7.3 erase block register 1 (ebr1) .................................................................... 815 21b.7.4 erase block register 2 (ebr2) .................................................................... 815 21b.7.5 ram emulation register (ramer) ........................................................... 816 21b.7.6 flash memory power control register (flpwcr)..................................... 818 21b.8 on-board programming modes .................................................................................... 819 21b.8.1 boot mode.................................................................................................... 820 21b.8.2 user program mode ..................................................................................... 824 21b.9 programming/erasing flash memory ........................................................................... 826 21b.9.1 program mode .............................................................................................. 828 21b.9.2 program-verify mode .................................................................................. 829 21b.9.3 erase mode................................................................................................... 833 21b.9.4 erase-verify mode ....................................................................................... 833 21b.10 protection ............................................................................................................... ....... 835 21b.10.1 hardware protection ..................................................................................... 835 21b.10.2 software protection ...................................................................................... 836 21b.10.3 error protection ............................................................................................ 837 21b.11 flash memory emulation in ram................................................................................ 839 21b.12 interrupt handling when programming/erasing flash memory ................................... 841 21b.13 flash memory programmer mode ................................................................................ 841 21b.13.1 socket adapter and memory map................................................................ 842 21b.13.2 programmer mode operation ....................................................................... 843 21b.13.3 memory read mode..................................................................................... 844 21b.13.4 auto-program mode..................................................................................... 848 21b.13.5 auto-erase mode.......................................................................................... 850 21b.13.6 status read mode......................................................................................... 852 21b.13.7 status po lling ................................................................................................ 853 21b.13.8 programmer mode transition time ............................................................. 853 21b.13.9 notes on memory progra mming .................................................................. 854 21b.14 flash memory and power-down states ........................................................................ 855 21b.14.1 notes on power-down states ....................................................................... 856 21b.15 flash memory programming and erasing precautions ................................................. 856 21b.16 note on switching from f-ztat version to mask rom version .............................. 862
rev. 6.00 feb 22, 2005 page liii of lx section 21c rom (h8s/2635 group) .......................................................................... 863 21c.1 overview.................................................................................................................. ..... 863 21c.1.1 block diagram.............................................................................................. 863 21c.1.2 register configuration ................................................................................. 864 21c.2 register descriptions .................................................................................................... 8 64 21c.2.1 mode control register (mdcr) .................................................................. 864 21c.3 operation................................................................................................................. ...... 864 21c.4 flash memory overview............................................................................................... 867 21c.4.1 features ........................................................................................................ 867 21c.4.2 block diagram.............................................................................................. 868 21c.4.3 mode transitions.......................................................................................... 869 21c.4.4 on-board progra mming modes ................................................................... 870 21c.4.5 flash memory emulation in ram ............................................................... 872 21c.4.6 differences between boot mode and user program mode .......................... 873 21c.4.7 block configuration ..................................................................................... 874 21c.5 pin configuration ......................................................................................................... . 875 21c.6 register configuration .................................................................................................. 87 6 21c.7 register descriptions .................................................................................................... 8 77 21c.7.1 flash memory control register 1 (flmcr1) ............................................. 877 21c.7.2 flash memory control register 2 (flmcr2) ............................................. 880 21c.7.3 erase block register 1 (ebr1) .................................................................... 881 21c.7.4 erase block register 2 (ebr2) .................................................................... 881 21c.7.5 ram emulation register (ramer) ........................................................... 882 21c.7.6 flash memory power control register (flpwcr)..................................... 884 21c.8 on-board programming modes .................................................................................... 885 21c.8.1 boot mode.................................................................................................... 886 21c.8.2 user program mode ..................................................................................... 890 21c.9 programming/erasing flash memory ........................................................................... 892 21c.9.1 program mode .............................................................................................. 894 21c.9.2 program-verify mode .................................................................................. 895 21c.9.3 erase mode................................................................................................... 899 21c.9.4 erase-verify mode ....................................................................................... 899 21c.10 protection ............................................................................................................... ....... 901 21c.10.1 hardware protection ..................................................................................... 901 21c.10.2 software protection ...................................................................................... 902 21c.10.3 error protection ............................................................................................ 903 21c.11 flash memory emulation in ram................................................................................ 905 21c.12 interrupt handling when programming/erasing flash memory ................................... 907 21c.13 flash memory programmer mode ................................................................................ 907 21c.13.1 socket adapter and memory map................................................................ 908
rev. 6.00 feb 22, 2005 page liv of lx 21c.13.2 programmer mode operation ....................................................................... 909 21c.13.3 memory read mode..................................................................................... 910 21c.13.4 auto-program mode..................................................................................... 914 21c.13.5 auto-erase mode.......................................................................................... 916 21c.13.6 status read mode......................................................................................... 918 21c.13.7 status po lling ................................................................................................ 919 21c.13.8 programmer mode transition time ............................................................. 919 21c.13.9 notes on memory progra mming .................................................................. 920 21c.14 flash memory and power-down states ........................................................................ 921 21c.14.1 notes on power-down states ....................................................................... 922 21c.15 flash memory programming and erasing precautions ................................................. 922 21c.16 note on switching from f-ztat version to mask rom version .............................. 928 section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) ....................................................................................... 929 22a.1 overview.................................................................................................................. ..... 929 22a.1.1 block diagram.............................................................................................. 929 22a.1.2 register configuration ................................................................................. 930 22a.2 register descriptions .................................................................................................... 9 30 22a.2.1 system clock control register (sckcr).................................................... 930 22a.2.2 low-power control register (lpwrcr).................................................... 931 22a.3 oscillator ....................................................................................................................... 932 22a.3.1 connecting a crystal resonator ................................................................... 932 22a.3.2 external clock input..................................................................................... 935 22a.4 pll circuit............................................................................................................... ..... 937 22a.5 medium-speed clock divider....................................................................................... 938 22a.6 bus master clock selection circuit .............................................................................. 938 22a.7 subclock oscillator ....................................................................................................... 938 22a.8 subclock waveform generation circuit ....................................................................... 939 22a.9 note on crystal resonator ............................................................................................ 939 section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) ....... 941 22b.1 overview.................................................................................................................. ..... 941 22b.1.1 block diagram.............................................................................................. 941 22b.1.2 register configuration ................................................................................. 942 22b.2 register descriptions .................................................................................................... 9 42 22b.2.1 system clock control register (sckcr).................................................... 942 22b.2.2 low-power control register (lpwrcr).................................................... 943 22b.3 oscillator ....................................................................................................................... 944 22b.3.1 connecting a crystal resonator ................................................................... 944
rev. 6.00 feb 22, 2005 page lv of lx 22b.3.2 external clock input..................................................................................... 947 22b.4 pll circuit............................................................................................................... ..... 949 22b.5 medium-speed clock divider....................................................................................... 949 22b.6 bus master clock selection circuit .............................................................................. 949 22b.7 subclock divider.......................................................................................................... . 950 22b.8 note on resonator......................................................................................................... 950 section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] .............................................................................................. 951 23a.1 overview.................................................................................................................. ..... 951 23a.1.1 register configuration ................................................................................. 955 23a.2 register descriptions .................................................................................................... 9 56 23a.2.1 standby control register (sbycr) ............................................................. 956 23a.2.2 system clock control register (sckcr).................................................... 957 23a.2.3 low-power control register (lpwrcr).................................................... 959 23a.2.4 timer control/status register (tcsr)......................................................... 959 23a.2.5 module stop control register (mstpcr)................................................... 960 23a.3 medium-speed mode.................................................................................................... 962 23a.4 sleep mode ................................................................................................................ ... 963 23a.4.1 sleep mode................................................................................................... 963 23a.4.2 exiting sleep mode ...................................................................................... 963 23a.5 module stop mode........................................................................................................ 96 4 23a.5.1 module stop mode ....................................................................................... 964 23a.5.2 usage notes.................................................................................................. 965 23a.6 software standby mode ................................................................................................ 966 23a.6.1 software standby mode ............................................................................... 966 23a.6.2 clearing software standby mode................................................................. 966 23a.6.3 setting osc illation stabilization time after clearing software standby mode............................................................................................... 967 23a.6.4 software standby mode application example............................................. 968 23a.6.5 usage notes.................................................................................................. 969 23a.7 hardware standby mode............................................................................................... 969 23a.7.1 hardware standby mode .............................................................................. 969 23a.7.2 hardware standby mode t iming ................................................................. 970 23a.8 clock output disabling function............................................................................... 971
rev. 6.00 feb 22, 2005 page lvi of lx section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf, hd6432635f, hd64f2635f, hd6432634f] ............................................................................................... 973 23b.1 overview.................................................................................................................. ..... 973 23b.1.1 register configuration ................................................................................. 979 23b.2 register descriptions .................................................................................................... 9 79 23b.2.1 standby control register (sbycr) ............................................................. 979 23b.2.2 system clock control register (sckcr).................................................... 981 23b.2.3 low-power control register (lpwrcr).................................................... 983 23b.2.4 timer control/status register (tcsr)......................................................... 985 23b.2.5 module stop control register (mstpcr)................................................... 987 23b.3 medium-speed mode.................................................................................................... 988 23b.4 sleep mode ................................................................................................................ ... 989 23b.4.1 sleep mode................................................................................................... 989 23b.4.2 exiting sleep mode ...................................................................................... 989 23b.5 module stop mode........................................................................................................ 99 0 23b.5.1 module stop mode ....................................................................................... 990 23b.5.2 usage notes.................................................................................................. 992 23b.6 software standby mode ................................................................................................ 992 23b.6.1 software standby mode ............................................................................... 992 23b.6.2 clearing software standby mode................................................................. 993 23b.6.3 setting osc illation stabilization time after clearing software standby mode............................................................................................... 993 23b.6.4 software standby mode application example............................................. 995 23b.6.5 usage notes.................................................................................................. 996 23b.7 hardware standby mode............................................................................................... 996 23b.7.1 hardware standby mode .............................................................................. 996 23b.7.2 hardware standby mode t iming ................................................................. 997 23b.8 watch mode (u-mask, w-mask version, h8s/2635 group only).............................. 997 23b.8.1 watch mode ................................................................................................. 997 23b.8.2 exiting watch mode..................................................................................... 998 23b.8.3 notes............................................................................................................. 998 23b.9 subsleep mode (u-mask, w-mask version, h8s/2635 group only).......................... 999 23b.9.1 subsleep mode ............................................................................................. 999 23b.9.2 exiting subsleep mode................................................................................. 999 23b.10 subactive mode (u-mask, w-mask version, h8s/2635 group only) ...................... 1000 23b.10.1 subactive mode .......................................................................................... 1000
rev. 6.00 feb 22, 2005 page lvii of lx 23b.10.2 exiting subactive mode ............................................................................. 1000 23b.11 direct transitions (u-mask, w-mask version, h8s/2635 group only).................... 1001 23b.11.1 overview of direct transitions .................................................................. 1001 23b.12 clock output disabling function............................................................................. 1002 23b.13 usage notes .............................................................................................................. .. 1003 section 24 electrical characteristics ........................................................................... 1005 24.1 h8s/2636 group electrical characteristics .................................................................... 1005 24.1.1 absolute maximum ratings .............................................................................. 1005 24.1.2 power supply voltage and operating frequency range................................... 1006 24.1.3 dc characteristics ............................................................................................. 1007 24.1.4 ac characteristics ............................................................................................. 1011 24.1.5 a/d conversion characteristics ........................................................................ 1016 24.1.6 d/a conversion characteristics ........................................................................ 1017 24.1.7 flash memory characteristics ........................................................................... 1018 24.2 h8s/2638 group electrical characteristics .................................................................... 1020 24.2.1 absolute maximum ratings .............................................................................. 1020 24.2.2 power supply voltage and operating frequency range................................... 1021 24.2.3 dc characteristics ............................................................................................. 1022 24.2.4 ac characteristics ............................................................................................. 1028 24.2.5 a/d conversion characteristics ........................................................................ 1034 24.2.6 d/a conversion characteristics ........................................................................ 1035 24.2.7 flash memory characteristics ........................................................................... 1036 24.3 h8s/2639 group, h8s/2635 group electrical characteristics....................................... 1038 24.3.1 absolute maximum ratings .............................................................................. 1038 24.3.2 power supply voltage and operating frequency range................................... 1039 24.3.3 dc characteristics ............................................................................................. 1040 24.3.4 ac characteristics ............................................................................................. 1046 24.3.5 a/d conversion characteristics ........................................................................ 1052 24.3.6 d/a conversion characteristics ........................................................................ 1053 24.3.7 flash memory characteristics ........................................................................... 1054 24.4 h8s/2630 group electrical characteristics .................................................................... 1056 24.4.1 absolute maximum ratings .............................................................................. 1056 24.4.2 power supply voltage and operating frequency range................................... 1057 24.4.3 dc characteristics ............................................................................................. 1058 24.4.4 ac characteristics ............................................................................................. 1064 24.4.5 a/d conversion characteristics ........................................................................ 1070 24.4.6 d/a conversion characteristics ........................................................................ 1071 24.4.7 flash memory characteristics ........................................................................... 1072
rev. 6.00 feb 22, 2005 page lviii of lx 24.5 operation t iming ............................................................................................................ 1074 24.5.1 clock t iming ..................................................................................................... 1074 24.5.2 control signal t iming ....................................................................................... 1075 24.5.3 bus t iming ........................................................................................................ 1076 24.5.4 on-chip supporting module t iming................................................................. 1080 24.6 usage note ................................................................................................................. .... 1084 appendix a instruction set ............................................................................................ 1085 a.1 instruction list............................................................................................................ .... 1085 a.2 instruction codes ........................................................................................................... . 1109 a.3 operation code map....................................................................................................... 112 4 a.4 number of states required for instruction execution.................................................... 1128 a.5 bus states during instruction execution......................................................................... 1142 a.6 condition code modification ......................................................................................... 1156 appendix b internal i/o register ................................................................................. 1162 b.1 address ..................................................................................................................... ...... 1162 b.2 functions ................................................................................................................... ..... 1184 appendix c i/o port block diagrams ........................................................................ 1448 c.1 port 1 block diagrams.................................................................................................... 144 8 c.2 port 3 block diagrams.................................................................................................... 145 4 c.3 port 4 block diagram ..................................................................................................... 146 0 c.4 port 9 block diagram ..................................................................................................... 146 1 c.5 port a block diagram .................................................................................................... 1462 c.6 port b block diagram..................................................................................................... 146 6 c.7 port c block diagram..................................................................................................... 146 7 c.8 port d block diagram .................................................................................................... 1468 c.9 port e block diagram..................................................................................................... 146 9 c.10 port f block diagrams ................................................................................................... 147 0 c.11 port h block diagram .................................................................................................... 147 6 c.12 port j block diagram...................................................................................................... 1 477 appendix d pin states ..................................................................................................... 1478 d.1 port states in each mode................................................................................................ 1478 appendix e timing of transition to and recovery from hardware standby mode ............................................................................................ 1481
rev. 6.00 feb 22, 2005 page lix of lx appendix f product code lineup ............................................................................... 1482 appendix g package dimensions ................................................................................ 1484
rev. 6.00 feb 22, 2005 page lx of lx
section 1 overview rev. 6.00 feb 22, 2005 page 1 of 1484 rej09b0103-0600 section 1 overview 1.1 overview the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 are microcomputers (mcus: microcomputer units), built around the h8s/2600 cpu, employing renesas technology's proprietary architecture, and equipped with peripheral functions on-chip. the h8s/2600 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, fac ilitating migration from the h8/ 300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include data transfer controller (dtc) bus masters, rom and ram memory, a16-bit timer-pulse unit (tpu), programmable pulse generator (ppg), motor control pwm timer (pwm) watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter, controller area network (hcan) and i/o ports. an i 2 c bus interface (iic) is available as an option in the h8s/2638, h8s/2639, and h8s/2630. on-chip rom is available as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte flash memory (f- ztat? * version), and as 128-kbyte, 192-kbyte, 256-kbyte, and 384-kbyte mask rom. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. subclock (32 khz oscillation) functions are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. the features of the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 are shown in table 1-1. notes: the h8s/2635 and h8s/2634 are not equipped with a dtc, a ppg, or a d/a converter. * f-ztat is a trademark of renesas technology corp.
section 1 overview rev. 6.00 feb 22, 2005 page 2 of 1484 rej09b0103-0600 table 1-1 overview item specification cpu ? general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for realtime control ? maximum clock rate: 20 mhz ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 16-bit register-register multiply : 200 ns 16 16 + 42-bit multiply and accumulate : 200 ns 32 16-bit register-register divide : 1000 ns ? instruction set suitable for high-speed operation ? sixty-nine basic instructions ? 8/16/32-bit move/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? multiply-and accumulate instruction ? powerful bit-manipulation instructions ? cpu operating modes ? advanced mode: 16-mbyte address space bus controller ? address space divided into 8 areas, with bus specifications settable independently for each area ? choice of 8-bit or 16-bit access space for each area ? 2-state or 3-state access space can be designated for each area ? number of program wait states can be set for each area ? direct connection to burst rom supported pc break controller (this function is not implemented in the h8s/2635 group) ? supports debugging functions by means of pc break interrupts ? two break channels data transfer controller (dtc) (this function is not implemented in the h8s/2635 group) ? can be activated by internal interrupt or software ? multiple transfers or multiple types of transfer possible for one activation source ? transfer possible in repeat mode, block transfer mode, etc. ? request can be sent to cpu for interrupt that activated dtc
section 1 overview rev. 6.00 feb 22, 2005 page 3 of 1484 rej09b0103-0600 item specification 16-bit timer-pulse unit (tpu) ? 6-channel 16-bit timer on-chip ? pulse i/o processing capability for up to 16 pins' ? automatic 2-phase encoder count capability programmable pulse generator (ppg) (this function is not implemented in the h8s/2635 group) ? maximum 8-bit pulse output possible with tpu as time base ? output trigger selectable in 4-bit groups ? non-overlap margin can be set ? direct output or inverse output setting possible watchdog timer (wdt) 2 channels ? watchdog timer or interval timer selectable ? operation using sub-clock supported (wdt1 only) * motor control pwm timer (pwm) ? maximum of 16 10-bit pwm outputs ? eight outputs with two channels each built in ? duty settable between 0% and 100% ? automatic transfer of buffer register data supported ? settable to any one of 5 operating speeds serial communica- tion interface (sci) 3 channels (sci0 to sci2) ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function ? smart card interface function controller area network (hcan) 2 channels (the h8s/2635 group has one hcan channel) ? can: ver. 2.0b compliant ? buffer size: 15 transmit/receive messages, transmit only one message ? filtering of receive messages a/d converter ? resolution: 10 bits ? input: 12 channels ? high-speed conversion: 13.3 s minimum conversion time (at 20 mhz operation) ? single or scan mode selectable ? sample and hold circuit ? a/d conversion can be activated by external trigger or timer trigger d/a converter (this function is not implemented in the h8s/2635 group) ? resolution: 8 bits ? output: 2 channels
section 1 overview rev. 6.00 feb 22, 2005 page 4 of 1484 rej09b0103-0600 item specification i/o ports ? 72 i/o pins, 12 input-only pins memory ? flash memory or mask rom ? high-speed static ram product name rom ram h8s/2636 128 kbytes 4 kbytes h8s/2638 256 kbytes 16 kbytes h8s/2639 h8s/2630 * 384 kbytes h8s/2635 192 kbytes 6 kbytes h8s/2634 128 kbytes note: * under development interrupt controller ? seven external interrupt pins (nmi, irq0 to irq5 ) ? 49 internal interrupt sources (45 sources in h8s/2635) ? eight priority levels settable power-down states ? medium-speed mode ? sleep mode ? module-stop mode ? software standby mode ? hardware standby mode ? sub-clock operation * (subactive mode, subsleep mode, watch mode) operating modes four mcu operating modes external data bus mode cpu operating mode description on-chip rom initial value maximum value 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled ? ?
section 1 overview rev. 6.00 feb 22, 2005 page 5 of 1484 rej09b0103-0600 item specification clock pulse generator ? on-chip pll circuit ( 1, 2, 4) ? input clock frequency h8s/2636, h8s/2638, h8s/2630: 4 to 20 mhz h8s/2639, h8s/2635, h8s/2634: 4 to 5 mhz i 2 c bus interface (iic) 2 channel (option) (only for the h8s/2638, h8s/2639, and h8s/2630) ? conforms to the i 2 c bus interface type advocated by philips ? single master mode/slave mode ? possible to determine arbitration lost conditions ? supports two slave addresses packages ? 128-pin plastic qfp (fp-128b) product lineup model name mask rom version f-ztat version subclock functions i 2 c bus interface rom/ ram (bytes) packages hd6432636f hd64f2636f no ? hd6432636uf (u-mask version) hd64f2636uf (u-mask version) yes ? 128 k/ 4 k fp-128b hd6432638f hd64f2638f no no hd6432638uf (u-mask version) hd64f2638uf (u-mask version) yes no 256 k/ 16 k hd6432638wf (w-mask version) hd64f2638wf (w-mask version) yes yes hd6432639uf (u-mask version) hd64f2639uf (u-mask version) yes no hd6432639wf (w-mask version) hd64f2639wf (w-mask version) yes yes hd6432630f hd64f2630f no no hd6432630uf (u-mask version) hd64f2630uf (u-mask version) yes no 384 k/ 16 k hd6432630wf (w-mask version) hd64f2630wf (w-mask version) yes yes hd6432635f hd64f2635f yes no 192 k/ 6 k hd6432634f ? yes no 128 k/ 6 k note: * under development note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the u-mask and w-mask versions, and h8s/2635 group, but are not available in the other versions.
section 1 overview rev. 6.00 feb 22, 2005 page 6 of 1484 rej09b0103-0600 1.2 internal block diagram figure 1-1 (a) shows an internal block diagram of the h8s/2636. pe7 /d7 pe6 /d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0 / d0 internal data bus peripheral data bus peripheral address bus pd7 /d15 pd6 /d14 pd5 /d13 pd4 /d12 pd3 /d11 pd2 /d10 pd1 /d9 pd0 /d8 port d vcc vcc vcc vcc vcc vss vss vss vss vss vss vss vss vss vss vss pa3 / a19/sck2 pa2 / a18/rxd2 pa1 / a17/txd2 pa0 / a16 pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd3 pb2/a10/tiocc3 pb1 / a9/tiocb3 pb0 / a8/tioca3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p35 / sck1/ irq5 p34 / rxd1 p33 / txd1 p32 / sck0/ irq4 p31 / rxd0 p30 / txd0 p93 / an11 p92 / an10 p91 / an9 p90 / an8 p47/an7/ da1 p46/an6/ da0 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 vref avcc avss hrxd0 htxd0 hrxd1 htxd1 pwmvcc pwmvcc pwmvss pwmvss pwmvss p10/ po8/tioca0 /a20 p11/ po9/tiocb0 /a21 p12/ po10/ tiocc0/ tclka/a22 p13/ po11/ tiocd0/ tclkb/a23 p14/ po12/ tioca1/ irq0 p15 / po13/ tiocb1 / tclkc p16/ po14/ tioca2/ irq1 p17 / po15/ tiocb2 / tclkd pf7 / pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf0 / irq2 rom (mask rom, flash memory) ram wdt 2 channels tpu sci 3 channels d/a converter motor control pwm timer a/d converter ppg vcl md2 md1 md0 osc2 * 1 osc1 * 1 extal xtal pllcap stby res nmi fwe * 2 h8s/2600 cpu dtc interrupt controller pc break controller port e port 4 port 1 internal address bus ph0/pwm1a ph1/pwm1b ph2/pwm1c ph3/pwm1d ph4/pwm1e ph5/pwm1f ph6/pwm1g ph7/pwm1h pj0/pwm2a pj1/pwm2b pj2/pwm2c pj3/pwm2d pj4/pwm2e pj5/pwm2f pj6/pwm2g pj7/pwm2h pll clock pulse generator port a port b port c port 3 port 9 bus controller hcan 2 channels port f port h port j notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask version. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 2. the fwe pin only applies to the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. figure 1-1 (a) internal block diagram of h8s/2636
section 1 overview rev. 6.00 feb 22, 2005 page 7 of 1484 rej09b0103-0600 figure 1-1 (b) shows an internal block diagram of the h8s/2638, h8s/2639, and h8s/2630. pe7 /d7 pe6 /d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0 / d0 pd7 /d15 pd6 /d14 pd5 /d13 pd4 /d12 pd3 /d11 pd2 /d10 pd1 /d9 pd0 /d8 vcc vcc vcc v cc v cc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0 / a16 pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd3 pb2/a10/tiocc3 pb1 / a9/tiocb3 pb0 / a8/tioca3 pc7/ a7 pc6/ a6 pc5/ a5 pc4/ a4 pc3/ a3 pc2/ a2 pc1/ a1 pc0/ a0 p35/sck1/scl0 * 2 / irq5 p34/rxd1/sda0 * 2 p33/txd1/scl1 * 2 p32/sck0/sda1 * 2 / irq4 p31 / rxd0 p30 / txd0 p93 / an11 p92 / an10 p91/an9 p90/an8 p47/an7/da1 p46/an6/da0 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 vref avcc avss hrxd0 htxd0 hrxd1 htxd1 pwmvcc pwmvcc pwmvss pwmvss pwmvss p10/po8/tioca0/a20 p11/po9/tiocb0/a21 p12/po10/tiocc0/tclka/a22 p13/po11/tiocd0/tclkb/a23 p14/po12/tioca1/ irq0 p15/po13/tiocb1/tclkc p16/po14/tioca2/ irq1 p17/po15/tiocb2/tclkd pf7 / pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf0/ irq2 ram tpu ppg vcl md2 md1 md0 osc2 * 1 osc1 * 1 extal xtal pllcap stby res nmi fwe * 3 h8s/2600 cpu dtc ph0/pwm1a ph1/pwm1b ph2/pwm1c ph3/pwm1d ph4/pwm1e ph5/pwm1f ph6/pwm1g ph7/pwm1h pj0/pwm2a pj1/pwm2b pj2/pwm2c pj3/pwm2d pj4/pwm2e pj5/pwm2f pj6/pwm2g pj7/pwm2h pll port d port e port a port b port c port 9 port 3 clock pulse generator port 4 port 1 port f port h port j bus controller wdt 2 channels i 2 c bus interface (option) motor control pwm timer d/a converter sci 3 channels hcan 2 channels a/d converter rom (mask rom, flash memory) pc break controller interrupt controller peripheral data bus peripheral address bus internal data bus internal address bus notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. the h8s/2639 has no osc1 and osc2 pins. 2. these pins are used for the i 2 c bus interface. the i 2 c bus interface is available as an option. the product equipped with the i 2 c bus interface is the w-mask version. 3. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. figure 1-1 (b) internal block diagram of h8s/2638, h8s/2639, and h8s/2630
section 1 overview rev. 6.00 feb 22, 2005 page 8 of 1484 rej09b0103-0600 figure 1-1 (c) shows an internal block diagram of the h8s/2635 group. pa3 / a19/sck2 pa2 / a18/rxd2 pa1 / a17/txd2 pa0/a16 pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd 3 pb2/a10/tiocc3 pb1 / a9/tiocb3 pb0 / a8/tioca3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 p93 / an11 p92 / an10 p91 / an9 p90 / an8 port a port b port c port 3 port 9 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 vref avcc avss hrxd htxd pwmvcc pwmvcc pwmvss pwmvss pwmvss p10/tioca0/a20 p11/tiocb0/a21 p12/tiocc0/tclka/a22 p13/tiocd0/tclkb/a23 p14/tioca1/ irq0 p15/tiocb1/tclkc p16/tioca2/ irq1 p17/tiocb2/tclkd port 4 port 1 pf7 / pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf0/ irq2 ph0/pwm1a ph1/pwm1b ph2/pwm1c ph3/pwm1d ph4/pwm1e ph5/pwm1f ph6/pwm1g ph7/pwm1h pj0/pwm2a pj1/pwm2b pj2/pwm2c pj3/pwm2d pj4/pwm2e pj5/pwm2f pj6/pwm2g pj7/pwm2h notes: 1. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. 2. the nc pin should be left open. port f port h port j vcl md2 md1 md0 nc * 2 extal xtal pllcap pllvss stby res nmi fwe * 1 vcc vcc vcc vcc vcc vss vss vss vss vss vss vss vss vss vss vss vss vss pe7 /d7 pe6 /d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 pd7 /d15 pd6 /d14 pd5 /d13 pd4 /d12 pd3 /d11 pd2 /d10 pd1 /d9 pd0 /d8 port d port e ram h8s/2600 cpu pll clock pulse generator bus controller wdt 2 channels motor control pwm timer hcan 1 channel sci 3 channels tpu a/d converter rom (mask rom, flash memory) interrupt controller peripheral data bus peripheral address bus internal data bus internal address bus figure 1-1 (c) internal block diagram of h8s/2635 group
section 1 overview rev. 6.00 feb 22, 2005 page 9 of 1484 rej09b0103-0600 1.3 pin description 1.3.1 pin arrangement figure 1-2 shows the pin arrangement of the h8s/2636, figure 1-3 shows the pin arrangement of the h8s/2638 and h8s/2630, figure 1-4 shows the pin arrangement of the h8s/2639, and figure 1-5 shows the pin arrangement of the h8s/2635 group. vcc vcc nc nc pa0/a16 pa1/a17/txd2 pa2/a18/rxd2 pa3/a19/sck2 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 vcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 vss vss hrxd1 htxd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vref avcc nc vss hrxd0 htxd0 p17/po15/tiocb2/tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/tclkb/a23 p12/po10/tiocc0/tclka/a22 p11/po9/tiocb0/a21 p10/po8/tioca0/a20 pf7/ stby fwe * 3 extal vss xtal vcl vcc vcc osc1 * 2 osc2 * 2 pllvss vss pllcap nmi res p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 vss vss p31/rxd0 p30/txd0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 pwmvss pj7/ pwm2h pj6/ pwm2g pj5/ pwm2f pj4/ pwm2e pwmvcc pj3/ pwm2d pj2/ pwm2c pj1/ pwm2b pj0/ pwm2a pwmvss ph7/pwm1h ph6/pwm1g ph5/pwm1f ph4/pwm1e pwmvcc ph3/pwm1d ph2/pwm1c ph1/pwm1b ph0/pwm1a pwmvss vss pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6/da0 p47/an7/da1 p90/an8 p91/an9 p92/an10 p93/an11 avss md0 md1 md2 pf0/ irq2 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 vss pb0/a8/tioca3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 top view (fp-128b) * 1 0.1 f notes: ppg and d/a converter pin functions not implemented. 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask version. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 3. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. 64f2636f20 h8s/2636 index 64f2636f20 h8s/2636 u index (u-mask version) figure 1-2 pin arrangement of h8s/2636 group (fp-128b: top view)
section 1 overview rev. 6.00 feb 22, 2005 page 10 of 1484 rej09b0103-0600 vcc vcc nc nc pa0/a16 pa1/a17/txd2 pa2/a18/rxd2 pa3/a19/sck2 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 vcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 vss vss hrxd1 htxd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vref avcc nc vss hrxd0 htxd0 p17/po15/tiocb2/tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/tclkb/a23 p12/po10/tiocc0/tclka/a22 p11/po9/tiocb0/a21 p10/po8/tioca0/a20 pf7/ stby fwe * 4 extal vss xtal vcl vcc vcc osc1 * 2 osc2 * 2 pllvss vss pllcap nmi res p35/sck1/scl0 * 3 / irq5 p34/rxd1/sda0 * 3 p33/txd1/scl1 * 3 p32/sck0/sda1 * 3 / irq4 vss vss p31/rxd0 p30/txd0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 top view (fp-128b) * 1 64f2638f20 h8s/2638 index 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6/da0 p47/an7/da1 p90/an8 p91/an9 p92/an10 p93/an11 avss md0 md1 md2 pf0/ irq2 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 vss pb0/a8/tioca3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 pwmvss pj7/pwm2h pj6/pwm2g pj5/pwm2f pj4/pwm2e pwmvcc pj3/pwm2d pj2/pwm2c pj1/pwm2b pj0/pwm2a pwmvss ph7/pwm1h ph6/pwm1g ph5/pwm1f ph4/pwm1e pwmvcc ph3/pwm1d ph2/pwm1c ph1/pwm1b ph0/pwm1a pwmvss vss pf3/ lwr / adtrg / irq 3 pf4/ hwr pf5/ rd pf6/ as 0.1 f 64f2638f20 h8s/2638 u index 64f2638f20 h8s/2638 w index (w-mask version) (u-mask version) 64f2630f20 h8s/2630 index 64f2630f20 h8s/2630 u index 64f2630f20 h8s/2630 w index (w-mask version) (u-mask version) notes: the ppg and d/a converter pin functions not implemented. 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 3. these pins are used for the i 2 c bus interface. the i 2 c bus interface is available as an option. the product equipped with the i 2 c bus interface is the w-mask version. 4. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. figure 1-3 pin arrangement of h8s/2638 group and h8s/2630 group (fp-128b: top view)
section 1 overview rev. 6.00 feb 22, 2005 page 11 of 1484 rej09b0103-0600 vcc vcc nc nc pa0/a16 pa1/a17/txd2 pa2/a18/rxd2 pa3/a19/sck2 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 vcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 vss vss hrxd1 htxd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vref avcc nc vss hrxd0 htxd0 p17/po15/tiocb2/tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/tclkb/a23 p12/po10/tiocc0/tclka/a22 p11/po9/tiocb0/a21 p10/po8/tioca0/a20 pf7/ stby fwe * 3 extal vss xtal vcl vcc vcc vss nc pllvss vss pllcap nmi res p35/sck1/scl0 * 2 / irq5 p34/rxd1/sda0 * 2 p33/txd1/scl1 * 2 p32/sck0/sda1 * 2 / irq4 vss vss p31/rxd0 p30/txd0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 top view (fp-128b) * 1 64f2639f20 h8s/2639 index 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6/da0 p47/an7/da1 p90/an8 p91/an9 p92/an10 p93/an11 avss md0 md1 md2 pf0/ irq2 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 vss pb0/a8/tioca3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 pwmvss pj7/ pwm2h pj6/ pwm2g pj5/ pwm2f pj4/ pwm2e pwmvcc pj3/ pwm2d pj2/ pwm2c pj1/ pwm2b pj0/ pwm2a pwmvss ph7/pwm1h ph6/pwm1g ph5/pwm1f ph4/pwm1e pwmvcc ph3/pwm1d ph2/pwm1c ph1/pwm1b ph0/pwm1a pwmvss vss pf3/ lwr / adtrg / irq 3 pf4/ hwr pf5/ rd pf6/ as u 0.1 f notes: 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). 2. these pins are used for the i 2 c bus interface. the i 2 c bus interface is available as an option. the product equipped with the i 2 c bus interface is the w-mask version. 3. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. 64f2639f20 h8s/2639 index w (w-mask version) (u-mask version) figure 1-4 pin arrangement of h8s/2639 group (fp-128b: top view)
section 1 overview rev. 6.00 feb 22, 2005 page 12 of 1484 rej09b0103-0600 vcc vcc nc nc pa0/a16 pa1/a17/txd2 pa2/a18/rxd2 pa3/a19/sck2 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 vcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 vss vss vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vref avcc nc vss hrxd0 htxd0 p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/po9/tiocb0/a21 p10/po8/tioca0/a20 pf7/ stby fwe * 2 extal vss xtal vcl vcc vcc vss nc pllvss vss pllcap nmi res p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 vss vss p31/rxd0 p30/txd0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 top view (fp-128b) * 1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p90/an8 p91/an9 p92/an10 p93/an11 avss md0 md1 md2 pf0/ irq2 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 vss pb0/a8/tioca3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 pwmvss pj7/pwm2h pj6/pwm2g pj5/pwm2f pj4/pwm2e pwmvcc pj3/pwm2d pj2/pwm2c pj1/pwm2b pj0/pwm2a pwmvss ph7/pwm1h ph6/pwm1g ph5/pwm1f ph4/pwm1e pwmvcc ph3/pwm1d ph2/pwm1c ph1/pwm1b ph0/pwm1a pwmvss vss pf3/ lwr / adtrg / irq 3 pf4/ hwr pf5/ rd pf6/ as 0.1 f notes: 1. connect a 0.1 f capacitor between vcl and vss (close to the pins). 2. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. figure 1-5 pin arrangement of h8s/2635 group (fp-128b: top view)
section 1 overview rev. 6.00 feb 22, 2005 page 13 of 1484 rej09b0103-0600 1.3.2 pin functions in each operating mode table 1-2 shows the pin functions for each operating mode. table 1-2 pin functions in each operating mode pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 1 vcc vcc vcc vcc 2 vcc vcc vcc vcc 3ncncncnc 4ncncncnc 5 pa0/a16 pa0/a16 pa0/a16 pa0 6 pa1/a17/txd2 pa1/a17/txd2 pa1/a17/txd2 pa1/txd2 7 pa2/a18/rxd2 pa2/a18/rxd2 pa2/a18/rxd2 pa2/rxd2 8 pa3/a19/sck2 pa3/a19/sck2 pa3/a19/sck2 pa3/sck2 9 a7 a7 pc7/a7 pc7 10 a6 a6 pc6/a6 pc6 11 a5 a5 pc5/a5 pc5 12 a4 a4 pc4/a4 pc4 13 a3 a3 pc3/a3 pc3 14 a2 a2 pc2/a2 pc2 15 a1 a1 pc1/a1 pc1 16 a0 a0 pc0/a0 pc0 17 d15 d15 d15 pd7 18 d14 d14 d14 pd6 19 d13 d13 d13 pd5 20 d12 d12 d12 pd4 21 d11 d11 d11 pd3 22 d10 d10 d10 pd2 23 d9 d9 d9 pd1 24 vcc vcc vcc vcc 25 d8 d8 d8 pd0 26 vss vss vss vss
section 1 overview rev. 6.00 feb 22, 2005 page 14 of 1484 rej09b0103-0600 pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 27 pe7/d7 pe7/d7 pe7/d7 pe7 28 pe6/d6 pe6/d6 pe6/d6 pe6 29 pe5/d5 pe5/d5 pe5/d5 pe5 30 pe4/d4 pe4/d4 pe4/d4 pe4 31 pe3/d3 pe3/d3 pe3/d3 pe3 32 pe2/d2 pe2/d2 pe2/d2 pe2 33 pe1/d1 pe1/d1 pe1/d1 pe1 34 pe0/d0 pe0/d0 pe0/d0 pe0 35 vss vss vss vss 36 vss vss vss vss 37 hrxd1 hrxd1 hrxd1 hrxd1 38 htxd1 htxd1 htxd1 htxd1 39 as as as pf6 40 rd rd rd pf5 41 hwr hwr hwr pf4 42 lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ adtrg / irq3 43 vss vss vss vss 44 pwmvss pwmvss pwmvss pwmvss 45 ph0/pwm1a ph0/pwm1a ph0/pwm1a ph0/pwm1a 46 ph1/pwm1b ph1/pwm1b ph1/pwm1b ph1/pwm1b 47 ph2/pwm1c ph2/pwm1c ph2/pwm1c ph2/pwm1c 48 ph3/pwm1d ph3/pwm1d ph3/pwm1d ph3/pwm1d 49 pwmvcc pwmvcc pwmvcc pwmvcc 50 ph4/pwm1e ph4/pwm1e ph4/pwm1e ph4/pwm1e 51 ph5/pwm1f ph5/pwm1f ph5/pwm1f ph5/pwm1f 52 ph6/pwm1g ph6/pwm1g ph6/pwm1g ph6/pwm1g 53 ph7/pwm1h ph7/pwm1h ph7/pwm1h ph7/pwm1h 54 pwmvss pwmvss pwmvss pwmvss 55 pj0/pwm2a pj0/pwm2a pj0/pwm2a pj0/pwm2a 56 pj1/pwm2b pj1/pwm2b pj1/pwm2b pj1/pwm2b
section 1 overview rev. 6.00 feb 22, 2005 page 15 of 1484 rej09b0103-0600 pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 57 pj2/pwm2c pj2/pwm2c pj2/pwm2c pj2/pwm2c 58 pj3/pwm2d pj3/pwm2d pj3/pwm2d pj3/pwm2d 59 pwmvcc pwmvcc pwmvcc pwmvcc 60 pj4/pwm2e pj4/pwm2e pj4/pwm2e pj4/pwm2e 61 pj5/pwm2f pj5/pwm2f pj5/pwm2f pj5/pwm2f 62 pj6/pwm2g pj6/pwm2g pj6/pwm2g pj6/pwm2g 63 pj7/pwm2h pj7/pwm2h pj7/pwm2h pj7/pwm2h 64 pwmvss pwmvss pwmvss pwmvss 65 p30/txd0 p30/txd0 p30/txd0 p30/txd0 66 p31/rxd0 p31/rxd0 p31/rxd0 p31/rxd0 67 vss vss vss vss 68 vss vss vss vss 69 p32/sck0/sda1 * 2 / irq4 p32/sck0/sda1 * 2 / irq4 p32/sck0/sda1 * 2 / irq4 p32/sck0/sda1 * 2 / irq4 70 p33/txd1/scl1 * 2 p33/txd1/scl1 * 2 p33/txd1/scl1 * 2 p33/txd1/scl1 * 2 71 p34/rxd1/sda0 * 2 p34/rxd1/sda0 * 2 p34/rxd1/sda0 * 2 p34/rxd1/sda0 * 2 72 p35/sck1/scl0 * 2 / irq5 p35/sck1/scl0 * 2 / irq5 p35/sck1/scl0 * 2 / irq5 p35/sck1/scl0 * 2 / irq5 73 resresresres 74 nmi nmi nmi nmi 75 pllcap pllcap pllcap pllcap 76 vss vss vss vss 77 pllvss pllvss pllvss pllvss 78 osc2 * 1 osc2 * 1 osc2 * 1 osc2 * 1 79 osc1 * 1 osc1 * 1 osc1 * 1 osc1 * 1 80 vcc vcc vcc vcc 81 vcc vcc vcc vcc 82 vcl vcl vcl vcl 83 xtal xtal xtal xtal 84 vss vss vss vss 85 extal extal extal extal 86 fwe * 3 fwe * 3 fwe * 3 fwe * 3
section 1 overview rev. 6.00 feb 22, 2005 page 16 of 1484 rej09b0103-0600 pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 87 stby stby stby stby 88 pf7/ pf7/ pf7/ pf7/ 89 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0/a20 p10/po8 * 4 /tioca0 90 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0/a21 p11/po9 * 4 /tiocb0 91 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka/a22 p12/po10 * 4 /tiocc0/ tclka 92 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb/a23 p13/po11 * 4 /tiocd0/ tclkb 93 p14/po12 * 4 /tioca1/ irq0 p14/po12 * 4 /tioca1/ irq0 p14/po12 * 4 /tioca1/ irq0 p14/po12 * 4 /tioca1/ irq0 94 p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc p15/po13 * 4 /tiocb1/ tclkc 95 p16/po14 * 4 /tioca2/ irq1 p16/po14 * 4 /tioca2/ irq1 p16/po14 * 4 /tioca2/ irq1 p16/po14 * 4 /tioca2/ irq1 96 p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd p17/po15 * 4 /tiocb2/ tclkd 97 htxd0 htxd0 htxd0 htxd0 98 hrxd0 hrxd0 hrxd0 hrxd0 99 vss vss vss vss 100ncncncnc 101 avcc avcc avcc avcc 102 vref vref vref vref 103 p40/an0 p40/an0 p40/an0 p40/an0 104 p41/an1 p41/an1 p41/an1 p41/an1 105 p42/an2 p42/an2 p42/an2 p42/an2 106 p43/an3 p43/an3 p43/an3 p43/an3 107 p44/an4 p44/an4 p44/an4 p44/an4 108 p45/an5 p45/an5 p45/an5 p45/an5 109 p46/an6/da0 * 4 p46/an6/da0 * 4 p46/an6/da0 * 4 p46/an6/da0 * 4 110 p47/an7/da1 * 4 p47/an7/da1 * 4 p47/an7/da1 * 4 p47/an7/da1 * 4 111 p90/an8 p90/an8 p90/an8 p90/an8 112 p91/an9 p91/an9 p91/an9 p91/an9
section 1 overview rev. 6.00 feb 22, 2005 page 17 of 1484 rej09b0103-0600 pin no. pin name fp-128b mode 4 mode 5 mode 6 mode 7 113 p92/an10 p92/an10 p92/an10 p92/an10 114 p93/an11 p93/an11 p93/an11 p93/an11 115 avss avss avss avss 116 md0 md0 md0 md0 117 md1 md1 md1 md1 118 md2 md2 md2 md2 119 pf0/ irq2 pf0/ irq2 pf0/ irq2 pf0/ irq2 120 pb7/a15/tiocb5 pb7/a15/tiocb5 pb7/a15/tiocb5 pb7/tiocb5 121 pb6/a14/tioca5 pb6/a14/tioca5 pb6/a14/tioca5 pb6/tioca5 122 pb5/a13/tiocb4 pb5/a13/tiocb4 pb5/a13/tiocb4 pb5/tiocb4 123 pb4/a12/tioca4 pb4/a12/tioca4 pb4/a12/tioca4 pb4/tioca4 124 pb3/a11/tiocd3 pb3/a11/tiocd3 pb3/a11/tiocd3 pb3/tiocd3 125 pb2/a10/tiocc3 pb2/a10/tiocc3 pb2/a10/tiocc3 pb2/tiocc3 126 pb1/a9/tiocb3 pb1/a9/tiocb3 pb1/a9/tiocb3 pb1/tiocb3 127 vss vss vss vss 128 pb0/a8/tioca3 pb0/a8/tioca3 pb0/a8/tioca3 pb0/tioca3 notes: nc pins should be connected to vss or left open. 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. the h8s/2639 and h8s/2635 groups have no osc1 and osc2 pins. 2. these pins are used for the i 2 c bus interface. the i 2 c bus interface is available as an option (h8s/2638, h8s/2639, h8s/2630 only). the product equipped with the i 2 c bus interface is the w-mask version. 3. the fwe pin is for compatibility with the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. 4. the ppg output, da0, and da1 are not supported in h8s/2635 group.
section 1 overview rev. 6.00 feb 22, 2005 page 18 of 1484 rej09b0103-0600 1.3.3 pin functions table 1-3 outlines the pin functions of the h8s/2636. table 1-3 pin functions type symbol i/o name and function power vcc input power supply: for connection to the power supply. all vcc pins should be connected to the system power supply. vss input ground: for connection to ground (0 v). all vss pins should be co nnected to the system power supply (0 v). vcl output on-chip step-down power supply pin: the vcl pin need not be connected to the power supply. connect this pin to vss via a 0.1 f capacitor (placed close to the pins). clock pllvss input pll ground: ground for on-chip pll oscillator. pllcap input pll capacitance: external capacitance pin for on-chip pll oscillator. xtal input crystal: connects to a crystal oscillator. see section 22a, 22b, clock pulse generator, for typical connection diagrams for a crystal oscillator. extal input external clock: connects to a crystal oscillator. see section 22a, 22b, clock pulse generator, for typical connection diagrams for a crystal oscillator. osc1 * 1 input subclock: connects to a 32.768 khz crystal oscillator. see section 22a, clock pulse generator, for typical connection diagrams for a crystal oscillator. osc2 * 1 input subclock: connects to a 32.768 khz crystal oscillator. see section 22a, clock pulse generator, for typical connection diagrams for a crystal oscillator. output system clock: supplies the system clock to an external device. hcan htxd0, htxd1 * 3 output hcan transmit data: pin for can bus transmission. hrxd0, hrxd1 * 3 input hcan receive data: pin for can bus reception.
section 1 overview rev. 6.00 feb 22, 2005 page 19 of 1484 rej09b0103-0600 type symbol i/o name and function operating mode control md2 to md0 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the h8s/2636 is operating. md2 md1 md0 operating mode 000? 1? 10? 1? 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res input reset input: when this pin is driven low, the chip is reset. stby input standby: when this pin is driven low, a transition is made to hardware standby mode. fwe * 2 input flash write enable: pin for flash memory use (in planning stage). interrupts nmi input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq5 to irq0 input interrupt request 5 to 0: these pins request a maskable interrupt. address bus a23 to a0 output address bus: these pins output an address. data bus d15 to d0 i/o data bus: these pins constitute a bidirectional data bus. bus control as output address strobe: when this pin is low, it indicates that address output on the address bus is enabled. rd output read: when this pin is low, it indicates that the external address space can be read. hwr output high write: a strobe signal that writes to external space and indicates that the upper half (d15 to d8) of the data bus is enabled.
section 1 overview rev. 6.00 feb 22, 2005 page 20 of 1484 rej09b0103-0600 type symbol i/o name and function bus control lwr output low write: a strobe signal that writes to external space and indicates that the lower half (d7 to d0) of the data bus is enabled. 16-bit timer- pulse unit (tpu) tclkd to tclka input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 i/o input capture/output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 i/o input capture/output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 i/o input capture/output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 i/o input capture/output compare match a3 to d3: the tgr3a to tgr3d input capture input or output compare output, or pwm output pins. tioca4, tiocb4 i/o input capture/output compare match a4 and b4: the tgr4a and tgr4b input capture input or output compare output, or pwm output pins. tioca5, tiocb5 i/o input capture/output compare match a5 and b5: the tgr5a and tgr5b input capture input or output compare output, or pwm output pins. programmable pulse generator (ppg) po15 to po8 * 4 output pulse output 15 to 8: pulse output pins. txd2, txd1, txd0 output transmit data (channel 0, 1, 2): data output pins. rxd2, rxd1, rxd0 input receive data (channel 0, 1, 2): data input pins. serial communication interface (sci)/ smart card interface sck2, sck1, sck0 i/o serial clock (channel 0, 1, 2): clock i/o pins. a/d converter an11 to an0 input analog 11 to 0: analog input pins. adtrg input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion.
section 1 overview rev. 6.00 feb 22, 2005 page 21 of 1484 rej09b0103-0600 type symbol i/o name and function d/a converter da1, da0 * 5 output analog output: analog output pins for d/a converter. a/d converter, d/a converter avcc input analog power supply: a/d converter and d/a converter power supply pin. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v). avss i nput analog ground: ground pin for a/d converter and d/a converter. connect to system power supply (0 v). vref input analog reference power supply: a/d converter and d/a converter reference voltage input pin. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v). i/o ports p17 to p10 i/o port 1: an 8-bit i/o port. input or output can be designated for each bit by means of the port 1 data direction register (p1ddr). p35 to p30 i/o port 3: a 6-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p47 to p40 input port 4: an 8-bit input port. p93 to p90 input port 9: a 4-bit input port. pa3 to pa0 i/o port a: a 4-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb7 to pb0 i/o port b: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc7 to pc0 i/o port c: an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). pd7 to pd0 i/o port d: an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr). pe7 to pe0 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr).
section 1 overview rev. 6.00 feb 22, 2005 page 22 of 1484 rej09b0103-0600 type symbol i/o name and function i/o ports pf7 to pf3, pf0 i/o port f: a 6-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). ph7 to ph0 i/o port h: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (phddr). pj7 to pj0 i/o port j: an 8-bit i/o port. input or output can be designated for each bit by means of the port j data direction register (pjddr). motor control pwm pwm1a to pwm1h output pwm output: motor control pwm channel 1 output pins. pwm2a to pwm2h output pwm output: motor control pwm channel 2 output pins. pwmvcc input pwm power supply: power supply pin for motor- control pwm. connect to the system power supply (+5 v) when the motor-control function is not used. pwmvss input pwm ground: ground pin for motor-control pwm. connect to the system power supply (0 v). scl0, scl1 i/o i 2 c clock input/output (channel 0/1): i 2 c clock input/output pins that have bus-driving capability. the output of scl0 is an nmos open-drain type. i 2 c bus interface (iic) (optionk) (only for the w- mask version of the h8s/2638, h8s/2639, and h8s/2630) sda0, sda1 i/o i 2 c data input/output (channel 0/1): i 2 c data input/output pins that have bus-driving capability. the output of sda0 is an nmos open-drain type. notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. the h8s/2639 and h8s/2635 groups have no osc1 and osc2 pins. 2. the fwe pin is functional only in the flash memory version. the fwe pin is a nc pin in the mask rom versions. in the mask rom version, the fwe pin must be left open or be connected to vss. 3. the htxd1 and hrxd1 pins are not supported in h8s/2635 group. 4. the po15 to po8 output are not supported in h8s/2635 group. 5. the da1 and da0 output are not supported in h8s/2635 group.
section 1 overview rev. 6.00 feb 22, 2005 page 23 of 1484 rej09b0103-0600 1.4 differences between h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634 there are four versions of the h8s/2636, including rom and u-mask options; there are six versions of the h8s/2638, including rom, u-mask, and w-mask options; and there are four versions of the h8s/2639, including rom, u-mask, and w-mask options; and there are six versions of the h8s/2630, including rom, u-mask, and w-mask options. the specifications of these products are compared in table 1-4 below. table 1-4 comparison of product specifications product specifications product type model rom ram subclock function i 2 c bus interface hcan dtc, pbc, ppg, dac power-down modes hd64f2636f no see section 23a, power- down modes hd64f2636uf 128-kbyte on-chip flash memory yes no see section 23b, power- down modes hd6432636f no see section 23a, power- down modes h8s/2636 hd6432636uf 128-kbyte mask rom 4-kbyte sram yes no see section 23b, power- down modes hd64f2638f no see section 23a, power- down modes hd64f2638uf no hd64f2638wf 256-kbyte on-chip flash memory yes yes see section 23b, power- down modes hd6432638f no see section 23a, power- down modes hd6432638uf no h8s/2638 hd6432638wf 256-kbyte mask rom 16-kbyte sram yes yes 2 channels yes see section 23b, power- down modes
section 1 overview rev. 6.00 feb 22, 2005 page 24 of 1484 rej09b0103-0600 product specifications product type model rom ram subclock function i 2 c bus interface hcan dtc, pbc, ppg, dac power-down modes hd64f2639uf no hd64f2639wf 256-kbyte on-chip flash memory yes hd6432639uf no h8s/2639 * 1 hd6432639wf 256-kbyte mask rom 16-kbyte sram yes yes see section 23b, power- down modes hd64f2630f no see section 23a, power- down modes hd64f2630uf no hd64f2630wf 384-kbyte on-chip flash memory yes yes see section 23b, power- down modes hd6432630f no see section 23a, power- down modes hd6432630uf no h8s/2630 hd6432630wf 384-kbyte mask rom 16-kbyte sram yes yes 2 channels yes hd64f2635f 192-kbyte on-chip flash memory h8s/2635 * 1 hd6432635f * 2 192-kbyte mask rom h8s/2634 * 1 hd6432634f * 2 128-kbyte mask rom 6-kbyte sram yes no 1 channel no see section 23b, power- down modes notes: 1. for details of the h8s/2639, h8s/2635, and h8s/2634 clock pulse generator, see section 22b, clock pulse generator (h8s/2639 group, h8s/2635 group). 2. under development
section 2 cpu rev. 6.00 feb 22, 2005 page 25 of 1484 rej09b0103-0600 section 2 cpu 2.1 overview the h8s/2600 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2600 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2600 cpu has the following features. ? upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs ? general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? sixty-nine basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? multiply-and-accumulate instruction ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally)
section 2 cpu rev. 6.00 feb 22, 2005 page 26 of 1484 rej09b0103-0600 ? high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate : 20 mhz ? 8/16/32-bit register-register add/subtract : 50 ns ? 8 8-bit register-register multiply : 150 ns ? 16 8-bit register-register divide : 600 ns ? 16 16-bit register-register multiply : 200 ns ? 32 16-bit register-register divide : 1000 ns ? two cpu operating modes ? normal mode * ? advanced mode note: * not available in the chip. ? power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. ? register configuration the mac register is supported only by the h8s/2600 cpu. ? basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. ? number of execution states the number of execution states of the mulxu and mulxs instructions is different in each cpu. execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21
section 2 cpu rev. 6.00 feb 22, 2005 page 27 of 1484 rej09b0103-0600 in addition, there are differences in address space, ccr and exr register functions, power-down modes, etc., depending on the model. 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2600 cpu has the following enhancements. ? more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added ? expanded address space ? normal mode * supports the same 64-kbyte address space as the h8/300 cpu ? advanced mode supports a maximum 16-mbyte address space note: * not available in the chip. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced ? signed multiply and divide instructions have been added ? a multiply-and-accumulate instruction has been added ? two-bit shift instructions have been added ? instructions for saving and restoring multiple registers have been added ? a test and set instruction has been added ? higher speed ? basic instructions execute twice as fast
section 2 cpu rev. 6.00 feb 22, 2005 page 28 of 1484 rej09b0103-0600 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2600 cpu has the following enhancements. ? additional control register ? one 8-bit and two 32-bit control registers have been added ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced ? a multiply-and-accumulate instruction has been added ? two-bit shift instructions have been added ? instructions for saving and restoring multiple registers have been added ? a test and set instruction has been added ? higher speed ? basic instructions execute twice as fast 2.2 cpu operating modes the h8s/2600 cpu has two operating modes: normal and advanced. normal mode * supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally a maximum 16-mbyte program area and a maximum of 4 gbytes for program and data areas combined). the mode is selected by the mode pins of the microcontroller. note: * not available in the chip. cpu operating modes note: * not available in the chip. normal mode * advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbytes for program and data areas combined figure 2-1 cpu operating modes
section 2 cpu rev. 6.00 feb 22, 2005 page 29 of 1484 rej09b0103-0600 (1) normal mode (not available in the chip) the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@?rn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits (figure 2-2). the exception vector table differs depending on the microcontroller. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2-2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16-
section 2 cpu rev. 6.00 feb 22, 2005 page 30 of 1484 rej09b0103-0600 bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1 * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 figure 2-3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used.
section 2 cpu rev. 6.00 feb 22, 2005 page 31 of 1484 rej09b0103-0600 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved reset exception vector (reserved for system use) reserved exception vector 1 reserved h'00000010 h'00000008 h'00000007 figure 2-4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table.
section 2 cpu rev. 6.00 feb 22, 2005 page 32 of 1484 rej09b0103-0600 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1 * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 reserved figure 2-5 stack structure in advanced mode
section 2 cpu rev. 6.00 feb 22, 2005 page 33 of 1484 rej09b0103-0600 2.3 address space figure 2-6 shows a memory map of the h8s/2600 cpu. the h8s/2600 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode * data area program area cannot be used by the chip note: * not available in the chip. figure 2-6 memory map
section 2 cpu rev. 6.00 feb 22, 2005 page 34 of 1484 rej09b0103-0600 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2-7. there are two types of registers: general registers and control registers. t ???? i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend: stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * cannot be used as an interrupt mask bit in the chip. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 sign extension 63 32 41 0 31 mac macl half-carry flag user bit negative flag zero flag overflow flag carry flag multiply-accumulate register h: u: n: z: v: c: mac: mach figure 2-7 cpu registers
section 2 cpu rev. 6.00 feb 22, 2005 page 35 of 1484 rej09b0103-0600 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2-8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2-8 usage of general registers
section 2 cpu rev. 6.00 feb 22, 2005 page 36 of 1484 rej09b0103-0600 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2-9 shows the stack. free area stack area sp (er7) figure 2-9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), 8-bit condition-code register (ccr), and 64-bit multiply-accumulate register (mac). (1) program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored (when an instruction is fetched, the least significant pc bit is regarded as 0). (2) extended control register (exr) this 8-bit register contains the trace bit (t) and three interrupt mask bits (i2 to i0). bit 7?trace bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3?reserved: these bits are reserved. they are always read as 1.
section 2 cpu rev. 6.00 feb 22, 2005 page 37 of 1484 rej09b0103-0600 bits 2 to 0?interrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?interrupt mask bit (i): masks interrupts other than nmi when set to 1 (nmi is accepted regardless of the i bit setting). the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. bit 6?user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details, refer to section 5, interrupt controller. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2?zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit
section 2 cpu rev. 6.00 feb 22, 2005 page 38 of 1484 rej09b0103-0600 the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. (4) multiply-accumulate register (mac) this 64-bit register stores the results of multiply-and-accumulate operations. it consists of two 32- bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are a sign extension. 2.4.4 initial register values reset exception handling loads the cpu's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset.
section 2 cpu rev. 6.00 feb 22, 2005 page 39 of 1484 rej09b0103-0600 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2-10 shows the data formats in general registers. 7 6 5 4 3 2 1 0 don?t care 70 don ? t care 76543210 43 70 70 don?t care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don ? t care upper lower 43 70 don?t care 70 don ? t care 70 figure 2-10 general register data formats
section 2 cpu rev. 6.00 feb 22, 2005 page 40 of 1484 rej09b0103-0600 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend: ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2-10 general register data formats (cont)
section 2 cpu rev. 6.00 feb 22, 2005 page 41 of 1484 rej09b0103-0600 2.5.2 memory data formats figure 2-11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2-11 memory data formats when er7 is used as an address register to access the stack, the operand size should be word size or longword size.
section 2 cpu rev. 6.00 feb 22, 2005 page 42 of 1484 rej09b0103-0600 2.6 instruction set 2.6.1 overview the h8s/2600 cpu has 69 types of instructions. the instructions are classified by function in table 2-1. table 2-1 instruction classification function instructions size types data transfer mov bwl 5 pop * 1 , push * 1 wl ldm * 5 , stm * 5 l movfpe * 3 , movtpe * 3 b arithmetic add, sub, cmp, neg bwl 23 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas * 4 b mac, ldmac, stmac, clrmac ? logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 69 types legend: b: byte w: word l: longword notes: 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. not available in the chip. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. 5. only registers er0 to er6 should be used when using the stm/ldm instruction.
section 2 cpu rev. 6.00 feb 22, 2005 page 43 of 1484 rej09b0103-0600 2.6.2 instructions and addressing modes table 2-2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu can use. table 2-2 combinations of instructions and addressing modes addressing modes function data transfer arithmetic operations instruction mov bwl bwl bwl bwl bwl bwl b bwl ? bwl ? ? ? ? pop, push ? ? ? ? ? ? ? ? ? ? ? ? ? wl ldm * 3 , stm * 3 ? ? ? ? ? ? ? ? ? ? ? ? ? l add, cmp bwl bwl ? ? ? ? ? ? ? ? ? ? ? ? sub wl bwl ? ? ? ? ? ? ? ? ? ? ? ? addx, subx b b ? ? ? ? ? ? ? ? ? ? ? ? adds, subs ? l ? ? ? ? ? ? ? ? ? ? ? ? inc, dec ? bwl ? ? ? ? ? ? ? ? ? ? ? ? daa, das ? b ? ? ? ? ? ? ? ? ? ? ? ? neg ? bwl ? ? ? ? ? ? ? ? ? ? ? ? extu, exts ? wl ? ? ? ? ? ? ? ? ? ? ? ? tas * 2 ? ? b ? ? ? ? ? ? ? ? ? ? ? mac ? ? ? ? ? ? ? ? ? ? ? ? ? clrmac ? ? ? ? ? ? ? ? ? ? ? ? ? movfpe * 1 , ? ? ? ? ? ? ? b ? ? ? ? ? ? movtpe * 1 mulxu, ? bw ? ? ? ? ? ? ? ? ? ? ? ? divxu mulxs, ? bw ? ? ? ? ? ? ? ? ? ? ? ? divxs ldmac, ? l ? ? ? ? ? ? ? ? ? ? ? ? stmac #xx rn @ern @(d:16,ern) @(d:32,ern) @ ? ern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 ?
section 2 cpu rev. 6.00 feb 22, 2005 page 44 of 1484 rej09b0103-0600 addressing modes function logic operations system control block data transfer shift bit manipulation branch instruction and, or, bwl bwl ? ? ? ? ? ? ? ? ? ? ? ? xor andc, b ? ? ? ? ? ? ? ? ? ? ? ? ? orc, xorc bcc, bsr ? ? ? ? ? ? ? ? ? ? ? ? jmp, jsr ? ? ? ? ? ? ? ? ? ? ? ? rts ? ? ? ? ? ? ? ? ? ? ? ? ? trapa ? ? ? ? ? ? ? ? ? ? ? ? ? rte ? ? ? ? ? ? ? ? ? ? ? ? ? sleep ? ? ? ? ? ? ? ? ? ? ? ? ? ldc b b w w w w ? w ? w ? ? ? ? stc ? b w w w w ? w ? w ? ? ? ? not ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? b b ? ? ? b b ? b ? ? ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw legend: b: byte w: word l: longword #xx rn @ern @(d:16,ern) @(d:32,ern) @ ? ern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 ? notes: 1. not available in the chip. 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. 3. only registers er0 to er6 should be used when using the stm/ldm instruction.
section 2 cpu rev. 6.00 feb 22, 2005 page 45 of 1484 rej09b0103-0600 2.6.3 table of instructions classified by function table 2-3 summarizes the instructions in each functional category. the notation used in table 2-3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
section 2 cpu rev. 6.00 feb 22, 2005 page 46 of 1484 rej09b0103-0600 table 2-3 instructions classified by function type instruction size * 1 function data transfer mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn @?sp pushes a register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. ldm * 2 l @sp+ rn (register list) pops two or more general registers from the stack. stm * 2 l rn (register list) @?sp pushes two or more general registers onto the stack.
section 2 cpu rev. 6.00 feb 22, 2005 page 47 of 1484 rej09b0103-0600 type instruction size * 1 function arithmetic operations add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction). addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2 (byte operands can be incremented or decremented by 1 only). adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder.
section 2 cpu rev. 6.00 feb 22, 2005 page 48 of 1484 rej09b0103-0600 type instruction size * 1 function arithmetic operations divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd ? 0, 1 ( of @erd) * 3 tests memory contents, and sets the most significant bit (bit 7) to 1. mac ? (eas) (ead) + mac mac performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. the following operations can be performed: 16 bits 16 bits + 32 bits 32 bits, saturating 16 bits 16 bits + 42 bits 42 bits, non-saturating clrmac ? 0 mac clears the multiply-accumulate register to zero. ldmac stmac lrs mac, mac rd transfers data between a general register and a multiply-accumulate register.
section 2 cpu rev. 6.00 feb 22, 2005 page 49 of 1484 rej09b0103-0600 type instruction size * 1 function logic operations and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement of general register contents. shift operations shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible.
section 2 cpu rev. 6.00 feb 22, 2005 page 50 of 1484 rej09b0103-0600 type instruction size * 1 function bit- manipulation instructions bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c [ ? ( of ) ] c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data.
section 2 cpu rev. 6.00 feb 22, 2005 page 51 of 1484 rej09b0103-0600 type instruction size * 1 function bit- manipulation instructions bxor bixor b b c ( of ) c exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? [ ( of ) ] c exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data.
section 2 cpu rev. 6.00 feb 22, 2005 page 52 of 1484 rej09b0103-0600 type instruction size * 1 function branch instructions bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine
section 2 cpu rev. 6.00 feb 22, 2005 page 53 of 1484 rej09b0103-0600 type instruction size * 1 function trapa ? starts trap-instruction exception handling. rte ? returns from an exception-handling routine. system control instructions sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter.
section 2 cpu rev. 6.00 feb 22, 2005 page 54 of 1484 rej09b0103-0600 type instruction size * 1 function block data transfer instruction eepmov.b eepmov.w ? ? if r4l 0 then repeat @er5+ @er6+ r4l?1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4?1 r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. notes: 1. size refers to the operand size. b: byte w: word l: longword 2. only registers er0 to er6 should be used when using the stm/ldm instruction. 3. only register er0, er1, er4, or er5 should be used when using the tas instruction. 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). (1) operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
section 2 cpu rev. 6.00 feb 22, 2005 page 55 of 1484 rej09b0103-0600 (4) condition field: specifies the branching condition of bcc instructions. figure 2-12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2-12 instruction formats (examples)
section 2 cpu rev. 6.00 feb 22, 2005 page 56 of 1484 rej09b0103-0600 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2-4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2-4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register direct?rn: the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. (2) register indirect?@ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). (3) register indirect with displacement?@(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added.
section 2 cpu rev. 6.00 feb 22, 2005 page 57 of 1484 rej09b0103-0600 (4) register indirect with post-increment or pre-decrement?@ern+ or @-ern: ? register indirect with post-increment?@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. ? register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. (5) absolute address?@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2-5 indicates the accessible absolute address ranges. table 2-5 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * not available in the chip.
section 2 cpu rev. 6.00 feb 22, 2005 page 58 of 1484 rej09b0103-0600 (6) immediate?#xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative?@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect?@@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode * , h'000000 to h'0000ff in advanced mode). in normal mode * the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. note: * not available in the chip.
section 2 cpu rev. 6.00 feb 22, 2005 page 59 of 1484 rej09b0103-0600 (a) normal mode * (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address note: * not available in the chip. figure 2-13 branch address specification in memory indirect mode if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address (for further information, see section 2.5.2, memory data formats). 2.7.2 effective address calculation table 2-6 indicates how effective addresses are calculated in each addressing mode. in normal mode * the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. note: * not available in the chip.
section 2 cpu rev. 6.00 feb 22, 2005 page 60 of 1484 rej09b0103-0600 table 2.6 effective address calculation register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @ ? ern 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care
section 2 cpu rev. 6.00 feb 22, 2005 page 61 of 1484 rej09b0103-0600 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff don ? t care 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care sign extension
section 2 cpu rev. 6.00 feb 22, 2005 page 62 of 1484 rej09b0103-0600 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? normal mode * ? advanced mode 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents h'00 don ? t care 24 23 don ? t care don ? t care note: * not available in the chip.
section 2 cpu rev. 6.00 feb 22, 2005 page 63 of 1484 rej09b0103-0600 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2-14 shows a diagram of the processing states. figure 2-15 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. see section 23a and 23b, power-down modes, for details. figure 2-14 processing states
section 2 cpu rev. 6.00 feb 22, 2005 page 64 of 1484 rej09b0103-0600 exception handling state bus-released state hardware standby mode * 2 software standby mode reset state * 1 sleep mode power-down state * 3 program execution state end of bus request bus request interrupt request external interrupt request res = high request for exc eption handling stby = high, res = low end of bus request bus request sleep instruction with ssby = 0 sleep instruct ion with ssby = 1 notes: 1. 2. 3. from any state except hardware standby mode, a transition to the reset state occurs whenever re s goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when stby goes low. apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. see section 23a, 23b, power-down modes. end of exception handling reset state figure 2-15 state transitions 2.8.2 reset state when the res goes low, all current processing stops and the cpu enters the reset state. in reset state all interrupts are disenabled. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to section 12, watchdog timer.
section 2 cpu rev. 6.00 feb 22, 2005 page 65 of 1484 rej09b0103-0600 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. (1) types of exception handling and their priority exception handling is performed for traces, resets, interrupts, and trap instructions. table 2-7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2-7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. trace end of instruction execution or end of exception-handling sequence * 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence interrupt end of instruction execution or end of exception-handling sequence * 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 3 notes: 1. traces are enabled only in interrupt control mode 2. trace exception-handling is not executed at the end of the rte instruction. 2. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 3. trap instruction exception handling is always accepted, in the program execution state.
section 2 cpu rev. 6.00 feb 22, 2005 page 66 of 1484 rej09b0103-0600 (2) reset exception handling after the res pin has gone low and the reset state has been entered, when res goes high again, reset exception handling starts. the cpu enters the reset state when the res is low. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. (3) traces traces are enabled only in interrupt control mode 2. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control mode 0, regardless of the state of the t bit. (4) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2-16 shows the stack after exception handling ends.
section 2 cpu rev. 6.00 feb 22, 2005 page 67 of 1484 rej09b0103-0600 (c) interrupt control mode 0 (d) interrupt control mode 2 ccr pc (24 bits) sp ccr pc (24 bits) sp exr reserved * 1 (a) interrupt control mode 0 (b) interrupt control mode 2 ccr ccr * 1 pc (16 bits) sp ccr ccr * 1 pc (16 bits) sp exr reserved * 1 normal mode * 2 a dvanced mode notes: 1. ignored when returning. 2. not available in the chip. figure 2-16 stack structure after exception handling (examples)
section 2 cpu rev. 6.00 feb 22, 2005 page 68 of 1484 rej09b0103-0600 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. bus masters other than the cpu is data transfer controller (dtc). for further details, refer to section 7, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual m odules, other than the cpu. subactive mode, subsleep mode, and watch mode are power-down states using subclock input. for details, refer to section 23a, 23b, power-down modes. (1) sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the software standby bit (ssby) in the standby control register (sbycr) is cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instructi on. the contents of cpu registers are retained. (2) software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is set to 0, and the pss bit in tcsr (wdt1) is set to 0. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. (3) hardware standby mode: a transition to hardware standby mode is made when the stby pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained.
section 2 cpu rev. 6.00 feb 22, 2005 page 69 of 1484 rej09b0103-0600 2.9 basic timing 2.9.1 overview the h8s/2600 cpu is driven by a system clock, denoted by the symbol . the period from one rising edge of to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2-17 shows the on-chip memory access cycle. figure 2-18 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t 1 address read data write data read access write access figure 2-17 on-chip memory access cycle
section 2 cpu rev. 6.00 feb 22, 2005 page 70 of 1484 rej09b0103-0600 bus cycle t 1 unchanged a ddress bus as rd hwr , lwr data bus high high high high-impedance state figure 2-18 pin states during on-chip memory access
section 2 cpu rev. 6.00 feb 22, 2005 page 71 of 1484 rej09b0103-0600 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2-19 shows the access t iming for the on-chip supporting m odules. figure 2-20 shows the pin states. bus cycle t 1 t 2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus figure 2-19 on-chip supporting module access cycle
section 2 cpu rev. 6.00 feb 22, 2005 page 72 of 1484 rej09b0103-0600 bus cycle t 1 t 2 unchanged a ddress bus as rd hwr , lwr data bus high high high high-impedance state figure 2-20 pin states during on-chip supporting module access
section 2 cpu rev. 6.00 feb 22, 2005 page 73 of 1484 rej09b0103-0600 2.9.4 on-chip hcan module access timing on-chip hcan module access is performed in four states. the data bus width is 16 bits. wait states can be inserted by means of a wait request from the hcan. on-chip hcan module access timing is shown in figures 2-21 and 2-22, and the pin states in figure 2-23. internal address bus hcan read signal internal data bus hcan write signal internal data bus bus cycle t 1 address read write read data write data t 3 t 2 t 4 figure 2-21 on-chip hcan module access cycle (no wait state)
section 2 cpu rev. 6.00 feb 22, 2005 page 74 of 1484 rej09b0103-0600 internal address bus hcan read signal internal data bus hcan write signal internal data bus bus cycle t 1 address read write t 3 t 2 t w read data write data t w t 4 figure 2-22 on-chip hcan module access cycle (wait states inserted) t 1 t 3 t 2 t 4 bus cycle as rd hwr , lwr data bus high high high held a ddress bus high-impedance state figure 2-23 pin states in on-chip hcan module access
section 2 cpu rev. 6.00 feb 22, 2005 page 75 of 1484 rej09b0103-0600 2.9.5 port h and j register access timing accesses to port h and j registers and the on-chip motor control pwm timer module are performed in four states. the data bus width is 8 or 16 bits depending on the internal i/o register. access timing for port h and j registers and the on-chip motor control pwm timer module is shown in figure 2-24, and the pin states are shown in figure 2-25. bus cycle t 1 t 2 t 3 t 4 address read data write data internal address bus internal data bus write signal internal data bus read signal read write figure 2-24 access cycle for ports h and j registers and on-chip motor control pwm timer module
section 2 cpu rev. 6.00 feb 22, 2005 page 76 of 1484 rej09b0103-0600 bus cycle t 1 t 2 t 3 t 4 a ddress bus rd hwr , lwr data bus as high impedance held high high high figure 2-25 pin states in access to ports h and j registers and on-chip motor control pwm timer module 2.9.6 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 7, bus controller.
section 2 cpu rev. 6.00 feb 22, 2005 page 77 of 1484 rej09b0103-0600 2.10 usage note 2.10.1 tas instruction only register er0, er1, er4, or er5 should be used when using the tas instruction. the tas instruction is not generated by the renesas technology h8s family and h8/300 series c/c++ compilers. if the tas instruction is used as a user-defined intrinsic function, ensure that only register er0, er1, er4, or er5 is used. 2.10.2 stm/ldm instructions with stm and ldm instructions, register er7 cannot be used as a register that can be saved (stm) or restored (ldm) since it is the stack pointer. the number of registers that can be saved (stm) or restored (ldm) by a single instruction is two, three, or four. the registers that can be used in these cases are as follows. two registers: er0?er1, er2?er3, er4?er5 three registers: er0?er2, er4?er6 four registers: er0?er3 the renesas technology h8s family and h8/300 series c/c++ compilers do not generate stm/ldm instructions that include er7. 2.10.3 caution to observe when using bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read data in a unit of byte, then, after bit manipulation, they write data in a unit of byte. therefore, caution must be exercised when executing any of these instructions for registers and ports that include write-only bits. the bclr instruction can be used to clear the flag of an internal i/o register to 0. in that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance.
section 2 cpu rev. 6.00 feb 22, 2005 page 78 of 1484 rej09b0103-0600
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 79 of 1484 rej09b0103-0600 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the chip has four operating modes (modes 4 to 7). these modes enable selection of the cpu operating mode, enabling/disabling of on-chip rom, and the initial bus width setting, by setting the mode pins (md2 to md0). table 3-1 lists the mcu operating modes. table 3-1 mcu operating mode selection external data bus mcu operating mode md2 md1 md0 cpu operating mode description on-chip rom initial width max. width 0 * 000? ? ? ? ? 1 * 1? 2 * 10 3 * 1 4 1 0 0 advanced disabled 16 bits 16 bits 51 on-chip rom disabled, expanded mode 8 bits 16 bits 610 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode ? ? note: * not available in the chip. the cpu?s architecture allows for 4 gbytes of address space, but the chip actually accesses a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 80 of 1484 rej09b0103-0600 the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set. note that the functions of each pin depend on the operating mode. the chip can be used only in modes 4 to 7. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 3.1.2 register configuration the chip has a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) that controls the operation of the chip. table 3-2 summarizes these registers. table 3-2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r undetermined h'fde7 system control register syscr r/w h'01 h'fde5 pin function control register pfcr r/w h'0d/h'00 h'fdeb note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) 7 ? 1 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? * r 2 mds2 ? * r 1 mds1 ? * r note: * determined by pins md2 to md0. bit initial value r/w : : : mdcr is an 8-bit register that indicates the current operating mode of the chip.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 81 of 1484 rej09b0103-0600 bit 7?reserved: only 1 should be written to these bits. bits 6 to 3?reserved: these bits are always read as 0 and cannot be modified. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read-only bits, and they cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are cancelled by a reset. 3.2.2 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 ? 0 ? 1 ? 0 ? bit initial value r/w : : : syscr is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the mac instruction, selects the interrupt control mode, selects the detected edge for nmi, and enables or disenables on-chip ram. syscr is initialized to h'01 by a reset and in hardware standby mode. syscr is not initialized in software standby mode. bit 7?mac saturation (macs): selects either saturating or non-saturating calculation for the mac instruction. bit 7 macs description 0 non-saturating calculation for mac instruction (initial value ) 1 saturating calculation for mac instruction bit 6?reserved: this bit is always read as 0 and cannot be modified.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 82 of 1484 rej09b0103-0600 bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 intm1 intm0 interrupt control mode description 0 0 0 control of interrupts by i bit (initial value ) 1 ? setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 ? setting prohibited bit 3?nmi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value ) 1 an interrupt is requested at the rising edge of nmi input bit 2? reserved: only 0 should be written to this bit. bit 1?reserved: this bit is always read as 0 and cannot be modified. bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset status is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value ) note: when the dtc is used, the rame bit must not be cleared to 0.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 83 of 1484 rej09b0103-0600 3.2.3 pin function control register (pfcr) 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w bit initial value r/w : : : pfcr is an 8-bit readable-writeable register that performs address output control in on-chip rom- enabled expansion mode. pfcr is initialized to h'0d/h'00 by a reset and in the hardware standby mode. bits 7 to 4? reserved: only 0 should be written to these bits. bits 3 to 0?address output enable 3 to 0 (ae3 to ae0): these bits select enabling or disabling of address outputs a8 to a23 in on-chip rom-disabled expansion mode and on-chip rom-enabled expansion mode. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 84 of 1484 rej09b0103-0600 bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0 0 0 0 a8 to a23 address output disabled (initial value * ) 1 a8 address output enabled; a9 to a23 address output disabled 1 0 a8, a9 address output enabled; a10 to a23 address output disabled 1 a8 to a10 address output enabled; a11 to a23 address output disabled 1 0 0 a8 to a11 address output enabled; a12 to a23 address output disabled 1 a8 to a12 address output enabled; a13 to a23 address output disabled 10 a8 to a13 address output enabled; a14 to a23 address output disabled 1 a8 to a14 address output enabled; a15 to a23 address output disabled 1 0 0 0 a8 to a15 address output enabled; a16 to a23 address output disabled 1 a8 to a16 address output enabled; a17 to a23 address output disabled 1 0 a8 to a17 address output enabled; a18 to a23 address output disabled 1 a8 to a18 address output enabled; a19 to a23 address output disabled 100 a8 to a19 address output enabled; a20 to a23 address output disabled 1 a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * ) 1 0 a8 to a21 address output enabled; a22, a23 address output disabled 1 a8 to a23 address output enabled note: * in on-chip rom-enabled expansion mode, bits ae3 to ae0 are initialized to b'0000. in on-chip rom-disabled expansion mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 85 of 1484 rej09b0103-0600 3.3 operating mode descriptions 3.3.1 mode 4 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports 1, a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8- bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 mode 5 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports 1, a, b, and c function as an address bus, port d function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.3 mode 6 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. ports 1, a, b, and c function as input port pins immediately after a reset. address output can be performed by setting the corresponding ddr (data direction register) bits to 1. port d functions as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 86 of 1484 rej09b0103-0600 3.3.4 mode 7 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports. 3.4 pin functions in each operating mode the pin functions of ports 1 and a to f vary depending on the operating mode. table 3-3 shows their functions in each operating mode. table 3-3 pin functions in each mode port mode 4 mode 5 mode 6 mode 7 port a p/a * p/a * p * /a p port b p/a * p/a * p * /a p port c aap * /a p port d dddp port e p/d * p * /d p * /d p port f pf7 p/c * p/c * p/c * p * /c pf6 to pf4cccp pf3 p/c * p * /c p * /c pf0 p * /c p * /c p * /c port 1 p11 to p13 p * /a p * /a p * /a p p10 p/a * p/a * p * /a legend: p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 87 of 1484 rej09b0103-0600 3.5 address map in each operating mode an address map of the h8s/2636 is shown in figure 3-1. an address map of the h8s/2638 and h8s/2639 is shown in figure 3-2. an address map of the h8s/2630 is shown in figure 3-3. an address map of the h8s/2635 is shown in figure 3-4. an address map of the h8s/2634 is shown in figure 3-5. the address space is 16 mbytes in modes 4 to 7 (advanced modes). the address space is divided into eight areas for modes 4 to 7. for details, see section 7, bus controller.
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 88 of 1484 rej09b0103-0600 h'000000 h'ffb000 h'ffafff h'ffefc0 h'fff800 h'020000 h'01ffff h'000000 h'01ffff h'000000 h'ffefbf external address space on-chip ram * reserved area on-chip ram * external address space internal i/o registers external address space internal i/o registers on-chip ram * external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers internal i/o registers note: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffffbf h'ffe000 h'ffdfff h'ffe000 h'ffdfff h'ffb000 h'ffafff h'ffe000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * reserved area on-chip ram external address space internal i/o registers h'ffffff h'ffffff h'fff800 h'ffff3f * external addresses can be accessed by clearing th rame bit in syscr to 0. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-1 memory map in each operating mode in the h8s/2636
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 89 of 1484 rej09b0103-0600 h'000000 h'ffb000 h'ffafff h'ffefc0 h'fff800 h'040000 h'03ffff h'000000 h'03ffff h'000000 h'ffefbf external address space on-chip ram * on-chip ram * external address space internal i/o registers external address space internal i/o registers on-chip ram * external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers internal i/o registers note: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffffbf h'ffb000 h'ffafff h'ffb000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * on-chip ram external address space internal i/o registers h'ffffff h'ffffff h'fff800 h'ffff3f * external addresses can be accessed by clearing th rame bit in syscr to 0. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-2 memory map in each operating mode in the h8s/2638 and h8s/2639
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 90 of 1484 rej09b0103-0600 h'000000 h'ffb000 h'ffafff h'ffefc0 h'fff800 h'060000 h'05ffff h'000000 h'05ffff h'000000 h'ffefbf external address space on-chip ram * on-chip ram * external address space internal i/o registers external address space internal i/o registers on-chip ram * external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers internal i/o registers note: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffffbf h'ffb000 h'ffafff h'ffb000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * on-chip ram external address space internal i/o registers h'ffffff h'ffffff h'fff800 h'ffff3f * external addresses can be accessed by clearing th rame bit in syscr to 0. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-3 memory map in each operating mode in the h8s/2630
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 91 of 1484 rej09b0103-0600 h'000000 h'ffb000 h'ffafff h'ffefc0 h'fff800 h'040000 h'03ffff h'030000 h'02ffff h'000000 h'02ffff h'000000 h'ffefbf external address space on-chip ram * reserved area on-chip ram * external address space internal i/o registers external address space internal i/o registers on-chip ram * external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers internal i/o registers note: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffffbf h'ffd800 h'ffd7ff h'ffd800 h'ffd7ff h'ffb000 h'ffafff h'ffd800 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * reserved area reserved area on-chip ram external address space internal i/o registers h'ffffff h'ffffff h'fff800 h'ffff3f * external addresses can be accessed by clearing th rame bit in syscr to 0. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-4 memory map in each operating mode in the h8s/2635
section 3 mcu operating modes rev. 6.00 feb 22, 2005 page 92 of 1484 rej09b0103-0600 h'000000 h'ffb000 h'ffafff h'ffefc0 h'fff800 h'040000 h'03ffff h'020000 h'01ffff h'000000 h'01ffff h'000000 h'ffefbf external address space on-chip ram * reserved area on-chip ram * external address space internal i/o registers external address space internal i/o registers on-chip ram * external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers internal i/o registers note: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffefbf h'fff7ff h'ffff3f h'ffff5f h'ffffbf h'ffffbf h'ffd800 h'ffd7ff h'ffd800 h'ffd7ff h'ffb000 h'ffafff h'ffd800 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * reserved area reserved area on-chip ram external address space internal i/o registers h'ffffff h'ffffff h'fff800 h'ffff3f * external addresses can be accessed by clearing th rame bit in syscr to 0. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-5 memory map in each operating mode in the h8s/2634
section 4 exception handling rev. 6.00 feb 22, 2005 page 93 of 1484 rej09b0103-0600 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4-1 indicates, exception handling may be caused by a reset, direct transition * , trap instruction, or interrupt. exception handling is prioritized as shown in table 4-1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times, in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits of syscr. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. table 4-1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog overflows. the cpu enters the reset state when the res pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 direct transition * 4 starts when a direct transition occurs due to execution of a sleep instruction. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state. 4. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. supported by the h8s/2635.
section 4 exception handling rev. 6.00 feb 22, 2005 page 94 of 1484 rej09b0103-0600 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extended register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception vector table the exception sources are classified as shown in figure 4-1. different vector addresses are assigned to different exception sources. table 4-2 lists the exception sources and their vector addresses. exception sources reset trace interrupts trap instruction external interrupts: nmi, irq5 to irq0 internal interrupts: 49 (+3: option) interrupt sources in on-chip supporting modules figure 4-1 exception sources
section 4 exception handling rev. 6.00 feb 22, 2005 page 95 of 1484 rej09b0103-0600 table 4-2 exception vector table vector address * 1 exception source vector number advanced mode reset 0 h'0000 to h'0003 reserved for system use 1 h'0004 to h'0007 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace 5 h'0014 to h'0017 direct transition * 3 6 h'0018 to h'001b external interrupt nmi 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 irq2 18 h'0048 to h'004b irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 21 h'0054 to h'0057 reserved for system use 22 h'0058 to h'005b 23 h'005c to h'005f internal interrupt * 2 24 ? 127 h'0060 to h'0063 ? h'01fc to h'01ff notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. 3. see section 23b.11, direct transition for details on direct transition. subclock functions are available in the u-mask and w-mask versions, and h8s/2635 group only.
section 4 exception handling rev. 6.00 feb 22, 2005 page 96 of 1484 rej09b0103-0600 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the res pin goes low, all current operations are stopped, and this lsi enters reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. when the res pin goes from low to high, reset exception handling starts. the h8s/2636 can also be reset by overflow of the watchdog timer. for details see section 12, watchdog timer. 4.2.2 reset sequence this lsi enters reset state when the res pin goes low. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-up. to reset during operation, hold the res pin low for at least 20 states. when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows. 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4-2 and 4-3 show examples of the reset sequence.
section 4 exception handling rev. 6.00 feb 22, 2005 page 97 of 1484 rej09b0103-0600 res internal address bus internal read signal internal write signal internal data bus vector fetch (1) (3) (5) high internal processing prefetch of first program instruction (2) (4) (1) (3) reset exception handling vector address (when power-on reset, (1) = h'000000, (3) = h'000002) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction (6) figure 4-2 reset sequence (modes 6 and 7)
section 4 exception handling rev. 6.00 feb 22, 2005 page 98 of 1484 rej09b0103-0600 res address bus rd hwr , lwr d15 to d0 (1) (3) high (2) (4) (5) (6) * * * vector fetch internal processing prefetch of first program instruction (1) (3) reset exception handling vector address (when reset, (1) = h'000000, (3) = h'000002) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction note: * 3 program wait states are inserted. figure 4-3 reset sequence (mode 4) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp).
section 4 exception handling rev. 6.00 feb 22, 2005 page 99 of 1484 rej09b0103-0600 4.2.4 state of on-chip supporting modules after reset release after reset release, mstpcra to mstpcrd are initialized to h'3f, h'ff, h'ff, and b'11****** *1 , respectively, and all modules except the dtc, enter module stop mode. consequently, on-chip supporting module registers cannot be read or written to. register reading and writing is enabled when module stop mode is exited. note: 1. the value of bits 5 to 0 is undefined. 4.3 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is canceled by clearing the t bit in exr to 0. it is not affected by interrupt masking. table 4-3 shows the state of ccr and exr after execution of trace exception handling. interrupts are accepted even within the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4-3 status of ccr and exr after trace exception handling ccr exr interrupt control mode iuii2 to i0t 0 trace exception handling cannot be used. 21??0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution.
section 4 exception handling rev. 6.00 feb 22, 2005 page 100 of 1484 rej09b0103-0600 4.4 interrupts interrupt exception handling can be requested by seven external sources (nmi, irq5 to irq0) and 49 internal sources in the on-chip supporting modules. figure 4-4 classifies the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit timer-pulse unit (tpu), serial communication interface (sci), data transfer controller (dtc), pc break controller (pbc), a/d converter, controller area network (hcan), motor control pwm timer, and i 2 c bus interface (iic). each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details of interrupts, see section 5, interrupt controller. notes: the dtc, pbc, and iic are not implemented in the h8s/2635 group. interrupts external interrupts internal interrupts nmi (1) irq5 to irq0 (6) wdt * 1 (2) tpu (26) sci (12) dtc (1) pbc (1) a/d converter (1) motor control pwm (2) hcan (4) * 3 iic * 2 (3) [option] numbers in parentheses are the numbers of interrupt sources. 1. when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. 3. 2 sources in the h8s/2635 group. notes: figure 4-4 interrupt sources and number of interrupts
section 4 exception handling rev. 6.00 feb 22, 2005 page 101 of 1484 rej09b0103-0600 4.5 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4-4 shows the status of ccr and exr after execution of trap instruction exception handling. table 4-4 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode iuii2 to i0t 0 1 ??? 21??0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution.
section 4 exception handling rev. 6.00 feb 22, 2005 page 102 of 1484 rej09b0103-0600 4.6 stack status after exception handling figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp sp ccr ccr * pc (16 bits) ccr ccr * pc (16 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (1) stack status after exception handling (normal modes: not available in the chip) sp sp ccr pc (24 bits) ccr pc (24 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (2) stack status after exception handling (advanced modes)
section 4 exception handling rev. 6.00 feb 22, 2005 page 103 of 1484 rej09b0103-0600 4.7 notes on use of the stack when accessing word data or longword data, the chip assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4-6 shows an example of what happens when the sp value is odd. sp legend: note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @ ? er7 sp set to h'fffeff trap instruction executed data saved above sp contents of ccr lost ccr: condition code register pc: program counter r1l: general register r1l sp: stack pointer figure 4-6 operation when sp value is odd
section 4 exception handling rev. 6.00 feb 22, 2005 page 104 of 1484 rej09b0103-0600
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 105 of 1484 rej09b0103-0600 section 5 interrupt controller 5.1 overview 5.1.1 features the chip controls interrupts by means of an interrupt controller. the interrupt controller has the following features: ? two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? seven external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq5 to irq0. ? dtc control * ? dtc activation is performed by means of interrupts. note: * the h8s/2635 group is not equipped with a dtc.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 106 of 1484 rej09b0103-0600 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5-1. syscr nmi input irq input internal interrupt request swdtend to rm0 intm1, intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu iscr: ier: isr: ipr: syscr: irq sense control register irq enable register irq status register interrupt priority register system control register legend: figure 5-1 block diagram of interrupt controller
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 107 of 1484 rej09b0103-0600 5.1.3 pin configuration table 5-1 summarizes the pins of the interrupt controller. table 5-1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 5 to 0 irq5 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 register configuration table 5-2 summarizes the registers of the interrupt controller. table 5-2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'01 h'fde5 irq sense control register h iscrh r/w h'00 h'fe12 irq sense control register l iscrl r/w h'00 h'fe13 irq enable register ier r/w h'00 h'fe14 irq status register isr r/(w) * 2 h'00 h'fe15 interrupt priority register a ipra r/w h'77 h'fec0 interrupt priority register b iprb r/w h'77 h'fec1 interrupt priority register c iprc r/w h'77 h'fec2 interrupt priority register d iprd r/w h'77 h'fec3 interrupt priority register e ipre r/w h'77 h'fec4 interrupt priority register f iprf r/w h'77 h'fec5 interrupt priority register g iprg r/w h'77 h'fec6 interrupt priority register h iprh r/w h'77 h'fec7 interrupt priority register j iprj r/w h'77 h'fec9 interrupt priority register k iprk r/w h'77 h'feca interrupt priority register l iprl r/w h'77 h'fecb interrupt priority register m iprm r/w h'77 h'fecc notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 108 of 1484 rej09b0103-0600 5.2 register descriptions note: the h8s/2635 group is not equipped with a dtc, a pc brake controller, or an hcan1. 5.2.1 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 ? 0 r/w 1 ? 0 ? bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'01 by a reset and in hardware standby mode. syscr is not initialized in software standby mode. bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. bit 5 bit 4 intm1 intm0 interrupt control mode description 0 0 0 interrupts are controlled by i bit (initial value ) 1 ? setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 ? setting prohibited bit 3?nmi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value ) 1 interrupt request generated at rising edge of nmi input
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 109 of 1484 rej09b0103-0600 5.2.2 interrupt priority registers a to h, j to m (ipra to iprh, iprj to iprm) 7 ? 0 ? 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 ? 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w : : : the ipr registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between ipr settings and interrupt sources is shown in table 5-3. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'77 by a reset and in hardware standby mode. bits 7 and 3?reserved: these bits are always read as 0 and cannot be modified. table 5-3 correspondence between interrupt sources and ipr settings bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2 irq4 irq3 irq5 iprc ? * 1 dtc * 3 iprd watchdog timer 0 ? * 1 ipre pc break * 3 a/d converter, watchdog timer 1 iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 iprh tpu channel 4 tpu channel 5 iprj ? * 1 sci channel 0 iprk sci channel 1 sci channel 2 iprl ? * 1 iic (option) * 2 iprm pwm channel 1, 2 hcan channel 1 * 3 hcan channel 0 notes: 1. reserved. these bits are always read as 1 and cannot be modified. 2. i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. the iic bit becomes reserved bit when this optional feature is not used. 3. the pc break, dtc, and hcan channel 1 are reserved in the h8s/2635 group.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 110 of 1484 rej09b0103-0600 as shown in table 5-3, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 5.2.3 irq enable register (ier) 7 ? 0 r/w 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq5 to irq0. ier is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6?reserved: these bits are always read as 0, and should only be written with 0. bits 5 to 0?irq5 to irq0 enable (irq5e to irq0e): these bits select whether irq5 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value ) 1 irqn interrupts enabled (n = 5 to 0)
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 111 of 1484 rej09b0103-0600 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh 15 ? 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : iscrl 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : the iscr registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq5 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode. bits 15 to 12?reserved: these bits are always read as 0, and should only be written with 0. bits 11 to 0?irq5 sense control a and b (irq5sca, irq5scb) to irq0 sense control a and b (irq0sca, irq0scb) bits 11 to 0 irq5scb to irq0scb irq5sca to irq0sca description 00 interrupt request generated at irq5 to irq0 input low level (initial value ) 1 interrupt request generated at falling edge of irq5 to irq0 input 1 0 interrupt request generated at rising edge of irq5 to irq0 input 1 interrupt request generated at both falling and rising edges of irq5 to irq0 input
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 112 of 1484 rej09b0103-0600 5.2.5 irq status register (isr) 7 ? 0 r/(w) * 6 ? 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * only 0 can be written, to clear the flag. : : : isr is an 8-bit readable/writable register that indicates the status of irq5 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 7 and 6?reserved: these bits are always read as 0. bits 5 to 0?irq5 to irq0 flags (irq5f to irq0f): these bits indicate the status of irq5 to irq0 interrupt requests.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 113 of 1484 rej09b0103-0600 bit n irqnf description 0 [clearing conditions] (initial value) ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 5 to 0)
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 114 of 1484 rej09b0103-0600 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq5 to irq0) and internal interrupts (49 sources). note: the h8s/2635 group is not equipped with a dtc, a pc brake controller, or an hcan1. the h8s/2635 group has 45 sources of internal interrupt. 5.3.1 external interrupts there are seven external interrupts: nmi and irq5 to irq0. of these, nmi and irq5 to irq0 can be used to restore the chip from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq5 to irq0 interrupts: interrupts irq5 to irq0 are requested by an input signal at pins irq5 to irq0 . interrupts irq5 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq5 to irq0 . ? enabling or disabling of interrupt requests irq5 to irq0 can be selected with ier. ? the interrupt priority level can be set with ipr. ? the status of interrupt requests irq5 to irq0 is indicated in isr. isr flags can be cleared to 0 by software.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 115 of 1484 rej09b0103-0600 a block diagram of interrupts irq5 to irq0 is shown in figure 5-2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n = 5 to 0 figure 5-2 block diagram of interrupts irq5 to irq0 figure 5-3 shows the timing of setting irqnf. irqn input pin irqnf f figure 5-3 timing of setting irqnf the vector numbers for irq5 to irq0 interrupt exception handling are 21 to 16. detection of irq5 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 and use the pin as an i/o pin for another function.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 116 of 1484 rej09b0103-0600 5.3.2 internal interrupts there are 49 sources for internal interrupts from on-chip supporting modules. ? for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. ? the interrupt priority level can be set by means of ipr. ? the dtc can be activated by a tpu, sci, or other interrupt request. when the dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 interrupt exception handling vector table table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 117 of 1484 rej09b0103-0600 table 5-4 interrupt sources, vector addresses, and interrupt priorities vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr priority nmi 7 h'001c high irq0 16 h'0040 ipra6 to 4 irq1 external pin 17 h'0044 ipra2 to 0 irq2 irq3 18 19 h'0048 h'004c iprb6 to 4 irq4 irq5 20 21 h'0050 h'0054 iprb2 to 0 reserved for system use ? 22 23 h'0058 h'005c ? swdtend (software activation interrupt end) dtc * 3 24 h'0060 iprc2 to 0 wovi0 (interval timer) watchdog timer 0 25 h'0064 iprd6 to 4 reserved for system use ? 26 h'0068 ? pc break pc break controller * 3 27 h'006c ipre6 to 4 adi (a/d conversion end) a/d 28 h'0070 ipre2 to 0 wovi1 (interval timer) watchdog timer 1 29 h'0074 reserved for system use ? 30 31 h'0078 h'007c ? tgi0a (tgr0a input capture/compare match) tgi0b (tgr0b input capture/compare match) tgi0c (tgr0c input capture/compare match) tgi0d (tgr0d input capture/compare match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0080 h'0084 h'0088 h'008c h'0090 iprf6 to 4 reserved for system use ? 37 to 39 h'0094 to h'009c ? low
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 118 of 1484 rej09b0103-0600 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr priority tgi1a (tgr1a input capture/compare match) tgi1b (tgr1b input capture/compare match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'00a0 h'00a4 h'00a8 h'00ac iprf2 to 0 high tgi2a (tgr2a input capture/compare match) tgi2b (tgr2b input capture/compare match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'00b0 h'00b4 h'00b8 h'00bc iprg6 to 4 tgi3a (tgr3a input capture/compare match) tgi3b (tgr3b input capture/compare match) tgi3c (tgr3c input capture/compare match) tgi3d (tgr3d input capture/compare match) tci3v (overflow 3) tpu channel 3 48 49 50 51 52 h'00c0 h'00c4 h'00c8 h'00cc h'00d0 iprg2 to 0 reserved for system use ? 53 to 55 h'00d4 to h'00dc ? tgi4a (tgr4a input capture/compare match) tgi4b (tgr4b input capture/compare match) tci4v (overflow 4) tci4u (underflow 4) tpu channel 4 56 57 58 59 h'00e0 h'00e4 h'00e8 h'00ec iprh6 to 4 low
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 119 of 1484 rej09b0103-0600 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr priority tgi5a (tgr5a input capture/compare match) tgi5b (tgr5b input capture/compare match) tci5v (overflow 5) tci5u (underflow 5) tpu channel 5 60 61 62 63 h'00f0 h'00f4 h'00f8 h'00fc iprh2 to 0 high reserved for system use ? 64 to 79 h'0100 to h'013c ? eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'0140 h'0144 h'0148 h'014c iprj2 to 0 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'0150 h'0154 h'0158 h'015c iprk6 to 4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 88 89 90 91 h'0160 h'0164 h'0168 h'016c iprk2 to 0 reserved for system use ? 92 to 99 h'0170 to h'018c ? i 2 ci0 (1-byte transmission/ reception completed) ddcsw1 (format switch) i 2 c channel 0 (option) * 2 100 101 h'0190 h'0194 iprl2 to 0 i 2 ci1 reserved for system use i 2 c channel 1 (option) * 2 102 103 h'0198 h'019c low
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 120 of 1484 rej09b0103-0600 vector address * 1 interrupt source origin of interrupt source vector number advanced mode ipr priority pwm1 pwm channel 1 104 h'01a0 iprm6 to 4 high pwm2 pwm channel 2 105 h'01a4 ers0, ovr0, rm1, sle0, rm0 hcan1 * 3 106 107 h'01a8 h'01ac ers0, ovr0, rm1, sle0, rm0 hcan0 108 109 h'01b0 h'01b4 iprm2 to 0 reserved for system use ? 110 h'01b8 111 h'01bc low notes: 1. lower 16 bits of the start address. 2. i 2 c is available as an option in the h8s/2638, h8s/2639, and h8s/2630 only. the product equipped with the i 2 c bus interface is the w-mask version. 3. the dtc, pc break, and hcan1 interrupts are reserved in the h8s/2635 group. 5.4 interrupt operation 5.4.1 interrupt control modes and interrupt operation interrupt operations in the chip differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5-5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr, and the masking state indicated by the i bit in the cpu?s ccr, and bits i2 to i0 in exr.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 121 of 1484 rej09b0103-0600 table 5-5 interrupt control modes syscr interrupt control mode intm1 intm0 priority setting registers interrupt mask bits description 0 0 0 ? i interrupt mask control is performed by the i bit. ? 1 ? ? setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. ? 1 ? ? setting prohibited figure 5-4 shows a block diagram of the priority decision circuit. interrupt acceptance control 8-level mask control default priority determination vector number interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5-4 block diagram of interrupt control operation
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 122 of 1484 rej09b0103-0600 (1) interrupt acceptance control in interrupt control mode 0, interrupt acceptance is controlled by the i bit in ccr. table 5-6 shows the interrupts selected in each interrupt control mode. table 5-6 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts legend: * : don't care (2) 8-level control in interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5-7 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0).
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 123 of 1484 rej09b0103-0600 (3) default priority determination when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5-8 shows operations and control signal functions in each interrupt control mode. table 5-8 operations and control signal functions in each interrupt control mode interrupt control setting interrupt acceptance control 8-level control mode intm1 intm0 i i2 to i0 ipr default priority determination t (trace) 000 im x ? ? * 2 ? 210x? * 1 im pr t legend: : interrupt operation control performed x: no operation (all interrupts enabled). im: used as interrupt mask bit pr: sets priority. ?: not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 124 of 1484 rej09b0103-0600 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpu?s ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. [3] interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] next, the i bit in ccr is set to 1. this masks all interrupts except nmi. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 125 of 1484 rej09b0103-0600 program execution status interrupt generated? nmi irq0 irq1 hcan i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5-5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 126 of 1484 rej09b0103-0600 5.4.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 127 of 1484 rej09b0103-0600 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5-6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 128 of 1484 rej09b0103-0600 5.4.4 interrupt exception handling sequence figure 5-7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data us (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address) instruction code (not executed) instruction prefetch address (not executed) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5-7 interrupt exception handling
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 129 of 1484 rej09b0103-0600 5.4.5 interrupt response times the chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5-9 are explained in table 5-10. table 5-9 interrupt response times normal mode * 5 advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 33 2 number of wait states until executing instruction ends * 2 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 3 pc, ccr, exr stack save 2 s k 3 s k 2 s k 3 s k 4 vector fetch s i s i 2s i 2s i 5 instruction fetch * 3 2 s i 2 s i 2 s i 2 s i 6 internal processing * 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and di vxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not implemented in the chip.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 130 of 1484 rej09b0103-0600 table 5-10 number of states in interrupt handling routine execution statuses object of access external device 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k legend: m: number of wait states in an external device access. 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instructi on, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5-8 shows an example in which the tciev bit in the tpu?s tier register is cleared to 0.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 131 of 1484 rej09b0103-0600 internal address bus internal write signal f tciev tcfv tcfv interrupt signal tier write cycle by cpu tcfv exception handling tier address figure 5-8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 times when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 132 of 1484 rej09b0103-0600 5.5.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 5.5.5 irq interrupts when operating by clock input, acceptance of input to an irq pin is synchronized with the clock. in software standby mode, the input is accepted asynchronously. for details on the input conditions, see section 24.5.2, control signal t iming. 5.5.6 notes on use of nmi interrupt when the system is operating normally under conditions conforming to the specified electrical properties, exception processing by the on-chip interrupt controller linked to the cpu is used to execute the nmi interrupt. when operation is not normal (runaway status) due to a software problem or abnormal input to one of the lsi?s pins, no operations can be guaranteed, including the nmi interrupt. in such cases it is possible to cause the lsi to return to normal program execution by applying an external reset.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 133 of 1484 rej09b0103-0600 5.6 dtc activation by interrupt note: the dtc is not implemented in the h8s/2635 group. 5.6.1 overview the dtc can be activated by an interrupt. in this case, the following options are available: ? interrupt request to cpu ? activation request to dtc ? selection of a number of the above for details of interrupt requests that can be used with to activate the dtc, see section 8, data transfer controller (dtc). 5.6.2 block diagram figure 5-9 shows a block diagram of the dtc interrupt controller. selection circuit dtcer dtvecr control logic determination of priority cpu dtc select signal irq interrupt on-chip supporting module clear signal interrupt controller i, i2 to i0 interrupt source clear signal interrupt request dtc activation request vector number cpu interrupt request vector number swdte clear signal clear signal figure 5-9 interrupt control for dtc
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 134 of 1484 rej09b0103-0600 5.6.3 operation the interrupt controller has three main functions in dtc control. (1) selection of interrupt source: interrupt factors are selected as dtc activation request or cpu interrupt request by the dtce bit of dtcera to dtcerg of dtc. by specifying the disel bit of the dtc?s mrb, it is possible to clear the dtce bit to 0 after dtc data transfer, and request a cpu interrupt. if dtc carries out the designate number of data transfers and the transfer counter reads 0, after dtc data transfer, the dtce bit is also cleared to 0, and a cpu interrupt requested. (2) determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see section 8.3.3, dtc vector table for the respective priority. (3) operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. table 5-11 shows the interrupt factor clear control and selection of interrupt factors by specification of the dtce bit of dtcera to dtcerg of dtc, and the disel bit of dtc?s mrb.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 135 of 1484 rej09b0103-0600 table 5-11 interrupt source selection and clearing control settings dtc interrupt source selection/clearing control dtce disel dtc cpu 0 * x ? 10 ? x 1 ? legend: ? : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. x : the relevant bit cannot be used. * : don?t care (4) notes on use: sci and a/d converter interrupt sources are cleared when the dtc reads or writes to the prescribed register.
section 5 interrupt controller rev. 6.00 feb 22, 2005 page 136 of 1484 rej09b0103-0600
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 137 of 1484 rej09b0103-0600 section 6 pc break controller (pbc) note: the h8s/2635 group is not equipped with a pbc. 6.1 overview the pc break controller (pbc) provides functions that simplify program debugging. using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. four break conditions can be set in the pbc: instruction fetch, data read, data write, and data read/write. 6.1.1 features the pc break controller has the following features: ? two break channels (a and b) ? the following can be set as break compare conditions: ? 24 address bits bit masking possible ? bus cycle instruction fetch data access: data read, data write, data read/write ? bus master either cpu or cpu/dtc can be selected ? the timing of pc break exception handling after the occurrence of a break condition is as follows: ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) ? module stop mode can be set ? the initial setting is for pbc operation to be halted. register access is enabled by clearing module stop mode.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 138 of 1484 rej09b0103-0600 6.1.2 block diagram figure 6-1 shows a block diagram of the pc break controller. output control mask control output control match signal pc break interrupt match signal mask control bara bcra barb bcrb comparator control logic comparator control logic internal address access status figure 6-1 block diagram of pc break controller
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 139 of 1484 rej09b0103-0600 6.1.3 register configuration table 6-1 shows the pc break controller registers. table 6-1 pc break controller registers initial value name abbreviation r/w reset address * 1 break address register a bara r/w h'xx000000 h'fe00 break address register b barb r/w h'xx000000 h'fe04 break control register a bcra r/(w) * 2 h'00 h'fe08 break control register b bcrb r/(w) * 2 h'00 h'fe09 module stop control register c mstpcrc r/w h'ff h'fdea notes: 1. lower 16 bits of the address. 2. only a 0 may be written to this bit to clear the flag. 6.2 register descriptions 6.2.1 break address register a (bara) bit initial value read/write ? ? 31 unde- fined ? ? 24 unde- fined r/w baa 23 23 0 r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/w 0 baa 0 0 . . . . . . . . . . . . . . . . . . . . . . . . bara is a 32-bit readable/writable register that specifies the channel a break address. baa23 to baa0 are initialized to h'000000 by a reset and in hardware standby mode. bits 31 to 24?reserved: these bits return an undefined value if read, and cannot be modified. bits 23 to 0?break address a23 to a0 (baa23 to baa0): these bits hold the channel a pc break address.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 140 of 1484 rej09b0103-0600 6.2.2 break address register b (barb) barb is the channel b break address register. the bit configuration is the same as for bara. 6.2.3 break control register a (bcra) bit initial value read/write note: * only a 0 may be written to this bit to clear the flag. r/(w) * 0 cmfa 7 r/w 0 cda 6 r/w 0 bamra2 5 r/w 0 bamra1 4 r/w 0 bamra0 3 r/w 0 csela1 2 r/w 0 csela0 1 r/w 0 biea 0 bcra is an 8-bit readable/writable register that controls channel a pc breaks. bcra (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. it also contains a condition match flag. bcra is initialized to h'00 by a reset and in hardware standby mode. bit 7?condition match flag a (cmfa): set to 1 when a break condition set for channel a is satisfied. this flag is not cleared to 0. bit 7 cmfa description 0 [clearing condition] ? when 0 is written to cmfa after reading cmfa = 1 (initial value) 1 [setting condition] ? when a condition set for channel a is satisfied
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 141 of 1484 rej09b0103-0600 bit 6?cpu cycle/dtc cycle select a (cda): selects the channel a break condition bus master. bit 6 cda description 0 pc break is performed when cpu is bus master (initial value) 1 pc break is performed when cpu or dtc is bus master bits 5 to 3?break address mask register a2 to a0 (bamra2 to bamra0): these bits specify which bits of the break address (baa23 to baa0) set in bara are to be masked. bit 5 bit 4 bit 3 bamra2 bamra1 bamra0 description 000all bara bits are unmasked and included in break conditions (initial value) 1 baa0 (lowest bit) is masked, and not included in break conditions 1 0 baa1, baa0 (lower 2 bits) are masked, and not included in break conditions 1 baa2 to baa0 (lower 3 bits) are masked, and not included in break conditions 1 0 0 baa3 to baa0 (lower 4 bits) are masked, and not included in break conditions 1 baa7 to baa0 (lower 8 bits) are masked, and not included in break conditions 10 baa11 to baa0 (lower 12 bits) are masked, and not included in break conditions 1 baa15 to baa0 (lower 16 bits) are masked, and not included in break conditions
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 142 of 1484 rej09b0103-0600 bits 2 and 1?break condition select a (csela1, csela0): these bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel a break condition. bit 2 bit 1 csela1 csela0 description 0 0 instruction fetch is used as break condition (initial value) 1 data read cycle is used as break condition 1 0 data write cycle is used as break condition 1 data read/write cycle is used as break condition bit 0?break interrupt enable a (biea): enables or disables channel a pc break interrupts. bit 0 biea description 0 pc break interrupts are disabled (initial value) 1 pc break interrupts are enabled 6.2.4 break control register b (bcrb) bcrb is the channel b break control register. the bit configuration is the same as for bcra. 6.2.5 module stop control register c (mstpcrc) 7 mstpc7 1 r/w bit initial value read/write 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w 0 mstpc0 1 r/w mstpcrc is an 8-bit readable/writable register that performs module stop mode control. when the mstpc4 bit is set to 1, pc break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. register read/write accesses are not possible in module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcrc is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 143 of 1484 rej09b0103-0600 bit 4?module stop (mstpc4): specifies the pc break controller module stop mode. bit 4 mstpc4 description 0 pc break controller module stop mode is cleared 1 pc break controller module stop mode is set (initial value) 6.3 operation the operation flow from break condition setting to pc break interrupt exception handling is shown in section 6.3.1, pc break interrupt due to instruction fetch, and 6.3.2, pc break interrupt due to data access, taking the example of channel a. 6.3.1 pc break interrupt due to instruction fetch (1) initial settings ? set the break address in bara. for a pc break caused by an instruction fetch, set the address of the first instruction byte as the break address. ? set the break conditions in bcra. bcra bit 6 (cda): with a pc break caused by an instruction fetch, the bus master must be the cpu. set 0 to select the cpu. bcra bits 5 to 3 (bama2 to bama0): set the address bits to be masked. bcra bits 2, 1 (csela1, csela0): set 00 to specify an instruction fetch as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts. (2) satisfaction of break condition ? when the instruction at the set address is fetched, a pc break request is generated immediately before execution of the fetched instructi on, and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 144 of 1484 rej09b0103-0600 6.3.2 pc break interrupt due to data access (1) initial settings ? set the break address in bara. for a pc break caused by a data access, set the target rom, ram, i/o, or external address space address as the break address. stack operations and branch address reads are included in data accesses. ? set the break conditions in bcra. bcra bit 6 (cda): select the bus master. bcra bits 5 to 3 (bama2 to bama0): set the address bits to be masked. bcra bits 2, 1 (csela1, csela0): set 01, 10, or 11 to specify data access as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts. (2) satisfaction of break condition ? after execution of the instruction that performs a data access on the set address, a pc break request is generated and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.3 notes on pc break interrupt handling (1) the pc break interrupt is shared by channels a and b. the channel from which the request was issued must be determined by the interrupt handler. (2) the cmfa and cmfb flags are not cleared to 0, so 0 must be written to cmfa or cmfb after first reading the flag while it is set to 1. if the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) a pc break interrupt generated when the dtc is the bus master is accepted after the bus has been transferred to the cpu by the bus controller.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 145 of 1484 rej09b0103-0600 6.3.4 operation in transitions to power-down modes the operation when a pc break interrupt is set for an instruction fetch at the address after a sleep instruction is shown below. (1) when the sleep instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode * to subsleep mode * : after execution of the sleep instruction, a transition is not made to sleep mode or subsleep mode * , and pc break interrupt handling is executed. after execution of pc break interrupt handling, the instruction at the address after the sleep instruction is executed (figure 6-2 (a)). (2) when the sleep instruction causes a transition from high-speed (medium-speed) mode to subactive mode * : after execution of the sleep instruction, a transition is made to subactive mode * via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6-2 (b)). (3) when the sleep instruction causes a transition from subactive mode * to high-speed (medium-speed) mode: after execution of the sleep instruction, and following the clock osc illation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6-2 (c)). (4) when the sleep instruction causes a transition to software standby mode or watch mode * : after execution of the sleep instruction, a transition is made to the respective mode, and pc break interrupt handling is not executed. however, the cmfa or cmfb flag is set (figure 6-2 (d)). note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 146 of 1484 rej09b0103-0600 sleep instruction execution high-speed (medium-speed) mode sleep instruction execution subactive * mode system clock subclock * direct transition * exception handling pc break exception handling execution of instruction after sleep instruction subclock * system clock, oscillation settling time sleep instruction execution transition to respective mode direct transition * exception handling pc break exception handling execution of instruction after sleep instruction pc break exception handling execution of instruction after sleep instruction note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. (a) (b) (c) (d) sleep instruction execution figure 6-2 operation in power-down mode transitions 6.3.5 pc break operation in continuous data transfer if a pc break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) when a pc break interrupt is generated at the transfer address of an eepmov.b instruction: pc break exception handling is executed after all data transfers have been completed and the eepmov.b instruction has ended. (2) when a pc break interrupt is generated at a dtc transfer address:31 pc break exception handling is executed after the dtc has completed the specified number of data transfers, or after data for which the disel bit is set to 1 has been transferred.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 147 of 1484 rej09b0103-0600 6.3.6 when instruction execution is delayed by one state caution is required in the following cases, as instruction execution is one state later than usual. (1) when the pbc is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (bcc d:8, bsr, jsr, jmp, trapa, rte, or rts) located in on- chip rom or ram is always delayed by one state. (2) when break interruption by instruction fetch is set, the set address indicates on-chip rom or ram space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip rom or ram, and that address is used for data access, the instruction will be one state later than in normal operation. @ern, @(d:16,ern), @(d:32,ern), @-ern/ern+, @aa:8, @aa:24, @aa:32, @(d:8,pc), @(d:16,pc), @@aa:8 (4) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is nop or sleep, or has #xx,rn as its addressing mode, and that instruction is located in on-chip rom or ram, the instruction will be one state later than in normal operation.
section 6 pc break controller (pbc) rev. 6.00 feb 22, 2005 page 148 of 1484 rej09b0103-0600 6.3.7 additional notes (1) when a pc break is set for an instruction fetch at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction: even if the instruction at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction is fetched, it is not executed, and so a pc break interrupt is not generated by the instruction fetch at the next address. (2) when the i bit is set by an ldc, andc, orc, or xorc instruction, a pc break interrupt becomes valid two states after the end of the executing instruction. if a pc break interrupt is set for the instruction following one of these instructions, since interrupts, including nmi, are disabled for a 3-state period in the case of ldc, andc, orc, and xorc, the next instruction is always executed. for details, see section 5, interrupt controller. (3) when a pc break is set for an instruction fetch at the address following a bcc instruction: a pc break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) when a pc break is set for an instruction fetch at the branch destination address of a bcc instruction: a pc break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed.
section 7 bus controller rev. 6.00 feb 22, 2005 page 149 of 1484 rej09b0103-0600 section 7 bus controller 7.1 overview the chip has an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu, and data transfer controller (dtc). note: the dtc is not implemented in the h8s/2635 group. 7.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as 8 areas of 2-mbytes ? bus specifications can be set independently for each area ? burst rom interface can be set ? basic bus interface ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? write buffer functions ? external write cycle and internal access can be executed in parallel ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu and dtc
section 7 bus controller rev. 6.00 feb 22, 2005 page 150 of 1484 rej09b0103-0600 ? other features ? external bus release function 7.1.2 block diagram figure 7-1 shows a block diagram of the bus controller. area decoder bus controller abwcr astcr bcrh bcrl internal address bus external bus control signals legend: a bwcr: bus width control register a stcr: access state control register bcrh: bus control register h bcrl: bus control register l wcrh: wait control register h wcrl: wait control register l internal control signals wait controller wcrh wcrl bus mode signal bus arbiter cpu bus request signal dtc bus request signal cpu bus acknowledge signal dtc bus acknowledge signal internal data bus figure 7-1 block diagram of bus controller
section 7 bus controller rev. 6.00 feb 22, 2005 page 151 of 1484 rej09b0103-0600 7.1.3 pin configuration table 7-1 summarizes the pins of the bus controller. table 7-1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write hwr output strobe signal indicating that external space is to be written, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d7 to d0) of data bus is enabled. 7.1.4 register configuration table 7-2 summarizes the registers of the bus controller. table 7-2 bus controller registers name abbreviation r/w initial value address * 1 bus width control register abwcr r/w h'ff/h'00 * 2 h'fed0 access state control register astcr r/w h'ff h'fed1 wait control register h wcrh r/w h'ff h'fed2 wait control register l wcrl r/w h'ff h'fed3 bus control register h bcrh r/w h'd0 h'fed4 bus control register l bcrl r/w h'08 h'fed5 pin function control register pfcr r/w h'0d/h'00 h'fdeb notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode.
section 7 bus controller rev. 6.00 feb 22, 2005 page 152 of 1484 rej09b0103-0600 7.2 register descriptions 7.2.1 bus width control register (abwcr) 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : rw initial value : : rw abwcr is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. after a reset and in hardware standby mode, abwcr is initialized to h'ff in modes 5, 6, 7, and to h'00 in mode 4. it is not initialized in software standby mode. bits 7 to 0?area 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0)
section 7 bus controller rev. 6.00 feb 22, 2005 page 153 of 1484 rej09b0103-0600 7.2.2 access state control register (astcr) 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : astcr is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. astcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space is disabled 1 area n is designated for 3-state access (initial value ) wait state insertion in area n external space is enabled (n = 7 to 0)
section 7 bus controller rev. 6.00 feb 22, 2005 page 154 of 1484 rej09b0103-0600 7.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in the case of on-chip memory or internal i/o registers. wcrh and wcrl are initialized to h'ff by a reset and in hardware standby mode. they are not initialized in software standby mode. wcrh 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : bits 7 and 6?area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 bit 6 w71 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value )
section 7 bus controller rev. 6.00 feb 22, 2005 page 155 of 1484 rej09b0103-0600 bits 5 and 4?area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 bit 4 w61 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value ) bits 3 and 2?area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 bit 2 w51 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value ) bits 1 and 0?area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 bit 0 w41 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value )
section 7 bus controller rev. 6.00 feb 22, 2005 page 156 of 1484 rej09b0103-0600 wcrl 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : bits 7 and 6?area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 bit 6 w31 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value ) bits 5 and 4?area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 bit 4 w21 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value )
section 7 bus controller rev. 6.00 feb 22, 2005 page 157 of 1484 rej09b0103-0600 bits 3 and 2?area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 bit 2 w11 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value ) bits 1 and 0?area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 bit 0 w01 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value )
section 7 bus controller rev. 6.00 feb 22, 2005 page 158 of 1484 rej09b0103-0600 7.2.4 bus control register h (bcrh) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w bit initial value r/w : : : bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 2 to 5, and 0. bcrh is initialized to h'd0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?idle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas 1 idle cycle inserted in case of successive external read cycles in different areas (initial value ) bit 6?idle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value )
section 7 bus controller rev. 6.00 feb 22, 2005 page 159 of 1484 rej09b0103-0600 bit 5?burst rom enable (brstrm): selects whether area 0 is used as a burst rom interface. bit 5 brstrm description 0 area 0 is basic bus interface (initial value ) 1 area 0 is burst rom interface bit 4?burst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value ) bit 3?burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value ) 1 max. 8 words in burst access bits 2 to 0?reserved: only 0 should be written to these bits.
section 7 bus controller rev. 6.00 feb 22, 2005 page 160 of 1484 rej09b0103-0600 7.2.5 bus control register l (bcrl) 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 ? 4 ? 0 r/w 3 ? 1 r/w 0 ? 0 r/w 2 ? 0 r/w 1 wdbe 0 r/w bit initial value r/w : : : bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function. bcrl is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?reserved: only 0 should be written to these bits. bit 5?reserved: it is always read as 0. cannot be written to. bit 4?reserved: only 0 should be written to this bit. bit 3?reserved: only 1 should be written to this bit. bit 2?reserved: only 0 should be written to this bit. bit 1?write data buffer enable (wdbe): this bit selects whether or not to use the write buffer function in the external write cycle. bit 1 wdbe description 0 write data buffer function not used (initial value) 1 write data buffer function used bit 0?reserved: only 0 should be written to these bits.
section 7 bus controller rev. 6.00 feb 22, 2005 page 161 of 1484 rej09b0103-0600 7.2.6 pin function control register (pfcr) 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w bit initial value r/w : : : pfcr is an 8-bit read/write register that controls the address output in on-chip rom-enabled expansion mode. pfcr is initialized to h'0d/h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. bits 7 to 4?reserved: only 0 should be written to these bits. bits 3 to 0?address output enable 3 to 0 (ae3 to ae0): these bits select enabling or disabling of address outputs a8 to a23 in on-chip rom-disabled expansion mode and on-chip rom-enabled expansion mode. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1.
section 7 bus controller rev. 6.00 feb 22, 2005 page 162 of 1484 rej09b0103-0600 bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0 0 0 0 a8 to a23 address output disabled (initial value * ) 1 a8 address output enabled; a9 to a23 address output disabled 1 0 a8, a9 address output enabled; a10 to a23 address output disabled 1 a8 to a10 address output enabled; a11 to a23 address output disabled 1 0 0 a8 to a11 address output enabled; a12 to a23 address output disabled 1 a8 to a12 address output enabled; a13 to a23 address output disabled 10 a8 to a13 address output enabled; a14 to a23 address output disabled 1 a8 to a14 address output enabled; a15 to a23 address output disabled 1 0 0 0 a8 to a15 address output enabled; a16 to a23 address output disabled 1 a8 to a16 address output enabled; a17 to a23 address output disabled 1 0 a8 to a17 address output enabled; a18 to a23 address output disabled 1 a8 to a18 address output enabled; a19 to a23 address output disabled 100 a8 to a19 address output enabled; a20 to a23 address output disabled 1 a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * ) 1 0 a8 to a21 address output enabled; a22, a23 address output disabled 1 a8 to a23 address output enabled note: * in on-chip rom-enabled expansion mode, bits ae3 to ae0 are initialized to b'0000. in on-chip rom-disabled expansion mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1.
section 7 bus controller rev. 6.00 feb 22, 2005 page 163 of 1484 rej09b0103-0600 7.3 overview of bus control 7.3.1 area partitioning in advanced mode, the bus controller partitions the 16 mbytes address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. in normal mode * , it controls a 64-kbyte address space comprising part of area 0. figure 7-2 shows an outline of the memory map. note: * not available in the chip. area 0 (2 mbytes) h'000000 h'ffffff (1) (2) h'0000 h'1fffff h'200000 area 1 (2 mbytes) h'3fffff h'400000 area 2 (2 mbytes) h'5fffff h'600000 area 3 (2 mbytes) h'7fffff h'800000 area 4 (2 mbytes) h'9fffff h'a00000 area 5 (2 mbytes) h'bfffff h'c00000 area 6 (2 mbytes) h'dfffff h'e00000 area 7 (2 mbytes) h'ffff advanced mode normal mode * note: * not available in the chip. figure 7-2 overview of area partitioning
section 7 bus controller rev. 6.00 feb 22, 2005 page 164 of 1484 rej09b0103-0600 7.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with adwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. when the burst rom interface is designated, 16-bit bus mode is always set. number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. with the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 7-3 shows the bus specifications for each basic bus interface area.
section 7 bus controller rev. 6.00 feb 22, 2005 page 165 of 1484 rej09b0103-0600 table 7-3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 00??16 2 0 100 3 0 11 10 2 13 10??8 2 0 100 3 0 11 10 2 13 7.3.3 memory interfaces the chip's memory interfaces comprise a basic bus interface that allows direct connection or rom, sram, and so on, and a burst rom interface that allows direct connection of burst rom. the memory interface can be selected independently for each area. an area for which the basic bus interface is designated functions as normal space, and an area for which the burst rom interface is designated functions as burst rom space.
section 7 bus controller rev. 6.00 feb 22, 2005 page 166 of 1484 rej09b0103-0600 7.3.4 interface specifications for each area the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (7.4, basic bus interface, and 7.5, burst rom interface) should be referred to for further details. area 0: area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. either basic bus interface or burst rom interface can be selected for area 0. areas 1 to 6: in external expansion mode, all of areas 1 to 6 is external space. only the basic bus interface can be used for areas 1 to 6. area 7: area 7 includes the on-chip ram and internal i/o registers. in external expansion mode, the space excluding the on-chip ram and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. only the basic bus interface can be used for the area 7.
section 7 bus controller rev. 6.00 feb 22, 2005 page 167 of 1484 rej09b0103-0600 7.4 basic bus interface 7.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 7-3). 7.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 7-3 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. d15 d8 d7d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 7-3 access sizes and data alignment control (8-bit access space)
section 7 bus controller rev. 6.00 feb 22, 2005 page 168 of 1484 rej09b0103-0600 16-bit access space: figure 7-4 illustrates data alignment control for the 16-bit access sp ace. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7d0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size even address byte size odd address lower data bus figure 7-4 access sizes and data alignment control (16-bit access space)
section 7 bus controller rev. 6.00 feb 22, 2005 page 169 of 1484 rej09b0103-0600 7.4.3 valid strobes table 7-4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid without discr imination between the upper and lower halves of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 7-4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) byte read ? rd valid invalid 8-bit access space write ? hwr hi-z byte read even rd valid invalid 16-bit access space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read ? rd valid valid write ? hwr , lwr valid valid note: hi-z: high impedance. invalid: input state; input value is ignored.
section 7 bus controller rev. 6.00 feb 22, 2005 page 170 of 1484 rej09b0103-0600 7.4.4 basic timing 8-bit 2-state access space: figure 7-5 shows the bus timing for an 8-bit 2-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states cannot be inserted. bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high figure 7-5 bus timing for 8-bit 2-state access space
section 7 bus controller rev. 6.00 feb 22, 2005 page 171 of 1484 rej09b0103-0600 8-bit 3-state access space: figure 7-6 shows the bus timing for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states can be inserted. bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high t 3 figure 7-6 bus timing for 8-bit 3-state access space
section 7 bus controller rev. 6.00 feb 22, 2005 page 172 of 1484 rej09b0103-0600 16-bit 2-state access space: figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states cannot be inserted. bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high figure 7-7 bus timing for 16-bit 2-state access space (1) (even address byte access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 173 of 1484 rej09b0103-0600 bus cycle t 1 t 2 address bus f as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 high impedance d7 to d0 valid write high figure 7-8 bus timing for 16-bit 2-state access space (2) (odd address byte access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 174 of 1484 rej09b0103-0600 bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write figure 7-9 bus timing for 16-bit 2-state access space (3) (word access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 175 of 1484 rej09b0103-0600 16-bit 3-state access space: figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. when a 16-bit access space is accessed , the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states can be inserted. bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high t 3 figure 7-10 bus timing for 16-bit 3-state access space (1) (even address byte access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 176 of 1484 rej09b0103-0600 bus cycle t 1 t 2 address bus f as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 high impedance d7 to d0 valid write high t 3 figure 7-11 bus timing for 16-bit 3-state access space (2) (odd address byte access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 177 of 1484 rej09b0103-0600 bus cycle t 1 t 2 address bus f as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 t 3 figure 7-12 bus timing for 16-bit 3-state access space (3) (word access)
section 7 bus controller rev. 6.00 feb 22, 2005 page 178 of 1484 rej09b0103-0600 7.4.5 wait control when accessing external space, the chip can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: program wait insertion. program wait insertion from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings of wcrh and wcrl. figure 7-13 shows an example of wait state insertion timing. by program wait t 1 address bus f as rd data bus read data read hwr , lwr write data write data bus t 2 t w t w t w t 3 figure 7-13 example of wait state insertion timing the settings after a reset are: 3-state access, 3 program wait state insertion.
section 7 bus controller rev. 6.00 feb 22, 2005 page 179 of 1484 rej09b0103-0600 7.5 burst rom interface 7.5.1 overview in this lsi, the area 0 external space can be set as burst rom space and burst rom interfacing performed. burst rom space interfacing allows 16-bit rom capable of burst access to be accessed at high-speed. the brstrm bit of bcrh sets area 0 as burst rom space. cpu instruction fetches (only) can be performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can be selected in the case of burst access. 7.5.2 basic timing the ast0 bit of astcr sets the number of access states in the initial cycle (full access) of the burst rom interface. wait states can be inserted when the ast0 bit is set to 1. the burst cycle can be set for 1 state or 2 sttes by setting the brsts1 bit of bcrh. wait states cannot be inserted. when area 0 is set as burst rom space, area 0 is a 16-bit access space regardless of the abw0 bit of abwcr. when the brsts0 bit of bcrh is cleared to 0, 4-word max. burst access is performed. when the brsts0 bit is set to 1, 8-word max. burst access is performed. figures 7-14 (a) and (b) show the basic access timing for the burst rom space. figure 7-14 (a) is an example when both the ast0 and brsts1 bits are set to 1. figure 7-14 (b) is an example when both the ast0 and brsts1 bits are set to 0.
section 7 bus controller rev. 6.00 feb 22, 2005 page 180 of 1484 rej09b0103-0600 t 1 address bus f as data bus t 2 t 3 t 1 t 2 t 1 full access t 2 rd burst access low address only changes read data read data read data figure 7-14 (a) example burst rom access timing (ast0 = brsts1 = 1) t 1 address bus f as data bus t 2 t 1 t 1 full access rd burst access low address only changes read data read data read data figure 7-14 (b) example burst rom access timing (ast0 = brsts1 = 0)
section 7 bus controller rev. 6.00 feb 22, 2005 page 181 of 1484 rej09b0103-0600 7.5.3 wait control as with the basic bus interface, program waits can be inserted in the burst rom interface initial cycle (full access). see section 7.4.5, wait control. wait states cannot be inserted in the burst cycle. 7.6 idle cycle 7.6.1 operation when the chip accesses external space, it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on.
section 7 bus controller rev. 6.00 feb 22, 2005 page 182 of 1484 rej09b0103-0600 (1) consecutive reads between different areas if consecutive reads between different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. figure 7-15 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a co llision occurs in cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus f rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b bus cycle a bus cycle b long output floating time note: * the cs signal is generated externally rather than inside the lsi device. data collision (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) t 1 address bus f rd data bus t 2 t 3 t i t 1 t 2 cs * (area a) cs * (area b) cs * (area a) cs * (area b) figure 7-15 example of idle cycle operation (1)
section 7 bus controller rev. 6.00 feb 22, 2005 page 183 of 1484 rej09b0103-0600 (2) write after read if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 7-16 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus note: * the cs signal is generated externally rather than inside the lsi device. f rd bus cycle a t 2 t 3 t 1 t 2 bus cycle b possibility of overlap between cs (area b) and rd t 1 address bus f bus cycle a t 2 t 3 t i t 1 bus cycle b t 2 cs * (area a) cs * (area b) rd cs * (area a) cs * (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 7-16 example of idle cycle operation (2)
section 7 bus controller rev. 6.00 feb 22, 2005 page 184 of 1484 rej09b0103-0600 (3) relationship between chip select ( cs * ) signal and read ( rd ) signal depending on the system?s load conditions, the rd signal may lag behind the cs signal * . an example is shown in figure 7-17. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. note: * the cs signal is generated externally rather than inside the lsi device. t 1 address bus f rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision t 1 address bus f rd bus cycle a data bus t 2 t 3 t i t 1 bus cycle b t 2 hwr hwr cs * (area a) cs * (area b) cs * (area a) cs * (area b) (a) idle cycle not inserted (icis0 = 0) (b) idle cycle inserted (initial value icis0 = 1) note: * the cs signal is generated externally rather than inside the lsi device. figure 7-17 relationship between chip select ( cs ) * and read ( rd )
section 7 bus controller rev. 6.00 feb 22, 2005 page 185 of 1484 rej09b0103-0600 7.6.2 pin states during idle cycles table 7-5 shows the pin states during idle cycles. table 7-5 pin states during idle cycles pins pin state a23 to a0 content identical to immediately following bus cycle d15 to d0 high impedance as high level rd high level hwr high level lwr high level
section 7 bus controller rev. 6.00 feb 22, 2005 page 186 of 1484 rej09b0103-0600 7.7 write data buffer function the chip has a write data buffer function in the external data bus. using this function enables the write data buffer to be accessed in parallel. the write data buffer function is made available by setting the wdbe bit in bcrl to 1. figure 7-18 shows an example of the timing when the write data buffer function is used. when this function is used, if an external write continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal i/o register read/write) is executed in parallel with the external write rather than waiting until it ends. t 1 internal address bus f a23 to a0 external write cycle hwr , lwr t 2 t w t w t 3 on-chip memory read internal i/o register read internal read signal d15 to d0 external address internal memory external space write internal i/o register address figure 7-18 example of timing when write data buffer function is used
section 7 bus controller rev. 6.00 feb 22, 2005 page 187 of 1484 rej09b0103-0600 7.8 bus arbitration note: the h8s/2635 group is not equipped with a dtc. 7.8.1 overview the chip has a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu and dtc which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 7.8.2 operation the bus arbiter detects the bus masters? bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) 7.8.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a.5, bus states during instruction execution, for t imings at which the bus is not transferred. ? if the cpu is in sleep mode, it transfers the bus immediately.
section 7 bus controller rev. 6.00 feb 22, 2005 page 188 of 1484 rej09b0103-0600 dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.9 resets and the bus controller in a reset, the chip, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 189 of 1484 rej09b0103-0600 section 8 data transfer controller (dtc) note: the h8s/2635 group is not equipped with a dtc. 8.1 overview the chip includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 8.1.1 features ? transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) ? wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected ? direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after the specified data transfers have completely ended ? activation by software is possible ? module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 190 of 1484 rej09b0103-0600 8.1.2 block diagram figure 8-1 shows a block diagram of the dtc. the dtc?s register information is stored in the on-chip ram * . a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc service request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend: mra, mrb: cra, crb: sar: dar: dtcera to dtcerg: dtvecr: dtcera to dtcerg dtvecr dtc mode registers a and b dtc transfer count registers a and b dtc source address register dtc destination address register dtc enable registers a to g dtc vector register figure 8-1 block diagram of dtc
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 191 of 1484 rej09b0103-0600 8.1.3 register configuration table 8-1 summarizes the dtc registers. table 8-1 dtc registers name abbreviation r/w initial value address * 1 dtc mode register a mra ? * 2 undefined ? * 3 dtc mode register b mrb ? * 2 undefined ? * 3 dtc source address register sar ? * 2 undefined ? * 3 dtc destination address register dar ? * 2 undefined ? * 3 dtc transfer count register a cra ? * 2 undefined ? * 3 dtc transfer count register b crb ? * 2 undefined ? * 3 dtc enable registers dtcer r/w h'00 h'fe16 to h'fe1c dtc vector register dtvecr r/w h'00 h'fe1f module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. registers within the dtc cannot be read or written to directly. 3. register information is located in on-chip ram addresses h'ebc0 to h'efbf. it cannot be located in external memory space. when the dtc is used, do not clear the rame bit in syscr to 0.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 192 of 1484 rej09b0103-0600 8.2 register descriptions 8.2.1 dtc mode register a (mra) 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : ? * r/w : ? * ? * ? * ? * ? * ? * ? * : undefined * mra is an 8-bit register that controls the dtc operating mode. bits 7 and 6?source address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0 description 0 ? sar is fixed 1 0 sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 sar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1) bits 5 and 4?destination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0 description 0 ? dar is fixed 1 0 dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 dar is decremented after a transfer (by ?1 when sz = 0; by ?2 when sz = 1)
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 193 of 1484 rej09b0103-0600 bits 3 and 2?dtc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0 description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1? bit 1?dtc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0?dtc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 194 of 1484 rej09b0103-0600 8.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit initial value : : r/w : ? * ? * ? * ? * ? * ? * ? * ? * : undefined * mrb is an 8-bit register that controls the dtc operating mode. bit 7?dtc chain transfer enable (chne): specifies chain transfer. with chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer is not performed. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6?dtc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0?reserved: these bits have no effect on dtc operation in the chip, and should always be written with 0.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 195 of 1484 rej09b0103-0600 8.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value : : ? * r/w : ? * ? * ? * ? * ? * ? * ? * ? * ? * * : undefined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 8.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value : : ? r/w : ???? ????? ***** ***** * : undefined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 8.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value : : ? * r/w : ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * ? * * : undefined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 196 of 1484 rej09b0103-0600 in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. 8.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value : : ? ? ? ? ?? ? ? ?? ? ? ?? ? ? r/w : **************** * : undefined crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 8.2.7 dtc enable registers (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : the dtc enable registers comprise seven 8-bit readable/writable registers, dtcera to dtcerg with bits corresponding to the interrupt sources that can control enabling and disabling of dtc activation. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable registers are initialized to h'00 by a reset and in hardware standby mode.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 197 of 1484 rej09b0103-0600 bit n?dtc activation enable (dtcen) bit n dtcen description 0 dtc activation by this interrupt is disabled (initial value ) [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended 1 dtc activation by this interrupt is enabled [holding condition] ? when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 8-4, together with the vector number generated for each interrupt controller. for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 notes: 1. only 1 can be written to the swdte bit. 2. bits dtvec6 to dtvec0 can be written to when swdte = 0. bit initial value r/w : : : dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 198 of 1484 rej09b0103-0600 bit 7?dtc software activation enable (swdte): enables or disables dtc activation by software. bit 7 swdte description 0 dtc software activation is disabled (initial value ) [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 is written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu 1 dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation bits 6 to 0?dtc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 199 of 1484 rej09b0103-0600 8.2.9 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value read/write 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is a 8-bit readable/writable register that performs module stop mode control. when the mstpa6 bit in mstpcra is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. for details, see section 23a.5, 23b.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 6?module stop (mstpa6): specifies the dtc module stop mode. bit 6 mstpa6 description 0 dtc module stop mode cleared (initial value ) 1 dtc module stop mode set
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 200 of 1484 rej09b0103-0600 8.3 operation 8.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 8-2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear an activation flag chne =1 end no no yes yes transfer counter= 0 or disel = 1 clear dtcer interrupt exception handling figure 8-2 flowchart of dtc operation
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 201 of 1484 rej09b0103-0600 the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 8-2 outlines the functions of the dtc. table 8-2 dtc functions address registers transfer mode activation source transfer source transfer destination ? normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible ? repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues ? block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination ? irq ? tpu tgi ? sci txi or rxi ? a/d converter adi ? motor control pwm cmi ? hcan rm0 (mail box 0) ? software 24 bits 24 bits
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 202 of 1484 rej09b0103-0600 8.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. an interrupt becomes a dtc activation source when the corresponding bit is set to 1, and a cpu interrupt source when the bit is cleared to 0. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding dtcer bit is cleared. table 8-3 shows activation source and dtcer clearance. the activation source flag, in the case of rxi0, for example, is the rdrf flag of sci0. table 8-3 activation source and dtcer clearance activation source when the disel bit is 0 and the specified number of transfers have not ended when the disel bit is 1, or when the specified number of transfers have ended software activation the swdte bit is cleared to 0 the swdte bit remains set to 1 an interrupt is issued to the cpu interrupt activation the corresponding dtcer bit remains set to 1 the activation source flag is cleared to 0 the corresponding dtcer bit is cleared to 0 the activation source flag remains set to 1 a request is issued to the cpu for the activation source interrupt
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 203 of 1484 rej09b0103-0600 figure 8-3 shows a block diagram of activation source control. for details see section 5, interrupt controller. on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear controller select interrupt request source flag cleared clear clear request interrupt mask figure 8-3 block diagram of dtc activation source control when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 204 of 1484 rej09b0103-0600 8.3.3 dtc vector table figure 8-4 shows the correspondence between dtc vector addresses and register information. table 8-4 shows the correspondence between activation and vector addresses. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] << 1) (where << 1 indicates a 1-bit left shift). for example, if dtvecr is h'10, the vector address is h'0420. the dtc reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. the register information can be placed at predetermined addresses in the on-chip ram. the start address of the register information should be an integral multiple of four. the configuration of the vector address is the same in both normal * and advanced modes, a 2-byte unit being used in both cases. these two bytes specify the lower bits of the address in the on-chip ram. note: * not available in the chip. register information start address register information chain transfer dtc vector address figure 8-4 correspondence between dtc vector address and register information
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 205 of 1484 rej09b0103-0600 table 8-4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * 1 priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0] <<1) ?high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 reserved ? 22 to 27 h'042c to h'0436 ? adi (a/d conversion end) a/d 28 h'0438 dtceb6 reserved ? 29 to 31 h'043a to h'043e ? tgi0a (gr0a compare match/ input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/ input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/ input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/ input capture) 35 h'0446 dtceb2 reserved ? 36 to 39 h'0448 to h'044e ? tgi1a (gr1a compare match/ input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/ input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/ input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/ input capture) 45 h'045a dtcec6 low
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 206 of 1484 rej09b0103-0600 interrupt source origin of interrupt source vector number vector address dtce * 1 priority tgi3a (gr3a compare match/ input capture) tpu channel 3 48 h'0460 dtcec5 high tgi3b (gr3b compare match/ input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare match/ input capture) 50 h'0464 dtcec3 tgi3d (gr3d compare match/ input capture) 51 h'0466 dtcec2 reserved ? 52 to 55 h'0468 to h'046e ? tgi4a (gr4a compare match/ input capture) tpu channel 4 56 h'0470 dtcec1 tgi4b (gr4b compare match/ input capture) 57 h'0472 dtcec0 reserved ? 58, 59 h'0474 to h'0476 ? tgi5a (gr5a compare match/ input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare match/ input capture) 61 h'047a dtced4 reserved ? 62 to 80 h'047c to h'04a0 ? rxi0 (reception complete 0) 81 h'04a2 dtcee3 txi0 (transmit data empty 0) sci channel 0 82 h'04a4 dtcee2 reserved ? 83, 84 h'04a6 to h'04a8 ? rxi1 (reception complete 1) 85 h'04aa dtcee1 txi1 (transmit data empty 1) sci channel 1 86 h'04ac dtcee0 reserved ? 87, 88 h'04ae to h'04b0 ? rxi2 (reception complete 2) 89 h'04b2 dtcef7 txi2 (transmit data empty 2) sci channel 2 90 h'04b4 dtcef6 reserved ? 91 to 97 h'04b6 to h'04c2 ? low
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 207 of 1484 rej09b0103-0600 interrupt source origin of interrupt source vector number vector address dtce * 1 priority i 2 ci0 (1-byte transmission/ reception completed) * 2 i 2 c channel 0 (option) 100 h'04c8 dtcef1 high i 2 ci1 (1-byte transmission/ reception completed) * 2 i 2 c channel 1 (option) 102 h'04cc dtcef0 cmi1 (pwcyr1 compare match) pwm 104 h'04d0 dtceg7 cmi2 (pwcyr2 compare match) 105 h'04d2 dtceg6 reserved ? 106 h'04d4 ? rm0 (hcan1 mail box 0) hcan1 107 h'04d6 dtceg4 reserved ? 108 h'04d8 ? rm0 (hcan0 mail box 0) hcan0 109 h'04da dtceg2 reserved ? 110 to 124 h'04dc to h'04f8 ? low notes: 1. dtce bits with no corresponding interrupt are reserved, and should be written with 0. 2. i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. these bits become reserved bits when this optional feature is not used or in the h8s/2636.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 208 of 1484 rej09b0103-0600 8.3.4 location of register information in address space figure 8-5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (contents of the vector address). in the case of chain transfer, register information should be located in consecutive areas. locate the register information in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information start address chain transfer register information for 2nd transfer in chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0123 sar mrb dar figure 8-5 location of register information in address space
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 209 of 1484 rej09b0103-0600 8.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. table 8-5 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used transfer sar dar figure 8-6 memory mapping in normal mode
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 210 of 1484 rej09b0103-0600 8.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. table 8-6 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register b crb not used transfer sar or dar dar or sar repeat area figure 8-7 memory mapping in repeat mode
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 211 of 1484 rej09b0103-0600 8.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. table 8-7 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 212 of 1484 rej09b0103-0600 transfer sar or dar dar or sar block area 1st block nth block ? ? ? figure 8-8 memory mapping in block transfer mode
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 213 of 1484 rej09b0103-0600 8.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 8-9 shows the memory map for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 8-9 chain transfer memory map in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 214 of 1484 rej09b0103-0600 8.3.9 operation timing figures 8-10 to 8-12 show an example of dtc operation timing. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write f figure 8-10 dtc operation timing (example in normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read f dtc activation request dtc request address figure 8-11 dtc operation timing (example of block transfer mode, with block size of 2)
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 215 of 1484 rej09b0103-0600 read write read write address f dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 8-12 dtc operation timing (example of chain transfer) 8.3.10 number of dtc execution states table 8-8 lists execution statuses for a single dtc data transfer, and table 8-9 shows the number of states required for each execution status. table 8-8 dtc execution statuses mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral)
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 216 of 1484 rej09b0103-0600 table 8-9 number of states required for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 8 16 16 access states 1 1 2 2 2 3 2 3 vector read s i ?1 ??4 6 + 2m23 + m execution status register information read/write s j 1????? ?? byte data read s k 112223 + m23 + m word data read s k 114246 + 2m23 + m byte data write s l 112223 + m23 + m word data write s l 114246 + 2m23 + m internal operation s m 111111 11 the number of execution states is calculated from the formula below. note that means the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i (s i + 1) + (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 14 states. the time from activation to the end of the data write is 11 states.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 217 of 1484 rej09b0103-0600 8.3.11 procedures for using dtc activation by interrupt: the procedure for using the dtc with interrupt activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. [5] after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. activation by software: the procedure for using the dtc with software activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] check that the swdte bit is 0. [4] write 1 to swdte bit and the vector number to dtvecr. [5] check the vector number written to dtvecr. [6] after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 218 of 1484 rej09b0103-0600 8.3.12 examples of use of the dtc (1) normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. [1] set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be r eceived in dar, and 128 (h'0080) in cra. crb can be set to any value. [2] set the start address of the register information at the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu s hould be enabled to accept receive error interrupts. [5] each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. [6] when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 219 of 1484 rej09b0103-0600 (2) chain transfer an example of dtc chain transfer is shown in which pulse output is performed using the ppg. chain transfer can be used to perform pulse output data transfer and ppg output trigger cycle updating. repeat mode transfer to the ppg?s ndr is performed in the first half of the chain transfer, and normal mode transfer to the tpu?s tgr in the second half. this is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when chne = 0). [1] perform settings for transfer to the ppg?s ndr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), repeat mode (md1 = 0, md0 = 1), and word size (sz = 1). set the source side as a repeat area (dts = 1). set mrb to chain mode (chne = 1, disel = 0). set the data table start address in sar, the ndrh address in dar, and the data table size in crah and cral. crb can be set to any value. [2] perform settings for transfer to the tpu?s tgr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), normal mode (md1 = md0 = 0), and word size (sz = 1). set the data table start address in sar, the tgra address in dar, and the data table size in cra. crb can be set to any value. [3] locate the tpu transfer register information consecutively after the ndr transfer register information. [4] set the start address of the ndr transfer register information to the dtc vector address. [5] set the bit corresponding to tgia in dtcer to 1. [6] set tgra as an output compare register (output disabled) with tior, and enable the tgia interrupt with tier. [7] set the initial output value in podr, and the next output value in ndr. set bits in ddr and nder for which output is to be performed to 1. using pcr, select the tpu compare match to be used as the output trigger. [8] set the cst bit in tstr to 1, and start the tcnt count operation. [9] each time a tgra compare match occurs, the next output value is transferred to ndr and the set value of the next output trigger period is transferred to tgra. the activation source tgfa flag is cleared.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 220 of 1484 rej09b0103-0600 [10] when the specified number of transfers are completed (the tpu transfer cra value is 0), the tgfa flag is held at 1, the dtce bit is cleared to 0, and a tgia interrupt request is sent to the cpu. termination processing should be performed in the interrupt handling routine. (3) software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. [1] set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. [2] set the start address of the register information at the dtc vector address (h'04c0). [3] check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. [4] write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. [5] read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. [6] if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. [7] after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 221 of 1484 rej09b0103-0600 8.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 8.5 usage notes module stop: when the mstpa6 bit in mstpcra is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. on-chip ram: the mra, mrb, sar, dar, cra, and crb registers are all located in on-chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. dtce bit setting: for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.
section 8 data transfer controller (dtc) rev. 6.00 feb 22, 2005 page 222 of 1484 rej09b0103-0600
section 9 i/o ports rev. 6.00 feb 22, 2005 page 223 of 1484 rej09b0103-0600 section 9 i/o ports 9.1 overview the chip has 10 i/o ports (ports 1, 3 and a to f, h, j), and two input-only port (ports 4 and 9). table 9-1 summarizes the port functions. the pins of each port also have other functions. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. the input-only ports do not have a dr or ddr register. ports a to e have an on-chip pull-up mos function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off state of mos input pull-up. ports 3, and a to c include an open-drain control register (odr) that controls the on/off state of the output buffer pmos. when ports 10 to 13 and a to f are used as the output pins for expanded bus control signals, they can drive one ttl load plus a 90pf capacitance load. those ports in other cases and ports 14 to 17 and 3 can drive one ttl load and a 30pf capacitance load. all i/o ports can drive darlington transistors when set to output. port 1 pins (p16 and p14) and port 3 pins (p35 and p32) and port f (pf3 and pf0) are schmitt- trigger inputs. see appendix c, i/o port block diagrams, for a block diagram of each port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 224 of 1484 rej09b0103-0600 table 9-1 port functions port description pins mode 4 mode 5 mode 6 mode 7 port 1 * 2 ? 8-bit i/o port schmitt- triggered input (p16, p14) p17/po15/tiocb2/ tclkd p16/po14/tioca2/ irq1 p15/po13/tiocb1/ tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/ tclkb/a23 p12/po10/tiocc0/ tclka/a22 p11/po9/tiocb0/a21 p10/po8/tioca0/a20 8 bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), ppg output pins (po15 to po8), interrupt input pins ( irq0 , irq1 ), and address outputs (a20 to a23) 8-bit i/o port also function- ing as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), ppg output pins (po15 to po8), interrupt input pins ( irq0 , irq1 ) port 3 6-bit i/o port open-drain output capability schmitt- triggered input (p35, p32) p35/sck1/scl0 * 1 / irq5 p34/rxd1/sda0 * 1 p33/txd1/scl1 * 1 p32/sck0/sda1 * 1 / irq4 p31/rxd0 p30/txd0 6-bit i/o port also functioning as sci (channel 0, 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1), interrupt input pins ( irq4 , irq5 ), iic (channel 0, 1) i/o pins (scl0, sda0, scl1, sda1) * 1 port 4 * 3 8-bit input port p47/an7/da1 p46/an6/da0 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 8-bit input port also functioning as a/d converter analog inputs (an7 to an0) and d/a converter analog outputs (da1, da0)
section 9 i/o ports rev. 6.00 feb 22, 2005 page 225 of 1484 rej09b0103-0600 port description pins mode 4 mode 5 mode 6 mode 7 port 9 4-bit input port p93/an11 p92/an10 p91/an9 p90/an8 4-bit input port also functioning as a/d converter analog inputs (an11 to an8) port a 4-bit i/o port on-chip mos input pull-up open-drain output capability pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 4-bit i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) and address outputs (a19 to a16) 4-bit i/o port also function- ing as sci (channel 2) i/o pins (txd2, rxd2, sck2) port b 8-bit i/o port on-chip mos input pull-up open-drain output capability pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 pb0/a8/tioca3 8-bit i/o port also functioning as tpu i/o pins (tiocb5, tioca5, tiocb4, tioca4, tiocd3, tiocc3, tiocb3, tiioca3) and address outputs (a15 to a8) 8-bit i/o port also functioning as tpu i/o pins (tiocb5, tioca5, tiocb4, tioca4, tiocd3, tiocc3, tiocb3, tiioca3) port c 8-bit i/o port on-chip mos input pull-up open-drain output capability pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 8-bit i/o port also functioning as address outputs (a7 to a0) i/o port port d 8-bit i/o port on-chip mos input pull-up pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 pd0/d8 data bus input/output i/o port
section 9 i/o ports rev. 6.00 feb 22, 2005 page 226 of 1484 rej09b0103-0600 port description pins mode 4 mode 5 mode 6 mode 7 port e 8-bit i/o port on-chip mos input pull-up pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 in 8-bit-bus mode: i/o port in 16-bit-bus mode: data bus input/output i/o port port f 6-bit i/o port schmitt- triggered input (pf3, pf0) pf7/ when ddr = 0: input port when ddr = 1 (after reset): output when ddr = 0 (after reset): input port when ddr = 1: output pf6/ as pf5/ rd pf4/ hwr pf3/ lwr / adtrg / irq3 rd , hwr , lwr outputs adtrg , irq3 input i/o port adtrg , irq3 input pf0/ irq2 irq2 input, i/o port port h 8-bit i/o port ph7/pwm1h ph6/pwm1g ph5/pwm1f ph4/pwm1e ph3/pwm1d ph2/pwm1c ph1/pwm1b ph0/pwm1a function as both motor control pwm timer output pins and 8- bit i/o port. port j 8-bit i/o port pj7/pwm2h pj6/pwm2g pj5/pwm2f pj4/pwm2e pj3/pwm2d pj2/pwm2c pj1/pwm2b pj0/pwm2a function as both motor control pwm timer output pins and 8- bit i/o port. notes: 1. pins for i 2 c bus interface. i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. 2. the ppg output is not implemented in the h8s/2635 group. 3. the da output is not implemented in the h8s/2635 group.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 227 of 1484 rej09b0103-0600 9.2 port 1 note: the ppg output is not implemented in the h8s/2635 group. 9.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt pins ( irq0 and irq1 ), and address bus output pins (a23 to a20). port 1 pin functions change according to the operating mode. figure 9-1 shows the port 1 pin configuration. p17 (i/o) / po15 (output) / tiocb2 (i/o) / tclkd (input) p16 (i/o) / po14 (output) / tioca2 (i/o) / irq1 (input) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) / irq0 (input) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) / a23 (output) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) / a22 (output) p11 (i/o) / po9 (output) / tiocb0 (i/o) / a21 (output) p10 (i/o) / po8 (output) / tioca0 (i/o) / a20 (output) port 1 port 1 pins pin functions in modes 4 to 6 p17 (i/o) / po15 (output) / tiocb2 (i/o) / tclkd (input) p16 (i/o) / po14 (output) / tioca2 (i/o) / irq1 (input) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) / irq0 (input) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) p11 (i/o) / po9 (output) / tiocb0 (i/o) p10 (i/o) / po8 (output) / tioca0 (i/o) pin functions in mode 7 figure 9-1 port 1 pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 228 of 1484 rej09b0103-0600 9.2.2 register configuration table 9-2 shows the port 1 register configuration. table 9-2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'fe30 port 1 data register p1dr r/w h'00 h'ff00 port 1 register port1 r undefined h'ffb0 note: * lower 16 bits of the address. port 1 data direction register (p1ddr) bit:76543210 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value:00000000 r/w:wwwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p1ddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port 1 data register (p1dr) bit:76543210 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). p1dr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 229 of 1484 rej09b0103-0600 port 1 register (port1) bit:76543210 p17 p16 p15 p14 p13 p12 p11 p10 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its prior state in software standby mode. 9.2.3 pin functions port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt input pins ( irq0 and irq1 ), and address bus output pins (a23 to a20). port 1 pin functions are shown in table 9-3. note: the ppg output is not implemented in the h8s/2635 group.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 230 of 1484 rej09b0103-0600 table 9-3 port 1 pin functions pin selection method and pin functions p17/po15/ tiocb2/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 setting (by bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, and bits cclr1 and cclr0 in tcr2), bits tpsc2 to tpsc0 in tcr0 and tcr5, bit nder15 in nderh, and bit p17ddr. tpu channel 2 setting table below (1) table below (2) p17ddr ? 0 1 1 nder15 ? ? 0 1 pin function tiocb2 output p17 input p17 output po15 output tiocb2 input * 1 tclkd input * 2 notes: 1. tiocb2 input when md3 to md0 = b'0000 or b'01xx, and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'10 b'10 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 9 i/o ports rev. 6.00 feb 22, 2005 page 231 of 1484 rej09b0103-0600 pin selection method and pin functions p16/po14/ tioca2/ irq1 the pin function is switched as shown below according to the combination of the tpu channel 2 setting (by bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, and bits cclr1 and cclr0 in tcr2), bit nder14 in nderh, and bit p16ddr. tpu channel 2 setting table below (1) table below (2) p16ddr ? 0 1 1 nder14 ? ? 0 1 pin function tioca2 output p16 input p16 output po14 output tioca2 input * 1 irq1 input tpu channel 2 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'01 b'01 output function ? output compare output ?pwm mode 1 output * 2 pwm mode 2 output ? x: don?t care notes: 1. tioca2 input when md3 to md0 = b'0000 or b'01xx, and ioa3 = 1. 2. tiocb2 output is disabled.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 232 of 1484 rej09b0103-0600 pin selection method and pin functions p15/po13/ tiocb1/tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 setting (by bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, and bits cclr1 and cclr0 in tcr1), bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, bit nder13 in nderh, and bit p15ddr. tpu channel 1 setting table below (1) table below (2) p15ddr ? 0 1 1 nder13 ? ? 0 1 pin function tiocb1 output p15 input p15 output po13 output tiocb1 input * 1 tclkc input * 2 notes: 1. tiocb1 input when md3 to md0 = b'0000 or b'01xx, and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110; or when the setting for either tcr4 or tcr5 is tpsc2 to tpsc0 = b'101. tclkc input when channels 2 and 4 are set to phase counting mode. tpu channel 1 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'10 b'10 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 9 i/o ports rev. 6.00 feb 22, 2005 page 233 of 1484 rej09b0103-0600 pin selection method and pin functions p14/po12/ tioca1/ irq0 the pin function is switched as shown below according to the combination of the tpu channel 1 setting (by bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, and bits cclr1 and cclr0 in tcr1), bit nder12 in nderh, and bit p14ddr. tpu channel 1 setting table below (1) table below (2) p14ddr ? 0 1 1 nder12 ? ? 0 1 pin function tioca1 output p14 input p14 output po12 output tioca1 input * 1 irq0 input tpu channel 1 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'01 b'01 output function ? output compare output ?pwm mode 1 output * 2 pwm mode 2 output ? x: don't care notes: 1. tioca1 input when md3 to md0 = b'0000 or b'01xx, and ioa3 to ioa0 = b'10xx. 2. tiocb1 output is disabled.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 234 of 1484 rej09b0103-0600 pin selection method and pin functions p13/po11/ tiocd0/tclkb/ a23 the pin function is switched as shown below according to the combination of the operating mode, and the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bits ae3 to ae0 in pfcr, bit nder11 in nderh, and bit p13ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1110 b'1111 tpu channel 0 setting table below (1) table below (2) ? p13ddr ? 0 1 1 ? nder11 ? ? 0 1 ? pin function tiocd0 output p13 input p13 output po11 output a23 output tiocd0 input * 1 tclkb input * 2 operating mode mode 7 ae3 to ae0 ? tpu channel 0 setting table below (1) table below (2) p13ddr ? 0 1 1 nder11 ? ? 0 1 pin function tiocd0 output p13 input p13 output po11 output tiocd0 input * 1 tclkb input * 2 notes: 1. tiocd0 input when md3 to md0 = b'0000, and iod3 to iod0 = b'10xx. 2. tclkb input when the setting for tcr0 to tcr2 is: tpsc2 to tpsc0 = b'101. tclkb input when channels 1 and 5 are set to phase counting mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 235 of 1484 rej09b0103-0600 pin selection method and pin functions tpu channel 0 setting (2) (1) (2) (2) (1) (2) p13/po11/ tiocd0/tclkb/ a23 md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'110 b'110 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 9 i/o ports rev. 6.00 feb 22, 2005 page 236 of 1484 rej09b0103-0600 pin selection method and pin functions p12/po10/ tiocc0/tclka/ a22 the pin function is switched as shown below according to the combination of the operating mode, and the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bits ae3 to ae0 in pfcr, bit nder10 in nderh, and bit p12ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1110 b'1111 tpu channel 0 setting table below (1) table below (2) ? p12ddr ? 0 1 1 ? nder10 ? ? 0 1 ? pin function tiocc0 output p12 input p12 output po10 output a22 output tiocc0 input * 1 tclka input * 2 operating mode mode 7 ae3 to ae0 ? tpu channel 0 setting table below (1) table below (2) p12ddr ? 0 1 1 nder10 ? ? 0 1 pin function tiocc0 output p12 input p12 output po10 output tiocc0 input * 1 tclka input * 2
section 9 i/o ports rev. 6.00 feb 22, 2005 page 237 of 1484 rej09b0103-0600 pin selection method and pin functions tpu channel 0 setting (2) (1) (2) (1) (1) (2) p12/po10/ tiocc0/tclka/ a22 md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'101 b'101 output function ? output compare output ?pwm mode 1 output * 3 pwm mode 2 output ? x: don?t care notes: 1. tiocc0 input when md3 to md0 = b'0000, and ioc3 to ioc0 = b'10xx. 2. tclka input when the setting for tcr0 to tcr5 is: tpsc2 to tpsc0 = b'100. tclka input when channels 1 and 5 are set to phase counting mode. 3. tiocd0 output is disabled. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and setting (2) applies.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 238 of 1484 rej09b0103-0600 pin selection method and pin functions p11/po9/tiocb0/ a21 the pin function is switched as shown below according to the combination of the operating mode, and the tpu channel 0 setting (by bits md3 to md0 in tmdr0, and bits iob3 to iob0 in tior0h), bits ae3 to ae0 in pfcr, bit nder9 in nderh, and bit p11ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1101 b'1110 to b'1111 tpu channel 0 setting table below (1) table below (2) ? p11ddr ? 0 1 1 ? nder9 ? ? 0 1 ? pin function tiocb0 output p11 input p11 output po9 output a21 output tiocb0 input * operating mode mode 7 ae3 to ae0 ? tpu channel 0 setting table below (1) table below (2) p11ddr ? 0 1 1 nder9 ? ? 0 1 pin function tiocb0 output p11 input p11 output po9 output tiocb0 input * note: * tiocb0 input when md3 to md0 = b'0000, and iob3 to iob0 = b'10xx.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 239 of 1484 rej09b0103-0600 pin selection method and pin functions p11/po9/tiocb0/ a21 tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'010 b'010 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 9 i/o ports rev. 6.00 feb 22, 2005 page 240 of 1484 rej09b0103-0600 pin selection method and pin functions p10/po8/tioca0/ a20 the pin function is switched as shown below according to the combination of the operating mode, and the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bits ae3 to ae0 in pfcr, bit nder8 in nderh, sae0 bit in dmabcrh, and bit p10ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1110 b'1101 to b'1111 tpu channel 0 setting table below (1) table below (2) ? p10ddr ? 0 1 1 ? nder8 ? ? 0 1 ? pin function tioca0 output p10 input p10 output po8 output a20 output tioca0 input * 1 operating mode mode 7 ae3 to ae0 ? tpu channel 0 setting table below (1) table below (2) p10ddr ? 0 1 1 nder8 ? ? 0 1 pin function tioca0 output p10 input p10 output po8 output tioca0 input * 1
section 9 i/o ports rev. 6.00 feb 22, 2005 page 241 of 1484 rej09b0103-0600 pin selection method and pin functions p10/po8/tioca0/ a20 tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'001 b'001 output function ? output compare output ?pwm mode 1 output * 2 pwm mode 2 output ? x: don?t care notes: 1. tioca0 input when md3 to md0 = b'0000, and ioa3 to ioa0 = b'10xx. 2. tiocb0 output is disabled.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 242 of 1484 rej09b0103-0600 9.3 port 3 9.3.1 overview port 3 is an 6-bit i/o port. port 3 is a multi-purpose port for sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1), external interrupt input pins ( irq4 , irq5 ), and iic i/o pins * (scl0, sda0, scl1, sda1). all of the port 3 pin functions have the same operating mode. the configuration for each of the port 3 pins is shown in figure. 9-2. note: * available when using i 2 c bus interface as an option in the h8s/2638, h8s/2639, and h8s/2630 (the product equipped with the i 2 c bus interface is the w-mask version). p35 (i/o) / sck1 (i/o) / scl0 * (i/o) / irq5 (input) p34 (i/o) / rxd1 (input) / sda0 * (i/o) p33 (i/o) / txd1 (input) / scl1 * (i/o) p32 (i/o) / sck0 (i/o) / sda1 * (i/o) / irq4 (input) p31 (i/o) / rxd0 (input) p30 (i/o) / txd0 (output) note: * available when using i 2 c bus interface as an option in the h8s/2638, h8s/2639, and h8s/2630 (the product equipped with the i 2 c bus interface is the w-mask version). port 3 pins port 3 figure 9-2 port 3 pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 243 of 1484 rej09b0103-0600 9.3.2 register configuration table 9-4 shows the configuration of port 3 registers. table 9-4 port 3 register configuration name abbreviation r/w initial value * 2 address * 1 port 3 data direction register p3ddr w b' ** 000000 h'fe32 port 3 data register p3dr r/w b' ** 000000 h'ff02 port 3 register port3 r undefined h'ffb2 port 3 open drain control register p3odr r/w b' ** 000000 h'fe46 notes: 1. lower 16 bits of the address. 2. value of bits 5 to 0. port 3 data direction register (p3ddr) 7 ? undefined ? bit initial value read/write 6 ? undefined ? 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w 0 p30ddr 0 w p3ddr is an 8-bit write-dedicated register, which specifies the i/o for each port 3 pin by bit. read is disenabled. if a read is carried out, undefined values are read out. by setting p3ddr to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input. p3ddr is initialized to b'**000000 by a reset and in hardware standby mode. the previous state is maintained in software standby mode. the pin state is determined by specifying sci, iic * , p3ddr, and p3dr. note: * available when using i 2 c bus interface as an option in the h8s/2638, h8s/2639, and h8s/2630 (the product equipped with the i 2 c bus interface is the w-mask version).
section 9 i/o ports rev. 6.00 feb 22, 2005 page 244 of 1484 rej09b0103-0600 port 3 data register (p3dr) 7 ? undefined ? bit initial value read/write 6 ? undefined ? 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w 0 p30dr 0 r/w p3dr is an 8-bit readable/writable register, which stores the output data of port 3 pins (p35 to p30). p3dr is initialized to b'**000000 by a reset and in hardware standby mode. the previous state is maintained in software standby mode. port 3 register (port3) 7 ? undefined ? bit initial value read/write 6 ? undefined ? 5 p35 ? * r 4 p34 ? * r 3 p33 ? * r 2 p32 ? * r 1 p31 ? * r 0 p30 ? * r note: * determined by the state of pins p35 to p30. port3 is an 8-bit read-dedicated register, which reflects the state of pins. write is disenabled. always carry out writing off output data of port 3 pins (p35 to p30) to p3dr without fail. when p3ddr is set to 1, if port 3 is read, the values of p3dr are read. when p3ddr is cleared to 0, if port 3 is read, the states of pins are read out. p3ddr and p3dr are initialized by a reset and in hardware standby mode, so port3 is determined by the state of the pins. the previous state is maintained in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 245 of 1484 rej09b0103-0600 port 3 open drain control register (p3odr) 7 ? undefined ? bit initial value read/write 6 ? undefined ? 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w 0 p30odr 0 r/w p3odr is an 8-bit readable/writable register, which controls the on/off of port 3 pins (p35 to p30). by setting p3odr to 1, the port 3 pins become an open drain out, and when cleared to 0 they become cmos output. p3odr is initialized to b'**000000 by a reset and in hardware standby mode. the previous state is maintained in software standby mode. 9.3.3 pin functions the port 3 pins double as sci i/o input pins (txd0, rxd0, sck0, txd1, rxd1, and sck1) external interrupt input pins ( irq4 and irq5 ), and iic i/o pins * (scl0, sda0, scl1, and sda1). the functions of port 3 pins are shown in table 9-5. note: * available when using i 2 c bus interface as an option in the h8s/2638, h8s/2639, and h8s/2630 (the product equipped with the i 2 c bus interface is the w-mask version).
section 9 i/o ports rev. 6.00 feb 22, 2005 page 246 of 1484 rej09b0103-0600 table 9-5 port 3 pin functions pin selection method and pin functions p35/sck1/ scl0 * 1 / irq5 switches as follows according to combinations of iccr0 ice bit * 1 of iic0, bit c/ a of smr1, bits cke0 and cke1 of scr1, and bit p35ddr. when used as a scl0 i/o pin, always be sure to clear the following bits to 0: bit c/ a of smr1, and bits cke0 and cke1 of scr1. the scl0 output format is nmos open drain output, enabling direct bus driving. ice * 1 01 cke1 0 1 0 c/ a 01?0 cke0 0 1 ? ? 0 p35ddr 0 1 ???? pin function p35 input p35 output * sck1 output * sck1 output * sck1 input scl0 i/o irq5 input note: * when p35odr = 1, it becomes nmos open drain output. in w mask-rom versions, the output format is nmos push-pull. however, it becomes nmos open drain output when p35odr = 1. p34/rxd1/ sda0 * 1 switches as follows according to combinations of iccr0 ice bit * 1 of iic0, bit re of scr1 and bit p34ddr. the sda0 output format is nmos open drain output, enabling direct bus driving. ice * 1 01 re 0 1 ? p34ddr 0 1 ? ? pin function p34 input p34 output * rxd1 input sda0 i/o note: * when p34odr = 1, it becomes nmos open drain output. in w mask-rom versions, the output format is nmos push-pull. however, it becomes nmos open drain output when p34odr = 1.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 247 of 1484 rej09b0103-0600 pin selection method and pin functions p33/txd1/ scl1 * 1 switches as follows according to combinations of iccr1 ice bit * 1 of iic1, bit te of scr1 and bit p33ddr. the scl1 output format is nmos open drain output, enabling direct bus driving. ice * 1 01 te 0 1 ? p33ddr 0 1 ? ? pin function p33 input p33 output * txd1 output * scl1 i/o note: * when p33odr = 1, it becomes nmos open drain output. p32/sck0/ sda1 * 1 / irq4 switches as follows according to combinations of iccr1 ice bit * 1 of iic1, bit c/ a of smr0, bits cke0 and cke1 of scr0, and bit p32ddr. when used as a sda1 i/o pin, always be sure to clear the following bits to 0: smr0 c/ a bit, scr0 cke0 and cke1 bits. the sda1 output format is nmos open drain output, enabling direct bus driving. ice * 1 01 cke1 0 1 0 c/ a 01?0 cke0 0 1 ? ? 0 p32ddr 0 1 ???? pin function p32 input p32 output sck0 output * sck0 output * sck0 input sda1 i/o irq4 input note: * when p32odr = 1, it becomes nmos open drain output. switches as follows according to combinations of bit re of scr0 and bit p31ddr. p31/rxd0/ irrxd re 0 1 p31ddr 0 1 ? pin function p31 input p31 output * rxd0 input note: * when p31odr = 1, it becomes nmos open drain output. switches as follows according to combinations of bit te of scr0 and bit p30ddr. p30/txd0/ irtxd te 0 1 p30ddr 0 1 ? pin function p30 input p30 output * txd0 output * note: * when p30odr = 1, it becomes nmos open drain output. note: 1. available when using i 2 c bus interface (the w-mask version of the h8s/2638, h8s/2639, and h8s/2630 only). in w mask-rom versions, the output format is nmos push-pull. however, it becomes nmos open drain output when p34odr = 1 and p35odr = 1.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 248 of 1484 rej09b0103-0600 9.4 port 4 note: the da output is not implemented in the h8s/2635 group. 9.4.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0, da1). port 4 pin functions are the same in all operating modes. figure 9-3 shows the port 4 pin configuration. p47 p46 p45 p44 p43 p42 p41 p40 (input) / (input) / (input) / (input) / (input) / (input) / (input) / (input) / an7 (input) / da1 (output) an6 (input) / da0 (output) an5 (input) an4 (input) an3 (input) an2 (input) an1 (input) an0 (input) port 4 pins port 4 figure 9-3 port 4 pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 249 of 1484 rej09b0103-0600 9.4.2 register configuration table 9-6 shows the port 4 register configuration. port 4 is an input-only port, and does not have a data direction register or data register. table 9-6 port 4 registers name abbreviation r/w initial value address * port 4 register port4 r undefined h'ffb3 note: * lower 16 bits of the address. port 4 register (port4): the pin states are always read when a port 4 read is performed. bit:76543210 p47 p46 p45 p44 p43 p42 p41 p40 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins p47 to p40. 9.4.3 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1).
section 9 i/o ports rev. 6.00 feb 22, 2005 page 250 of 1484 rej09b0103-0600 9.5 port 9 9.5.1 overview port 9 is a 4-bit input-only port. port 9 pins also function as a/d converter analog input pins (an8 to an11). port 9 pin functions are the same in all operating modes. figure 9-4 shows the port 9 pin configuration. p93 p92 p91 p90 (input) / (input) / (input) / (input) / an11 (input) an10 (input) an9 (input) an8 (input) port 9 pins port 9 figure 9-4 port 9 pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 251 of 1484 rej09b0103-0600 9.5.2 register configuration table 9-7 shows the port 9 register configuration. port 9 is an input-only port, and does not have a data direction register or data register. table 9-7 port 9 registers name abbreviation r/w initial value address * port 9 register port9 r undefined h'ffb8 note: * lower 16 bits of the address. port 9 register (port9): the pin states are always read when a port 9 read is performed. bit:76543210 ????p93p92p91p90 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w : ???? r r r r note: * determined by state of pins p93 to p90. 9.5.3 pin functions port 9 pins also function as a/d converter analog input pins (an8 to an11) are multipurpose pins which function as a/d converter analog input pins (an8 to an11).
section 9 i/o ports rev. 6.00 feb 22, 2005 page 252 of 1484 rej09b0103-0600 9.6 port a 9.6.1 overview port a is a 4-bit i/o port. port a pins also function as address bus outputs and sci2 i/o pins (sck2, rxd2, and txd2). the pin functions change according to the operating mode. port a has an on-chip mos input pull-up function that can be controlled by software. figure 9-5 shows the port a pin configuration. pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 port a pins pin functions in mode 7 pa3 (i/o) / a19 (output) / sck2 (i/o) pa2 (i/o) / a18 (output) / rxd2 (input) pa1 (i/o) / a17 (output) / txd2 (output) pa0 (i/o) / a16 (output) pin functions in modes 4 to 6 pa3 (i/o) / sck2 (output) pa2 (i/o) / rxd2 (input) pa1 (i/o) / txd2 (output) pa0 (i/o) port a figure 9-5 port a pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 253 of 1484 rej09b0103-0600 9.6.2 register configuration table 9-8 shows the port a register configuration. table 9-8 port a registers name abbreviation r/w initial value * 2 address * 1 port a data direction register paddr w h'0 h'fe39 port a data register padr r/w h'0 h'ff09 port a register porta r undefined h'ffb9 port a mos pull-up control register papcr r/w h'0 h 'ff40 port a open-drain control register paodr r/w h'0 h'ff47 notes: 1. lower 16 bits of the address. 2. value of bits 3 to 0. port a data direction register (paddr) bit:76543210 ? ? ? ? pa3ddr pa2ddr pa1ddr pa0ddr initial value : undefined undefined undefined undefined 0000 r/w:????wwww paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. bits 7 to 4 are reserved; they return an undetermined value if read. paddr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 to 6 the corresponding port a pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, irrespective of the value of bits pa3ddr to pa0ddr. when pins are not used as address outputs, setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 254 of 1484 rej09b0103-0600 ? mode 7 setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. port a data register (padr) bit:76543210 ? ? ? ? pa3dr pa2dr pa1dr pa0dr initial value : undefined undefined undefined undefined 0000 r/w : ? ? ? ? r/w r/w r/w r/w padr is an 8-bit readable/writable register that stores output data for the port a pins (pa3 to pa0). bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. padr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port a register (porta) bit:76543210 ? ? ? ? pa3 pa2 pa1 pa0 initial value : undefined undefined undefined undefined ? * ? * ? * ? * r/w:???? r r r r note: * determined by state of pins pa3 to pa0. porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa3 to pa0) must always be performed on padr. bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 255 of 1484 rej09b0103-0600 port a mos pull-up control register (papcr) bit:76543210 ? ? ? ? pa3pcr pa2pcr pa1pcr pa0pcr initial value : undefined undefined undefined undefined 0000 r/w : ? ? ? ? r/w r/w r/w r/w papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on an individual bit basis. bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, in the sci?s scmr, smr, and scr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in the sci?s scmr, smr, and scr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. papcr is initialized by a reset or to h'0 (bits 3 to 0), and in hardware standby mode. it retains its prior state in software standby mode. port a open drain control register (paodr) bit:76543210 ? ? ? ? pa3odr pa2odr pa1odr pa0odr initial value : undefined undefined undefined undefined 0000 r/w : ? ? ? ? r/w r/w r/w r/w paodr is an 8-bit readable/writable register that controls whether pmos is on or off for each port a pin (pa3 to pa0). bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. when pins are not address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, setting a paodr bit makes the corresponding port a pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. paodr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 256 of 1484 rej09b0103-0600 9.6.3 pin functions port a pins also function as sci input/output pins (txd2, rxd2, sck2) and address bus output pins (a19 to a16). port a pin functions are shown in table 9-9. table 9-9 port a pin functions pin selection method and pin functions pa3/a19/sck2 the pin function is switched as shown below according to the operating mode, bits ae3 to ae0 in pfcr, bit c/ a in smr and bits cke0 and cke1 in scr of sci2, and bit pa3ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1011 b'1100 to b'1111 cke1 0 1 ? c/ a 01?? cke0 0 1 ? ? ? pa3ddr 0 1 ? ? ? ? pin function pa3 input pa3 output sck2 output sck2 output sck2 input a19 output operating mode mode 7 cke1 0 1 c/ a 01? cke0 0 1 ? ? pa3ddr 0 1 ? ? ? pin function pa3 input pa3 output sck2 output sck2 output sck2 input
section 9 i/o ports rev. 6.00 feb 22, 2005 page 257 of 1484 rej09b0103-0600 pin selection method and pin functions pa2/a18/rxd2 the pin function is switched as shown below according to the operating mode, bits ae3 to ae0 in pfcr, bit re in scr of sci2, and bit pa2ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1011 b'1011 to b'1111 re 0 1 ? pa2ddr 0 1 ? ? pin function pa2 input pa2 output rxd2 input a18 output operating mode mode 7 re 0 1 pa2ddr 0 1 ? pin function pa2 input pa2 output rxd2 input pa1/a17/txd2 the pin function is switched as shown below according to the operating mode, bits ae3 to ae0 in pfcr, bit te in scr of sci2, and bit pa1ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1001 b'1010 to b'1111 te 0 1 ? pa1ddr 0 1 ? ? pin function pa1 input pa1 output txd2 output a17 output operating mode mode 7 te 0 1 pa1ddr 0 1 ? pin function pa1 input pa1 output txd2 output
section 9 i/o ports rev. 6.00 feb 22, 2005 page 258 of 1484 rej09b0103-0600 pin selection method and pin functions pa0/a16 the pin function is switched as shown below according to the operating mode, bits ae3 to ae0 in pfcr, and bit pa0ddr. operating mode modes 4 to 6 ae3 to ae0 b'0000 to b'1000 b'1001 to b'1111 pa0ddr 0 1 ? pin function pa0 input pa0 output a16 output operating mode mode 7 pa0ddr 0 1 pin function pa0 input pa0 output 9.6.4 pin functions modes 4 to 6: in modes 4 to 6, port a pins function as address outputs according to the setting of ae3 to ae0 in pfcr; when they do not function as address outputs, the pins function as sci i/o pins and i/o ports. port a pin functions in modes 4 to 6 are shown in figure 9-6. pa3 (i/o) / a19 (output) / sck2 (i/o) pa2 (i/o) / a18 (output) / rxd2 (input) pa1 (i/o) / a17 (output) / txd2 (output) pa0 (i/o) / a16 (output) port a figure 9-6 port a pin functions (modes 4 to 6) mode 7: in mode 7, port a pins function as i/o ports and sci2 i/o pins (sck2, txd2, rxd2). input or output can be specified for each pin on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. port a pin functions are shown in figure 9-7.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 259 of 1484 rej09b0103-0600 pa3 (i/o) / sck2 (i/o) pa2 (i/o) / rxd2 (input) pa1 (i/o) / txd2 (output) pa0 (i/o) port a figure 9-7 port a pin functions (mode 7) 9.6.5 mos input pull-up function port a has an on-chip mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, in the sci?s scmr, smr, and scr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in the sci?s scmr, smr, and scr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 9-10summarizes the mos input pull-up states. table 9-10 mos input pull-up states (port a) pin states reset hardware standby mode software standby mode in other operations address output or sci output off off off off other than above on/off on/off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 260 of 1484 rej09b0103-0600 9.7 port b 9.7.1 overview port b is an 8-bit i/o port. port b pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) and as address outputs; the pin functions change according to the operating mode. port b has an on-chip mos input pull-up function that can be controlled by software. figure 9-8 shows the port b pin configuration. pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd3 pb2 / a10/tiocc3 pb1 / a9 /tiodb3 pb0 / a8 /tioca3 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (input) / (input) / (input) / (input) / (input) / (input) / (input) / (input) / a15 a14 a13 a12 a11 a10 a9 a8 (output) / tiocb5 (i/o) (output) / tioca5 (i/o) (output) / tiocb4 (i/o) (output) / tioca4 (i/o) (output) / tiocd3 (i/o) (output) / tiocc3 (i/o) (output) / tiocb3 (i/o) (output) / tioca3 (i/o) port b pins pin functions in mode 7 pin functions in modes 4 to 6 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (i/o) / tiocb5 (i/o) (i/o) / tioca5 (i/o) (i/o) / tiocb4 (i/o) (i/o) / tioca4 (i/o) (i/o) / tiocd3 (i/o) (i/o) / tiocc3 (i/o) (i/o) / tiocb3 (i/o) (i/o) / tioca3 (i/o) port b figure 9-8 port b pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 261 of 1484 rej09b0103-0600 9.7.2 register configuration table 9-11 shows the port b register configuration. table 9-11 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'fe3a port b data register pbdr r/w h'00 h'ff0a port b register portb r undefined h'ffba port b mos pull-up control register pbpcr r/w h'00 h 'ff41 port b open-drain control register pbodr r/w h'00 h'fe48 note: * lower 16 bits of the address. port b data direction register (pbddr) bit:76543210 pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr initial value:00000000 r/w:wwwwwwww pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 to 6 the corresponding port b pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, irrespective of the value of the pbddr bits. when pins are not used as address outputs, setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 262 of 1484 rej09b0103-0600 port b data register (pbdr) bit:76543210 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port b register (portb) bit:76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 263 of 1484 rej09b0103-0600 port b mos pull-up control register (pbpcr) bit:76543210 pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, in the tpu?s tior, and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in the tpu?s tior and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. pbpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port b open drain control register (pbodr) bit:76543210 pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbodr is an 8-bit readable/writable register that controls the pmos on/off state for each port b pin (pb7 to pb0). when pins are not address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, setting a pbodr bit makes the corresponding port b pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. pbodr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 264 of 1484 rej09b0103-0600 9.7.3 pin functions modes 4 to 6: in modes 4 to 6, the corresponding port b pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr. when pins are not used as address outputs, they function as tpu i/o pins and i/o ports. port b pin functions in modes 4 to 6 are shown in figure 9-9. pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b (i/o) / a15 (output) / tiocb5 (i/o) (i/o) / a14 (output) / tioca5 (i/o) (i/o) / a13 (output) / tiocb4 (i/o) (i/o) / a12 (output) / tioca4 (i/o) (i/o) / a11 (output) / tiocd3 (i/o) (i/o) / a10 (output) / tiocc3 (i/o) (i/o) / a9 (output) / tiocb3 (i/o) (i/o) / a8 (output) / tioca3 (i/o) figure 9-9 port b pin functions (modes 4 to 6) mode 7: in mode 7, port b pins function as i/o ports and tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5). input or output can be specified for each pin on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. port b pin functions in mode 7 are shown in figure 9-10. pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b (i/o) / tiocb5 (i/o) (i/o) / tioca5 (i/o) (i/o) / tiocb4 (i/o) (i/o) / tioca4 (i/o) (i/o) / tiocd3 (i/o) (i/o) / tiocc3 (i/o) (i/o) / tiocb3 (i/o) (i/o) / tioca3 (i/o) figure 9-10 port b pin functions (mode 7)
section 9 i/o ports rev. 6.00 feb 22, 2005 page 265 of 1484 rej09b0103-0600 9.7.4 mos input pull-up function port b has an on-chip mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, in the tpu?s tior, and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in the tpu?s tior and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 9-12 summarizes the mos input pull-up states. table 9-12 mos input pull-up states (port b) pin states reset hardware standby mode software standby mode in other operations address output or tpu output off off off off other than above on/off on/off legend: off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 266 of 1484 rej09b0103-0600 9.8 port c 9.8.1 overview port c is an 8-bit i/o port. port c has an address bus output function. the pin functions change according to the operating mode. port c has an on-chip mos input pull-up function that can be controlled by software. figure 9-11 shows the port c pin configuration. pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 port c port c pins pin functions in mode 7 a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pin functions in modes 4 and 5 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in mode 6 pcddr = 1 a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pcddr = 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (input) (input) (input) (input) (input) (input) (input) (input) figure 9-11 port c pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 267 of 1484 rej09b0103-0600 9.8.2 register configuration table 9-13 shows the port c register configuration. table 9-13 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe3b port c data register pcdr r/w h'00 h'ff0b port c register portc r undefined h'ffbb port c mos pull-up control register pcpcr r/w h'00 h'ff42 port c open-drain control register pcodr r/w h'00 h'fe49 note: * lower 16 bits of the address. port c data direction register (pcddr) bit:76543210 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr initial value:00000000 r/w:wwwwwwww pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when the mode is changed to software standby mode. ? modes 4 and 5 the corresponding port c pins are address outputs irrespective of the value of the pcddr bits. ? mode 6 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 268 of 1484 rej09b0103-0600 port c data register (pcdr) bit:76543210 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port c register (portc) bit:76543210 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 269 of 1484 rej09b0103-0600 port c mos pull-up control register (pcpcr) bit:76543210 pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on an individual bit basis. in modes 6 and 7, if pcpcr is set to 1 when the port is in the input state in accordance with the settings of pcddr, the mos input pull-up is set to on. pcpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. port c open drain control register (pcodr) 7 pc7odr 0 r/w bit initial value read/write 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w 0 pc0odr 0 r/w pcddr is an 8-bit read/write register and controls pmos on/off of each pin (pc7 to pc0) of port c. if pcodr is set to 1 by setting ae3 to ae0 in pfcr in mode other than address output mode, port c pins function as nmos open drain outputs and when the setting is cleared to 0, the pins function as cmos outputs. pcodr is initialized to h'00 in reset mode or hardware standby mode. pcodr retains the last state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 270 of 1484 rej09b0103-0600 9.8.3 pin functions for each mode modes 4 and 5: in modes 4 and 5, port c pins function as address outputs automatically. figure 9-12 shows the port c pin functions. a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) port c figure 9-12 port c pin functions (modes 4 and 5) mode 6: in mode 6, port c pints function as address outputs or input ports and i/o can be specified in bit units. when each bit in pcddr is set to 1, the corresponding pin functions as an address output and when the bit cleared to 0, the pin functions as an input port. figure 9-13 shows the port c pin functions. a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pcddr = 1 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (input) (input) (input) (input) (input) (input) (input) (input) pcddr = 0 port c figure 9-13 port c pin functions (mode 6)
section 9 i/o ports rev. 6.00 feb 22, 2005 page 271 of 1484 rej09b0103-0600 mode 7: in mode 7, port c pins function as i/o ports and i/o can be specified for each pin in bit units. when each bit in pcddr is set to 1, the corresponding pin functions as an output port and when the bit is cleared to 0, the pin functions as an input port. figure 9-14 shows the port c pin functions. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port c figure 9-14 port c pin functions (mode 7)
section 9 i/o ports rev. 6.00 feb 22, 2005 page 272 of 1484 rej09b0103-0600 9.8.4 mos input pull-up function port c has an on-chip mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. in modes 6 and 7, when pcpcr is set to 1 in the input state by setting of pcddr, the mos input pull-up is set to on. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 9-14 summarizes the mos input pull-up states. table 9-14 mos input pull-up states (port c) pin states reset hardware standby mode software standby mode in other operations address output off off off off other than above on/off on/off legend: off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 273 of 1484 rej09b0103-0600 9.9 port d 9.9.1 overview port d is an 8-bit i/o port. port d has a data bus i/o function, and the pin functions change according to the operating mode. port d has an on-chip mos input pull-up function that can be controlled by software. figure 9-15 shows the port d pin configuration. pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d d15 d14 d13 d12 d11 d10 d9 d8 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port d pins pin functions in modes 4 to 6 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in mode 7 figure 9-15 port d pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 274 of 1484 rej09b0103-0600 9.9.2 register configuration table 9-15 shows the port d register configuration. table 9-15 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe3c port d data register pddr r/w h'00 h'ff0c port d register portd r undefined h'ffbc port d mos pull-up control register pdpcr r/w h'00 h'fe43 note: * lower 16 bits of the address. port d data direction register (pdddr) bit:76543210 pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr initial value:00000000 r/w:wwwwwwww pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. ? modes 4 to 6 the input/output direction specification by pdddr is ignored, and port d is automatically designated for data i/o. ? mode 7 setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 275 of 1484 rej09b0103-0600 port d data register (pddr) bit:76543210 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port d register (portd) bit:76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 276 of 1484 rej09b0103-0600 port d mos pull-up control register (pdpcr) bit:76543210 pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on an individual bit basis. when a pdddr bit is cleared to 0 (input port setting) in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 9.9.3 pin functions modes 4 to 6: in modes 4 to 6, port d pins are automatically designated as data i/o pins. port d pin functions in modes 4 to 6 are shown in figure 9-16. d15 d14 d13 d12 d11 d10 d9 d8 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 9-16 port d pin functions (modes 4 to 6) mode 7: in mode 7, port d pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 277 of 1484 rej09b0103-0600 port d pin functions in mode 7 are shown in figure 9-17. pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 9-17 port d pin functions (mode 7) 9.9.4 mos input pull-up function port d has an on-chip mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. when a pdddr bit is cleared to 0 in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 9-16 summarizes the mos input pull-up states. table 9-16 mos input pull-up states (port d) modes reset hardware standby mode software standby mode in other operations 4 to 6 off off off off 7 on/off on/off legend: off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 278 of 1484 rej09b0103-0600 9.10 port e 9.10.1 overview port e is an 8-bit i/o port. port e has a data bus i/o function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. port e has an on-chip mos input pull-up function that can be controlled by software. figure 9-18 shows the port e pin configuration. pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / port e pins pin functions in modes 4 to 6 pin functions in mode 7 d7 d6 d5 d4 d3 d2 d1 d0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port e figure 9-18 port e pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 279 of 1484 rej09b0103-0600 9.10.2 register configuration table 9-17 shows the port e register configuration. table 9-17 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'fe3d port e data register pedr r/w h'00 h'ff0d port e register porte r undefined h'ffbd port e mos pull-up control register pepcr r/w h'00 h'fe44 note: * lower 16 bits of the address. port e data direction register (peddr) bit:76543210 pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr initial value:00000000 r/w:wwwwwwww peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value w ill be read. peddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. ? modes 4 to 6 when 8-bit bus mode has been selected, port e pins function as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode has been selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. for details of 8-bit and 16-bit bus modes, see section 7, bus controller. ? mode 7 setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 280 of 1484 rej09b0103-0600 port e data register (pedr) bit:76543210 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port e register (porte) bit:76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 281 of 1484 rej09b0103-0600 port e mos pull-up control register (pepcr) bit:76543210 pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on an individual bit basis. when a peddr bit is cleared to 0 (input port setting) with 8-bit bus mode selected in mode 4, 5, or 6, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 9.10.3 pin functions modes 4 to 6: in modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port e pins are automatically designated as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. port e pin functions in modes 4 to 6 are shown in figure 9-19.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 282 of 1484 rej09b0103-0600 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e d7 d6 d5 d4 d3 d2 d1 d0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) 8-bit bus mode 16-bit bus mode (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 9-19 port e pin functions (modes 4 to 6) mode 7: in mode 7, port e pins function as i/o ports. input or output can be specified for each pin on a bit-by-bit basis. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. port e pin functions in mode 7 are shown in figure 9-20. pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 9-20 port e pin functions (mode 7)
section 9 i/o ports rev. 6.00 feb 22, 2005 page 283 of 1484 rej09b0103-0600 9.10.4 mos input pull-up function port e has an on-chip mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. when a peddr bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 9-18 summarizes the mos input pull-up states. table 9-18 mos input pull-up states (port e) modes reset hardware standby mode software standby mode in other operations 7 off off on/off on/off 4 to 6 8-bit bus 16-bit bus off off legend: off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 284 of 1484 rej09b0103-0600 9.11 port f 9.11.1 overview port f is a 6-bit i/o port. port f pins also function as external interrupt input pins ( irq2 and irq3 ), a/d trigger input pin ( adtrg ), bus control signal input/output pins ( as , rd , hwr , and lwr ), and the system clock ( ) output pin. figure 9-21 shows the port f pin configuration. pf7 / pf6 / as / lcas pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf0 / irq2 port f port f pins pf7 pf6 pf5 pf4 pf3 pf0 (input) / (output) (i/o) (i/o) (i/o) (i/o) / adtrg (input) / irq3 (input) (i/o) / irq2 (input) pin functions in mode 7 pf7 (input) / (output) as (output) rd (output) hwr (output) pf3 (i/o) / lwr (output) / adtrg (input) / irq3 (input) pf0 (i/o) / irq2 (input) pin functions in modes 4 to 6 figure 9-21 port f pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 285 of 1484 rej09b0103-0600 9.11.2 register configuration table 9-19 shows the port f register configuration. table 9-19 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w b'10000 ** 0 * 2 / b'00000 ** 0 * 2 h'fe3e port f data register pfdr r/w b'00000 ** 0 h'ff0e port f register portf r undefined h'ffbe notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. port f data direction register (pfddr) bit:76543210 pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr ? ? pf0ddr modes 4 to 6 initial value : 1 0 0 0 0 undefined undefined 0 r/w:wwwww??w mode 7 initial value : 0 0 0 0 0 undefined undefined 0 r/w:wwwww??w pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read. pfddr is initialized by a reset, and in hardware standby mode, to b'10000**0 in modes 4 to 6, and to b'00000**0 in mode 7. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 to 6 pin pf7 functions as the output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. the input/output direction specified by pfddr is ignored for pins pf6 to pf3, which are automatically designated as bus control outputs ( as , rd , hwr , and lwr ) (in the 8-bit mode, pin pf3 is designated by pfddr).
section 9 i/o ports rev. 6.00 feb 22, 2005 page 286 of 1484 rej09b0103-0600 pin pf0 is setting a pfddr bit to 1 makes the corresponding port f pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a pfddr bit to 1 makes the corresponding port f pin pf6 to pf3, pf0 an output port, or in the case of pin pf7, the output pin. clearing the bit to 0 makes the pin an input port. port f data register (pfdr) bit:76543210 pf7dr pf6dr pf5dr pf4dr pf3dr ? ? pf0dr initial value : 0 0 0 0 0 undefined undefined 0 r/w : r/w r/w r/w r/w r/w ? ? r/w pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf3, pf0). pfdr is initialized to b'00000**0 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port f register (portf) bit:76543210 pf7 pf6 pf5 pf4 pf3 ? ? pf0 initial value : ? * ? * ? * ? * ? * undefined undefined ? * r/w:rrrrr??r note: * determined by state of pins pf7 to pf3, pf0. portf is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port f pins (pf7 to pf3, pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 287 of 1484 rej09b0103-0600 9.11.3 pin functions port f pins also function as external interrupt input pins (irq2 and irq3), a/d trigger input pin ( adtrg ), bus control signal input/output pins ( as , rd , hwr , lwr ), and the system clock ( ) output pin. the pin functions differ between modes 4 to 6, and mode 7. port f pin functions are shown in table 9-20. table 9-20 port f pin functions pin selection method and pin functions pf7/ the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input output pf6/ as the pin function is switched as shown below according to bit pf6ddr. operating mode modes 4 to 6 mode 7 pf6ddr ? 0 1 pin function as output pf6 input pf6 output pf5/ rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 4 to 6 mode 7 pf5ddr ? 0 1 pin function rd output pf5 input pf5 output pf4/ hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 4 to 6 mode 7 pf4ddr ? 0 1 pin function hwr output pf4 input pf4 output
section 9 i/o ports rev. 6.00 feb 22, 2005 page 288 of 1484 rej09b0103-0600 pin selection method and pin functions pf3/ lwr / adtrg / irq3 the pin function is switched as shown below according to the operating mode, the bus mode, a/d converter bits trgs1 and trgs0, and bit pf3ddr. operating mode modes 4 to 6 mode 7 bus mode 16-bit bus mode 8-bit bus mode ? pf3ddr ?0101 pin function lwr output pin pf3 input pin pf3 output pin pf3 input pin pf3 output pin adtrg input pin * 1 irq3 input pin * 2 notes: 1. adtrg input when trgs0 = trgs1 = 1. 2. when used as an external interrupt input pin, do not use as an i/o pin for another function. pf0/ irq2 the pin function is switched as shown below according to the bit pf0ddr. pf0ddr 0 1 pin function pf0 input pf0 output irq2 input
section 9 i/o ports rev. 6.00 feb 22, 2005 page 289 of 1484 rej09b0103-0600 9.12 port h 9.12.1 overview port h is an 8-bit i/o port. port h pins also function as motor control pwm timer output pins (pwm1a to pwm1h). figure 9-22 shows the port h pin configuration. ph7 / pwm1h ph6 / pwm1g ph5 / pwm1f ph4 / pwm1e ph3 / pwm1d ph2 / pwm1c ph1 / pwm1b ph0 / pwm1a port h pin port h figure 9-22 port h pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 290 of 1484 rej09b0103-0600 9.12.2 register configuration table 9-21 shows the port h register configuration. table 9-21 port h registers name abbreviation r/w initial value address * port h data direction register phddr w h'00 h'fc20 port h data register phdr rw h'00 h'fc24 port h register porth r undefined h'fc28 note: * lower 16 bits of the address. port h data direction register (phddr) bit:76543210 ph7ddr ph6ddr ph5ddr ph4ddr ph3ddr ph2ddr ph1ddr ph0ddr initial value:00000000 r/w:wwwwwwww phddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port h. phddr cannot be read. if it is, an undefined value will be read. phddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port h data register (phdr) bit:76543210 ph7dr ph6dr ph5dr ph4dr ph3dr ph2dr ph1dr ph0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w phdr is an 8-bit readable/writeable register that stores output data for the port h pins (ph7 to ph0). phdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 291 of 1484 rej09b0103-0600 port h register (porth) bit:76543210 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by the state of ph7 to ph0 porth is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port h pins (ph7 to ph0) must always be performed on phdr. if a port h read is performed while phddr bits are set to 1, the phdr values are read. if a port h read is performed while phddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porth contents are determined by the pin states, as phddr and phdr are initialized. porth retains its prior state in software standby mode. 9.12.3 pin functions as shown in table 9-22, the port h pin functions can be switched, bit by bit, by changing the values of oe1a to oe1h of motor control pwm timer pwocr1 and phddr. table 9-22 port h pin functions 0e1a to 0e1h 1 0 phddr ? 0 1 pin function pwm output ph7 to ph0 input ph7 to ph0 output
section 9 i/o ports rev. 6.00 feb 22, 2005 page 292 of 1484 rej09b0103-0600 9.13 port j 9.13.1 overview port j is an 8-bit i/o port. port j pins also function as motor control pwm timer output pins (pwm2a to pwm2h). figure 9-23 shows the port j pin configuration. pj7 / pwm2h pj6 / pwm2g pj5 / pwm2f pj4 / pwm2e pj3 / pwm2d pj2 / pwm2c pj1 / pwm2b pj0 / pwm2a port j port j pin figure 9-23 port j pin functions
section 9 i/o ports rev. 6.00 feb 22, 2005 page 293 of 1484 rej09b0103-0600 9.13.2 register configuration table 9-23 shows the port j register configuration. table 9-23 port j registers name abbreviation r/w initial value address * port j data direction register pjddr w h'00 h'fc21 port j data register pjdr rw h'00 h'fc25 port j register portj r undefined h'fc29 note: * lower 16 bits of the address port j data direction register (pjddr) bit:76543210 pj7ddr pj6ddr pj5ddr pj4ddr pj3ddr pj2ddr pj1ddr pj0ddr initial value:00000000 r/w:wwwwwwww pjddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port j. pjddr cannot be read. if it is, an undefined value will be read. pjddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port j data register (pjdr) bit:76543210 pj7dr pj6dr pj5dr pj4dr pj3dr pj2dr pj1dr pj0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pjdr is an 8-bit readable/writeable register that stores output data for the port j pins (pj7 to pj0). pjdr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode.
section 9 i/o ports rev. 6.00 feb 22, 2005 page 294 of 1484 rej09b0103-0600 port j register (portj) bit:76543210 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr portj is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port j pins (pj7 to pj0) must always be performed on pjdr. if a port j read is performed while pjddr bits are set to 1, the pjdr values are read. if a port j read is performed while pjddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portj contents are determined by the pin states, as pjddr and pjdr are initialized. portj retains its prior state in software standby mode. 9.13.3 pin functions as shown in table 9-24, the port j pin functions can be switched, bit by bit, by changing the values of oe2a to oe2h of motor control pwm timer pwocr2 and pjddr. table 9-24 port j pin functions oe2a to oe2h 1 0 pjddr ? 0 1 pin function pwm output pj7 to pj0 input pj7 to pj0 output
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 295 of 1484 rej09b0103-0600 section 10 16-bit timer pulse unit (tpu) note: the h8s/2635 group is not equipped with a dtc or a ppg. 10.1 overview the chip has an on-chip 16-bit timer pulse unit (tpu) that comprises six 16-bit timer channels. 10.1.1 features ? maximum 16-pulse input/output ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channels 0 and 3 can also be used as buffer registers ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture possible ? register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set ? maximum of 15-phase pwm output possible by combination with synchronous operation ? buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible ? phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible ? cascaded operation ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow ? fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 296 of 1484 rej09b0103-0600 ? 26 interrupt sources ? for channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently ? automatic transfer of register data ? block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (dtc) ? programmable pulse generator (ppg) output trigger can be generated ? channel 0 to 3 compare match/input capture signals can be used as ppg output trigger ? a/d converter conversion start trigger can be generated ? channel 0 to 5 compare match a/input capture a signals can be used as a/d converter conversion start trigger ? module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. table 10-1 lists the functions of the tpu.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 297 of 1484 rej09b0103-0600 table 10-1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock /1 /4 /16 /64 tclka tclkb tclkc tclkd /1 /4 /16 /64 /256 tclka tclkb /1 /4 /16 /64 /1024 tclka tclkb tclkc /1 /4 /16 /64 /256 /1024 /4096 tclka /1 /4 /16 /64 /1024 tclka tclkc /1 /4 /16 /64 /256 tclka tclkc tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b tgr4a tgr4b tgr5a tgr5b general registers/ buffer registers tgr0c tgr0d ??tgr3c tgr3d ?? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output 1 output compare match output toggle output input capture function synchronous operation pwm mode phase counting mode ? ? buffer operation ?? ??
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 298 of 1484 rej09b0103-0600 item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture ppg trigger tgr0a/ tgr0b compare match or input capture tgr1a/ tgr1b compare match or input capture tgr2a/ tgr2b compare match or input capture tgr3a/ tgr3b compare match or input capture ?? interrupt sources 5 sources compare match or input capture 0a compare match or input capture 0b compare match or input capture 0c compare match or input capture 0d overflow 4 sources compare match or input capture 1a compare match or input capture 1b overflow underflow 4 sources compare match or input capture 2a compare match or input capture 2b overflow underflow 5 sources compare match or input capture 3a compare match or input capture 3b compare match or input capture 3c compare match or input capture 3d overflow 4 sources compare match or input capture 4a compare match or input capture 4b overflow underflow 4 sources compare match or input capture 5a compare match or input capture 5b overflow underflow legend: : possible ?: not possible
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 299 of 1484 rej09b0103-0600 10.1.2 block diagram figure 10-1 shows a block diagram of the tpu. channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus ppg output trigger signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: legend: tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) channel 2 common channel 5 bus interface a/d converter conversion start signal figure 10-1 block diagram of tpu
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 300 of 1484 rej09b0103-0600 10.1.3 pin configuration table 10-2 summarizes the tpu pins. table 10-2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 301 of 1484 rej09b0103-0600 channel name symbol i/o function 3 input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin 4 input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 302 of 1484 rej09b0103-0600 10.1.4 register configuration table 10-3 summarizes the tpu registers. table 10-3 tpu registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ff10 timer mode register 0 tmdr0 r/w h'c0 h'ff11 timer i/o control register 0h tior0h r/w h'00 h'ff12 timer i/o control register 0l tior0l r/w h'00 h'ff13 timer interrupt enable register 0 tier0 r/w h'40 h'ff14 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ff15 timer counter 0 tcnt0 r/w h'0000 h'ff16 timer general register 0a tgr0a r/w h'ffff h'ff18 timer general register 0b tgr0b r/w h'ffff h'ff1a timer general register 0c tgr0c r/w h'ffff h'ff1c timer general register 0d tgr0d r/w h'ffff h'ff1e 1 timer control register 1 tcr1 r/w h'00 h'ff20 timer mode register 1 tmdr1 r/w h'c0 h'ff21 timer i/o control register 1 tior1 r/w h'00 h'ff22 timer interrupt enable register 1 tier1 r/w h'40 h'ff24 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ff25 timer counter 1 tcnt1 r/w h'0000 h'ff26 timer general register 1a tgr1a r/w h'ffff h'ff28 timer general register 1b tgr1b r/w h'ffff h'ff2a 2 timer control register 2 tcr2 r/w h'00 h'ff30 timer mode register 2 tmdr2 r/w h'c0 h'ff31 timer i/o control register 2 tior2 r/w h'00 h'ff32 timer interrupt enable register 2 tier2 r/w h'40 h'ff34 timer status register 2 tsr2 r/(w) * 2 h'c0 h'ff35 timer counter 2 tcnt2 r/w h'0000 h'ff36 timer general register 2a tgr2a r/w h'ffff h'ff38 timer general register 2b tgr2b r/w h'ffff h'ff3a
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 303 of 1484 rej09b0103-0600 channel name abbreviation r/w initial value address * 1 3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e 4 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a 5 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all timer start register tstr r/w h'00 h'feb0 timer synchro register tsyr r/w h'00 h'feb1 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 304 of 1484 rej09b0103-0600 10.2 register descriptions 10.2.1 timer control register (tcr) channel 0: tcr0 channel 3: tcr3 bit:76543210 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 channel 5: tcr5 bit:76543210 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w : ? r/w r/w r/w r/w r/w r/w r/w the tcr registers are 8-bit registers that control the tcnt channels. the tpu has six tcr registers, one for each of channels 0 to 5. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode. tcr register settings should be made only when tcnt operation is stopped.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 305 of 1484 rej09b0103-0600 bits 7 to 5?counter clear 2, 1, and 0 (cclr2, cclr1, cclr0): these bits select the tcnt counter clearing source. channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0, 3 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 10 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 channel bit 7 reserved * 3 bit 6 cclr1 bit 5 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 10 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 306 of 1484 rej09b0103-0600 bits 4 and 3?clock edge 1 and 0 (ckeg1, ckeg0): these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. bit 4 ckeg1 bit 3 ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 ? count at both edges note: internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. bits 2 to 0?time prescaler 2, 1, and 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 10-4 shows the clock sources that can be set for each channel. table 10-4 tpu clock sources internal clock external clock channel /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd overflow/ underflow on another channel 0 1 2 3 4 5 legend: : setting blank: no setting
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 307 of 1484 rej09b0103-0600 channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on /256 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on /1024 note: this setting is ignored when channel 2 is in phase counting mode.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 308 of 1484 rej09b0103-0600 channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on /1024 1 0 internal clock: counts on /256 1 internal clock: counts on /4096 channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 4 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /1024 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 5 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /256 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 309 of 1484 rej09b0103-0600 10.2.2 timer mode register (tmdr) channel 0: tmdr0 channel 3: tmdr3 bit:76543210 ? ? bfb bfa md3 md2 md1 md0 initial value:11000000 r/w : ? ? r/w r/w r/w r/w r/w r/w channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 channel 5: tmdr5 bit:76543210 ????md3md2md1md0 initial value:11000000 r/w : ? ? ? ? r/w r/w r/w r/w the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has six tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode. tmdr register settings should be made only when tcnt operation is stopped. bits 7 and 6?reserved: these bits are always read as 1 and cannot be modified. bit 5?buffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd used together for buffer operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 310 of 1484 rej09b0103-0600 bit 4?buffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc used together for buffer operation bits 3 to 0?modes 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation (initial value) 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** ? * : don?t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 311 of 1484 rej09b0103-0600 10.2.3 timer i/o control register (tior) channel 0: tior0h channel 1: tior1 channel 2: tior2 channel 3: tior3h channel 4: tior4 channel 5: tior5 bit:76543210 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w channel 0: tior0l channel 3: tior3l bit:76543210 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. the tior registers are 8-bit registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. the tior registers are initialized to h'00 by a reset, and in hardware standby mode. care is required since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 312 of 1484 rej09b0103-0600 bits 7 to 4? i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): bits iob3 to iob0 specify the function of tgrb. bits iod3 to iod0 specify the function of tgrd. channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 0 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0b is output compare register initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb0 pin input capture at both edges 1 ** tgr0b is input capture register capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : don?t care note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 313 of 1484 rej09b0103-0600 channel bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 description 0 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0d is output compare register * 2 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocd0 pin input capture at both edges 1 ** tgr0d is input capture register * 2 capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : don?t care notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 314 of 1484 rej09b0103-0600 channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 1 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr1b is output compare register initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb1 pin input capture at both edges 1 ** tgr1b is input capture register capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/ input capture * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 315 of 1484 rej09b0103-0600 channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 2 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 100 tgr2b is output compare register output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2b is input capture register capture input source is tiocb2 pin input capture at both edges * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 316 of 1484 rej09b0103-0600 channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 3 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 tgr3b is output compare register initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr3b is input capture register capture input source is tiocb3 pin input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don?t care note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 317 of 1484 rej09b0103-0600 channel bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 description 3 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 tgr3d is output compare register * 2 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 100 0 input capture at rising edge 1 input capture at falling edge 1 * tgr3d is input capture register * 2 capture input source is tiocd3 pin input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don?t care notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 318 of 1484 rej09b0103-0600 channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 4 0 0 0 0 output disabled (initial value) 1 0 output at compare match 10 initial output is 0 output 1 output at compare match 1 tgr4b is output compare register toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 10 initial output is 1 output 1 output at compare match 1 toggle output at compare match 100 0 input capture at rising edge 1 input capture at falling edge 1 * tgr4b is input capture register capture input source is tiocb4 pin input capture at both edges 1 ** capture input source is tgr3c compare match/ input capture input capture at generation of tgr3c compare match/ input capture * : don?t care channel bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 5 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 tgr5b is output compare register initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 10 initial output is 1 output 1 output at compare match 1 toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5b is input capture register capture input source is tiocb5 pin input capture at both edges * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 319 of 1484 rej09b0103-0600 bits 3 to 0? i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 0 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0a is output compare register initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr0a is input capture register capture input source is tioca0 pin input capture at both edges 1 ** capture input source is channel 1/ count clock input capture at tcnt1 count-up/count-down * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 320 of 1484 rej09b0103-0600 channel bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 description 0 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0c is output compare register * 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocc0 pin input capture at both edges 1 ** tgr0c is input capture register * 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * : don?t care note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 321 of 1484 rej09b0103-0600 channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 1 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr1a is output compare register initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca1 pin input capture at both edges 1 ** tgr1a is input capture register capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/input capture * : don?t care channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 2 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr2a is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2a is input capture register capture input source is tioca2 pin input capture at both edges * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 322 of 1484 rej09b0103-0600 channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 3 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3a is output compare register initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca3 pin input capture at both edges 1 ** tgr3a is input capture register capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 323 of 1484 rej09b0103-0600 channel bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 description 3 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3c is output compare register * 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocc3 pin input capture at both edges 1 ** tgr3c is input capture register * 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don?t care note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 324 of 1484 rej09b0103-0600 channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 4 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr4a is output compare register initial output is 1 output toggle output at compare match 100 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca4 pin input capture at both edges 1 ** tgr4a is input capture register capture input source is tgr3a compare match/ input capture input capture at generation of tgr3a compare match/ input capture * : don?t care channel bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 5 0 0 0 0 output disabled (initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr5a is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5a is input capture register capture input source is tioca5 pin input capture at both edges * : don?t care
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 325 of 1484 rej09b0103-0600 10.2.4 timer interrupt enable register (tier) channel 0: tier0 channel 3: tier3 bit:76543210 ttge ? ? tciev tgied tgiec tgieb tgiea initial value:01000000 r/w : r/w ? ? r/w r/w r/w r/w r/w channel 1: tier1 channel 2: tier2 channel 4: tier4 channel 5: tier5 bit:76543210 ttge ? tcieu tciev ? ? tgieb tgiea initial value:01000000 r/w : r/w ? r/w r/w ? ? r/w r/w the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 326 of 1484 rej09b0103-0600 bit 7?a/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by tgra input capture/compare match. bit 7 ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled bit 6?reserved: this bit is always read as 1 and cannot be modified. bit 5?underflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled bit 4?overflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. bit 4 tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3?tgr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 327 of 1484 rej09b0103-0600 bit 2?tgr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1?tgr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. bit 1 tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled bit 0?tgr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. bit 0 tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 328 of 1484 rej09b0103-0600 10.2.5 timer status register (tsr) channel 0: tsr0 channel 3: tsr3 bit:76543210 ? ? ? tcfv tgfd tgfc tgfb tgfa initial value:11000000 r/w : ? ? ? r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * can only be written with 0 for flag clearing. channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 channel 5: tsr5 bit:76543210 tcfd ? tcfu tcfv ? ? tgfb tgfa initial value:11000000 r/w : r ? r/(w) * r/(w) * ??r/(w) * r/(w) * note: * can only be written with 0 for flag clearing. the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 329 of 1484 rej09b0103-0600 bit 7?count direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bit 6?reserved: this bit is always read as 1 and cannot be modified. bit 5?underflow flag (tcfu): status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcfu description 0 [clearing condition] (initial value) ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4?overflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4 tcfv description 0 [clearing condition] (initial value) ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000 )
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 330 of 1484 rej09b0103-0600 bit 3?input capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgfd description 0 [clearing conditions] (initial value) ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register bit 2?input capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgfc description 0 [clearing conditions] (initial value) ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 331 of 1484 rej09b0103-0600 bit 1?input capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1 tgfb description 0 [clearing conditions] (initial value) ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register bit 0?input capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0 tgfa description 0 [clearing conditions] (initial value) ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 332 of 1484 rej09b0103-0600 10.2.6 timer counter (tcnt) channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter * ) channel 2: tcnt2 (up/down-counter * ) channel 3: tcnt3 (up-counter) channel 4: tcnt4 (up/down-counter * ) channel 5: tcnt5 (up/down-counter * ) bit :1514131211109876543210 initial value:0000000000000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up- counters. the tcnt registers are 16-bit counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 333 of 1484 rej09b0103-0600 10.2.7 timer general register (tgr) bit :1514131211109876543210 initial value:1111111111111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers * . the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgra?tgrc and tgrb?tgrd.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 334 of 1484 rej09b0103-0600 10.2.8 timer start register (tstr) bit:76543210 ? ? cst5 cst4 cst3 cst2 cst1 cst0 initial value:00000000 r/w : ? ? r/w r/w r/w r/w r/w r/w tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. tstr is initialized to h'00 by a reset, and in hardware standby mode. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bits 7 and 6?reserved: should always be written with 0. bits 5 to 0?counter start 5 to 0 (cst5 to cst0): these bits select operation or stoppage for tcnt. bit n cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation n = 5 to 0 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 335 of 1484 rej09b0103-0600 10.2.9 timer synchro register (tsyr) bit:76543210 ? ? sync5 sync4 sync3 sync2 sync1 sync0 initial value:00000000 r/w : ? ? r/w r/w r/w r/w r/w r/w tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 and 6?reserved: should always be written with 0. bits 5 to 0?timer synchro 5 to 0 (sync5 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels * 1 , and synchronous clearing through counter clearing on another channel * 2 are possible. notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. bit n syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible n = 5 to 0
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 336 of 1484 rej09b0103-0600 10.2.10 module stop control register a (mstpcra) bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa5 bit in mstpcra is set to 1, tpu operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 5?module stop (mstpa5): specifies the tpu module stop mode. bit 5 mstpa5 description 0 tpu module stop mode cleared 1 tpu module stop mode set (initial value)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 337 of 1484 rej09b0103-0600 10.3 interface to bus master 10.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 10-2. bus interface h internal data bus l bus master module data bus tcnth tcntl figure 10-2 16-bit register access operation [bus master ? ? ? ? tcnt (16 bits)] 10.3.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 338 of 1484 rej09b0103-0600 examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. bus interface h internal data bus l module data bus tcr bus master figure 10-3 8-bit register access operation [bus master ? ? ? ? tcr (upper 8 bits)] bus interface h internal data bus l module data bus tmdr bus master figure 10-4 8-bit register access operation [bus master ? ? ? ? tmdr (lower 8 bits)] bus interface h internal data bus l module data bus tcr tmdr bus master figure 10-5 8-bit register access operation [bus master ? ? ? ? tcr and tmdr (16 bits)]
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 339 of 1484 rej09b0103-0600 10.4 operation 10.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. synchronous operation: when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. buffer operation ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. ? when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. cascaded operation: the channel 1 counter (tcnt1), channel 2 counter (tcnt2), channel 4 counter (tcnt4), and channel 5 counter (tcnt5) can be connected together to operate as a 32- bit counter. pwm mode: in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. phase counting mode: in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this can be used for two-phase encoder pulse input.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 340 of 1484 rej09b0103-0600 10.4.2 basic functions counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. ? example of count operation setting procedure figure 10-6 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count operation [1] [2] [4] [3] [5] free-running counter start count operation [5] [1] [2] [3] [4] [5] select output compare register select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 in tcr. designate the tgr selected in [2] as an output compare register by means of tior. set the periodic counter cycle in the tgr selected in [2]. set the cst bit in tstr to 1 to start the counter operation. figure 10-6 example of counter operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 341 of 1484 rej09b0103-0600 ? free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 10-7 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 10-7 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 342 of 1484 rej09b0103-0600 figure 10-8 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 10-8 periodic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. ? example of setting procedure for waveform output by compare match figure 10-9 shows an example of the setting procedure for waveform output by compare match select waveform output mode output selection set output timing start count operation [1] [2] [3] [1] select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin until the first compare match occurs. [2] set the timing for compare match generation in tgr. [3] set the cst bit in tstr to 1 to start the count operation. figure 10-9 example of setting procedure for waveform output by compare match
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 343 of 1484 rej09b0103-0600 ? examples of waveform output operation figure 10-10 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 10-10 example of 0 output/1 output operation figure 10-11 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 10-11 example of toggle output operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 344 of 1484 rej09b0103-0600 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channel?s counter input clock or compare match signal as the input capture source. note: when another channel?s counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if /1 is selected. ? example of input capture operation setting procedure figure 10-12 shows an example of the input capture operation setting procedure. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 10-12 example of input capture operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 345 of 1484 rej09b0103-0600 ? example of input capture operation figure 10-13 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin i nput capture input edge, fa lling edge has been selected as the tiocb pin i nput capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 10-13 example of input capture operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 346 of 1484 rej09b0103-0600 10.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 10-14 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting [1] [2] synchronous clearing select counter clearing source [3] start count [5] set synchronous counter clearing [4] start count [5] clearing sourcegeneration channel? no yes [1] [2] [3] [4] [5] set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. use bits cclr2 to cclr0 in tcr to specify tcnt clearing by input capture/output compare, etc. use bits cclr2 to cclr0 in tcr to designate synchronous clearing for the counter clearing source. set to 1 the cst bits in tstr for the relevant channels, to start the count operation. figure 10-14 example of synchronous operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 347 of 1484 rej09b0103-0600 example of synchronous operation: figure 10-15 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchronous clearing by tgr0b compare match, is performed for channel 0 to 2 tcnt counters, and the data set in tgr0b is used as the pwm cycle. for details of pwm modes, see section 10.4.6, pwm modes. tcnt0 to tcnt2 values h0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 10-15 example of synchronous operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 348 of 1484 rej09b0103-0600 10.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10-5 shows the register combinations used in buffer operation. table 10-5 register combinations in buffer operation channel timer general register buffer register 0tgr0a tgr0c tgr0b tgr0d 3tgr3a tgr3c tgr3b tgr3d ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10-16. buffer register timer general register tcnt comparator compare match signal figure 10-16 compare match buffer operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 349 of 1484 rej09b0103-0600 ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10-17. buffer register timer general register tcnt input capture signal figure 10-17 input capture buffer operation example of buffer operation setting procedure: figure 10-18 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count [1] [2] [3] [1] designate tgr as an input capture register or output compare register by means of tior. [2] designate tgr for buffer operation with bits bfa and bfb in tmdr. [3] set the cst bit in tstr to 1 to start the count operation. figure 10-18 example of buffer operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 350 of 1484 rej09b0103-0600 examples of buffer operation ? when tgr is an output compare register figure 10-19 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 10.4.6, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 10-19 example of buffer operation (1)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 351 of 1484 rej09b0103-0600 ? when tgr is an input capture register figure 10-20 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and fa lling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 10-20 example of buffer operation (2)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 352 of 1484 rej09b0103-0600 10.4.5 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt2 (tcnt5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 10-6 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 10-6 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt1 tcnt2 channels 4 and 5 tcnt4 tcnt5 example of cascaded operation setting procedure: figure 10-21 shows an example of the setting procedure for cascaded operation. set cascading cascaded operation start count [1] [2] [1] set bits tpsc2 to tpsc0 in the channel 1 (channel 4) tcr to b'111 to select tcnt2 (tcnt5) overflow/underflow counting. [2] set the cst bit in tstr for the upper and lower channel to 1 to start the count operation. figure 10-21 cascaded operation setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 353 of 1484 rej09b0103-0600 examples of cascaded operation: figure 10-22 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, tgr1a, and tgr2a have been designated as input capture registers, and tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgr1a, and the lower 16 bits to tgr2a. tcnt2 clock tcnt2 h'ffff h'0000 h'0001 tioca1, tioca2 tgr1a h'03a2 tgr2a h'0000 tcnt1 clock tcnt1 h'03a1 h'03a2 figure 10-22 example of cascaded operation (1) figure 10-23 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, and phase counting mode has been designated for channel 2. tcnt1 is incremented by tcnt2 overflow and decremented by tcnt2 underflow. tclkc tcnt2 fffd tcnt1 0001 tclkd fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 10-23 example of cascaded operation (2)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 354 of 1484 rej09b0103-0600 10.4.6 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob3 to iob0 and iod3 to iod0 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 10-7.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 355 of 1484 rej09b0103-0600 table 10-7 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioca0 tioca0 tgr0b tiocb0 tgr0c tiocc0 tiocc0 tgr0d tiocd0 1 tgr1a tioca1 tioca1 tgr1b tiocb1 2 tgr2a tioca2 tioca2 tgr2b tiocb2 3 tgr3a tioca3 tioca3 tgr3b tiocb3 tgr3c tiocc3 tiocc3 tgr3d tiocd3 4 tgr4a tioca4 tioca4 tgr4b tiocb4 5 tgr5a tioca5 tioca5 tgr5b tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 356 of 1484 rej09b0103-0600 example of pwm mode setting procedure: figure 10-24 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level [1] [2] [3] set tgr [4] set pwm mode [5] start count [6] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr2 to cclr0 in tcr to select the tgr to be used as the tcnt clearing source. [3] use tior to designate the tgr as an output compare register, and select the initial value and output value. [4] set the cycle in the tgr selected in [2], and set the duty in the other the tgr. [5] select the pwm mode with bits md3 to md0 in tmdr. [6] set the cst bit in tstr to 1 to start the count operation. figure 10-24 example of pwm mode setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 357 of 1484 rej09b0103-0600 examples of pwm mode operation: figure 10-25 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in tgrb registers as the duty. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10-25 example of pwm mode operation (1)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 358 of 1484 rej09b0103-0600 figure 10-26 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgr0a to tgr0d, tgr1a), to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgrs as the duty. tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 10-26 example of pwm mode operation (2)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 359 of 1484 rej09b0103-0600 figure 10-27 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 10-27 example of pwm mode operation (3)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 360 of 1484 rej09b0103-0600 10.4.7 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag provides an indication of whether tcnt is counting up or down. table 10-8 shows the correspondence between external clock pins and channels. table 10-8 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 10-28 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count [1] [2] [1] select phase counting mode with bits md3 to md0 in tmdr. [2] set the cst bit in tstr to 1 to start the count operation. figure 10-28 example of phase counting mode setting procedure
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 361 of 1484 rej09b0103-0600 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. ? phase counting mode 1 figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10-29 example of phase counting mode 1 operation table 10-9 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 362 of 1484 rej09b0103-0600 ? phase counting mode 2 figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10-30 example of phase counting mode 2 operation table 10-10 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level don?t care low level don?t care high level up-count high level don?t care low level don?t care high level don?t care low level down-count legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 363 of 1484 rej09b0103-0600 ? phase counting mode 3 figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) down-count figure 10-31 example of phase counting mode 3 operation table 10-11 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level don?t care low level don?t care high level up-count high level down-count low level don?t care high level don?t care low level don?t care legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 364 of 1484 rej09b0103-0600 ? phase counting mode 4 figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the tcnt up/down-count conditions. time tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) up-count down-count tcnt value figure 10-32 example of phase counting mode 4 operation table 10-12 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level don?t care high level high level down-count low level high level don?t care low level legend: : rising edge : falling edge
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 365 of 1484 rej09b0103-0600 phase counting mode application example: figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgr0c compare match; tgr0a and tgr0c are used for the compare match function, and are set with the speed control period and position control period. tgr0b is used for input capture, with tgr0b and tgr0d operating in buffer mode. the channel 1 counter input clock is designated as the tgr0b input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. tgr1a and tgr1b for channel 1 are designated for input capture, channel 0 tgr0a and tgr0c compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. this procedure enables accurate position/speed detection to be achieved.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 366 of 1484 rej09b0103-0600 tcnt1 tcnt0 channel 1 tgr1a (speed period capture) tgr0a (speed control period) tgr1b (position period capture) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) channel 0 tclka tclkb edge detection circuit + ? + ? figure 10-33 phase counting mode application example
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 367 of 1484 rej09b0103-0600 10.5 interrupts 10.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 10-13 lists the tpu interrupt sources.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 368 of 1484 rej09b0103-0600 table 10-13 tpu interrupts channel interrupt source description dtc activation priority 0 tgi0a tgr0a input capture/compare match possible high tgi0b tgr0b input capture/compare match possible tgi0c tgr0c input capture/compare match possible tgi0d tgr0d input capture/compare match possible tci0v tcnt0 overflow not possible 1 tgi1a tgr1a input capture/compare match possible tgi1b tgr1b input capture/compare match possible tci1v tcnt1 overflow not possible tci1u tcnt1 underflow not possible 2 tgi2a tgr2a input capture/compare match possible tgi2b tgr2b input capture/compare match possible tci2v tcnt2 overflow not possible tci2u tcnt2 underflow not possible 3 tgi3a tgr3a input capture/compare match possible tgi3b tgr3b input capture/compare match possible tgi3c tgr3c input capture/compare match possible tgi3d tgr3d input capture/compare match possible tci3v tcnt3 overflow not possible 4 tgi4a tgr4a input capture/compare match possible tgi4b tgr4b input capture/compare match possible tci4v tcnt4 overflow not possible tci4u tcnt4 underflow not possible 5 tgi5a tgr5a input capture/compare match possible tgi5b tgr5b input capture/compare match possible tci5v tcnt5 overflow not possible tci5u tcnt5 underflow not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 369 of 1484 rej09b0103-0600 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 dtc activation note: the dtc is not implemented in the h8s/2635 and h8s/2634. dtc activation: the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 8, data transfer controller (dtc). a total of 16 tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.5.3 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 370 of 1484 rej09b0103-0600 10.6 operation timing 10.6.1 input/output timing tcnt count timing: figure 10-34 shows tcnt count timing in internal clock operati on, and figure 10-35 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n ? 1 n n + 1 n + 2 falling edge rising edge figure 10-34 count timing in internal clock operation tcnt tcnt input clock external clock n ? 1 n n + 1 n + 2 rising edge falling edge falling edge figure 10-35 count timing in external clock operation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 371 of 1484 rej09b0103-0600 output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 10-36 shows output compare output timing. tgr tcnt tcnt input clock n n n + 1 compare match signal tioc pin figure 10-36 output compare output timing input capture signal timing: figure 10-37 shows input capture signal t iming. tcnt input capture input n n + 1 n + 2 n n + 2 tgr input capture signal figure 10-37 input capture input signal timing
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 372 of 1484 rej09b0103-0600 timing for counter clearing by compare match/input capture: figure 10-38 shows the timing when c ounter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by i nput capture occurrence is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 10-38 counter clear timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n figure 10-39 counter clear timing (input capture)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 373 of 1484 rej09b0103-0600 buffer operation timing: figures 10-40 and 10-41 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n n n + 1 figure 10-40 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n + 1 n n n + 1 figure 10-41 buffer operation timing (input capture)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 374 of 1484 rej09b0103-0600 10.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10-42 shows the timing for setting of the tgf flag in tsr by compare match occurrence, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n + 1 compare match signal tgf flag tgi interrupt figure 10-42 tgi interrupt timing (compare match)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 375 of 1484 rej09b0103-0600 tgf flag setting timing in case of input capture: figure 10-43 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and tgi interrupt request signal t iming. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 10-43 tgi interrupt timing (input capture)
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 376 of 1484 rej09b0103-0600 tcfv flag/tcfu flag setting timing: figure 10-44 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and tciv interrupt request signal timing. figure 10-45 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 10-44 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 10-45 tciu interrupt setting timing
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 377 of 1484 rej09b0103-0600 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc * is activated, the flag is cleared automatically. figure 10-46 shows the timing for status flag clearing by the cpu, and figure 10-47 shows the timing for status flag clearing by the dtc. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. status flag write signal a ddress tsr address interrupt request signal tsr write cycle t 1 t 2 figure 10-46 timing for status flag clearing by cpu interrupt request signal status flag a ddress source address dtc read cycle t 1 t 2 destination address t 1 t 2 dtc write cycle figure 10-47 timing for status flag clearing by dtc activation
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 378 of 1484 rej09b0103-0600 10.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. input clock restrictions: the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10-48 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap: pulse width: 1.5 states or more 2.5 states or more figure 10-48 phase difference, overlap, and pulse width in phase counting mode caution on period setting: when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) where f : counter frequency : operating frequency n: tgr set value
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 379 of 1484 rej09b0103-0600 contention between tcnt write and clear operations: if the counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10-49 shows the timing in this case. counter clear signal write signal a ddress tcnt address tcnt tcnt write cycle t 1 t 2 n h'0000 figure 10-49 contention between tcnt write and clear operations
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 380 of 1484 rej09b0103-0600 contention between tcnt write and increment operations: if incrementing occurs in the t 2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10-50 shows the timing in this case. tcnt input clock write signal a ddress tcnt address tcnt tcnt write cycle t 1 t 2 n m tcnt write data figure 10-50 contention between tcnt write and increment operations
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 381 of 1484 rej09b0103-0600 contention between tgr write and compare match: if a compare match occurs in the t 2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the same value as before is written. figure 10-51 shows the timing in this case. compare match signal write signal a ddress tgr address tcnt tgr write cycle t 1 t 2 n m tgr write data tgr n n + 1 prohibited figure 10-51 contention between tgr write and compare match
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 382 of 1484 rej09b0103-0600 contention between buffer register write and compare match: if a compare match occurs in the t 2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the data prior to the write. figure 10-52 shows the timing in this case. compare match signal write signal a ddress buffer register address buffer register tgr write cycle t 1 t 2 n tgr n m buffer register write data figure 10-52 contention between buffer register write and compare match
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 383 of 1484 rej09b0103-0600 contention between tgr read and input capture: if the input capture signal is generated in the t 1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 10-53 shows the timing in this case. input capture signal read signal a ddress tgr address tgr tgr read cycle t 1 t 2 m internal data bus x m figure 10-53 contention between tgr read and input capture
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 384 of 1484 rej09b0103-0600 contention between tgr write and input capture: if the input capture signal is generated in the t 2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10-54 shows the timing in this case. input capture signal write signal a ddress tcnt tgr write cycle t 1 t 2 m tgr m tgr address figure 10-54 contention between tgr write and input capture
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 385 of 1484 rej09b0103-0600 contention between buffer register write and input capture: if the input capture signal is generated in the t 2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10-55 shows the timing in this case. input capture signal write signal a ddress tcnt buffer register write cycle t 1 t 2 n tgr n m m buffer register buffer register address figure 10-55 contention between buffer register write and input capture
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 386 of 1484 rej09b0103-0600 contention between overflow/underflow and counter clearing: if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 10-56 shows the operation timing when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt input clock tcnt tgf prohibited tcfv h'ffff h'0000 figure 10-56 contention between overflow and counter clearing
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 387 of 1484 rej09b0103-0600 contention between tcnt write and overflow/underflow: if there is an up-count or down- count in the t 2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 10-57 shows the operation timing when there is contention between tcnt write and overflow. write signal a ddress tcnt address tcnt tcnt write cycle t 1 t 2 h'ffff m tcnt write data tcfv flag prohibited figure 10-57 contention between tcnt write and overflow multiplexing of i/o pins: in the chip, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. interrupts and module stop mode: if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc * activation source. interrupts should therefore be disabled before entering module stop mode. note: * the dtc is not implemented in the h8s/2635 and h8s/2634.
section 10 16-bit timer pulse unit (tpu) rev. 6.00 feb 22, 2005 page 388 of 1484 rej09b0103-0600
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 389 of 1484 rej09b0103-0600 section 11 programmable pulse generator (ppg) note: the h8s/2635 group is not equipped with a ppg. 11.1 overview the chip has an on-chip programmable pulse generator (ppg) that provides pulse outputs by using the 16-bit timer-pulse unit (tpu) as a time base. the ppg pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently. 11.1.1 features ppg features are listed below. ? 8-bit output data ? maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis ? two output groups ? output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit outputs ? selectable output trigger signals ? output trigger signals can be selected for each group from the compare match signals of four tpu channels ? non-overlap mode ? a non-overlap margin can be provided between pulse outputs ? can operate together with the data transfer controller (dtc) ? the compare match signals selected as output trigger signals can activate the dtc for sequential output of data without cpu intervention ? settable inverted output ? inverted data can be output for each group ? module stop mode can be set ? as the initial setting, ppg operation is halted. register access is enabled by exiting module stop mode
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 390 of 1484 rej09b0103-0600 11.1.2 block diagram figure 11-1 shows a block diagram of the ppg. compare match signals po15 po14 po13 po12 po11 po10 po9 po8 legend: ppg output mode register ppg output control register next data enable register h next data enable register l next data register h next data register l output data register h output data register l internal data bus pmr: pcr: nderh: nderl: ndrh: ndrl: podrh: podrl: pulse output pins, group 3 pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 podrh podrl ndrh ndrl control logic nderh pmr nderl pcr figure 11-1 block diagram of ppg
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 391 of 1484 rej09b0103-0600 11.1.3 pin configuration table 11-1 summarizes the ppg pins. table 11-1 ppg pins name symbol i/o function pulse output 8 po8 output group 2 pulse output pulse output 9 po9 output pulse output 10 po10 output pulse output 11 po11 output pulse output 12 po12 output group 3 pulse output pulse output 13 po13 output pulse output 14 po14 output pulse output 15 po15 output
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 392 of 1484 rej09b0103-0600 11.1.4 registers table 11-2 summarizes the ppg registers. table 11-2 ppg registers name abbreviation r/w initial value address * 1 ppg output control register pcr r/w h'ff h'fe26 ppg output mode register pmr r/w h'f0 h'fe27 next data enable register h nderh r/w h'00 h'fe28 next data enable register l * 4 nderl r/w h'00 h'fe29 output data register h podrh r/(w) * 2 h'00 h'fe2a output data register l * 4 podrl r/(w) * 2 h'00 h'fe2b next data register h ndrh r/w h'00 h'fe2c * 3 h'fe2e next data register l * 4 ndrl r/w h'00 h'fe2d * 3 h'fe2f port 1 data direction register p1ddr w h'00 h'fe30 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. bits used for pulse output cannot be written to. 3. when the same output trigger is selected for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fe2c. when the output triggers are different, the ndrh address is h'fe2e for group 2 and h'fe2c for group 3. similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the pcr setting, the ndrl address is h'fe2d. when the output triggers are different, the ndrl address is h'fe2f for group 0 and h'fe2d for group 1. 4. the chip has no pins corresponding to pulse output groups 0 and 1.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 393 of 1484 rej09b0103-0600 11.2 register descriptions 11.2.1 next data enable registers h and l (nderh, nderl) nderh bit:76543210 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w nderl bit:76543210 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w nderh and nderl are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. if a bit is enabled for pulse output by nderh or nderl, the ndr value is automatically transferred to the corresponding podr bit when the tpu compare match event specified by pcr occurs, updating the output value. if pulse output is disabled, the bit value is not transferred from ndr to podr and the output value does not change. nderh and nderl are each initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. nderh bits 7 to 0?next data enable 15 to 8 (nder15 to nder8): these bits enable or disable pulse output on a bit-by-bit basis. bits 7 to 0 nder15 to nder8 description 0 pulse outputs po15 to po8 are disabled (ndr15 to ndr8 are not transferred to pod15 to pod8) (initial value) 1 pulse outputs po15 to po8 are enabled (ndr15 to ndr8 are transferred to pod15 to pod8)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 394 of 1484 rej09b0103-0600 nderl bits 7 to 0?next data enable 7 to 0 (nder7 to nder0): these bits enable or disable pulse output on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 pulse outputs po7 to po0 are disabled (ndr7 to ndr0 are not transferred to pod7 to pod0) (initial value) 1 pulse outputs po7 to po0 are enabled (ndr7 to ndr0 are transferred to pod7 to pod0) 11.2.2 output data registers h and l (podrh, podrl) podrh bit:76543210 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 initial value:00000000 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * podrl bit:76543210 pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 initial value:00000000 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * a bit that has been set for pulse output by nder is read-only. podrh and podrl are 8-bit readable/writable registers that store output data for use in pulse output. however, the chip has no pins corresponding to podrl.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 395 of 1484 rej09b0103-0600 11.2.3 next data registers h and l (ndrh, ndrl) ndrh and ndrl are 8-bit readable/writable registers that store the next data for pulse output. during pulse output, the contents of ndrh and ndrl are transferred to the corresponding bits in podrh and podrl when the tpu compare match event specified by pcr occurs. the ndrh and ndrl addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. for details see section 11.2.4, notes on ndr access. ndrh and ndrl are each initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. 11.2.4 notes on ndr access the ndrh and ndrl addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. same trigger for pulse output groups: if pulse output groups 2 and 3 are triggered by the same compare match event, the ndrh address is h'fe2c. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'fe2e consists entirely of reserved bits that cannot be modified and are always read as 1. address h'fe2c bit:76543210 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w address h'fe2e bit:76543210 ???????? initial value:11111111 r/w:???????? if pulse output groups 0 and 1 are triggered by the same compare match event, the ndrl address is h'fe2d. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'fe2f consists entirely of reserved bits that cannot be modified and are always read as 1. however, the chip has no output pins corresponding to pulse output groups 0 and 1.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 396 of 1484 rej09b0103-0600 address h'fe2d bit:76543210 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w address h'fe2f bit:76543210 ???????? initial value:11111111 r/w:???????? different triggers for pulse output groups: if pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in ndrh (group 3) is h'fe2c and the address of the lower 4 bits (group 2) is h'fe2e. bits 3 to 0 of address h'fe2c and bits 7 to 4 of address h'fe2e are reserved bits that cannot be modified and are always read as 1. address h'fe2c bit:76543210 ndr15 ndr14 ndr13 ndr12 ? ? ? ? initial value:00001111 r/w : r/w r/w r/w r/w ? ? ? ? address h'fe2e bit:76543210 ? ? ? ? ndr11 ndr10 ndr9 ndr8 initial value:11110000 r/w : ? ? ? ? r/w r/w r/w r/w if pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in ndrl (group 1) is h'fe2d and the address of the lower 4 bits (group 0) is h'fe2f. bits 3 to 0 of address h'fe2d and bits 7 to 4 of address h'fe2f are reserved bits that cannot be modified and are always read as 1. however, the chip has no output pins corresponding to pulse output groups 0 and 1.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 397 of 1484 rej09b0103-0600 address h'fe2d bit:76543210 ndr7 ndr6 ndr5 ndr4 ? ? ? ? initial value:00001111 r/w : r/w r/w r/w r/w ? ? ? ? address h'fe2f bit:76543210 ? ? ? ? ndr3 ndr2 ndr1 ndr0 initial value:11110000 r/w : ? ? ? ? r/w r/w r/w r/w 11.2.5 ppg output control register (pcr) bit:76543210 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcr is an 8-bit readable/writable register that selects output trigger signals for ppg outputs on a group-by-group basis. pcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?group 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match that triggers pulse output group 3 (pins po15 to po12). description bit 7 g3cms1 bit 6 g3cms0 output trigger for pulse output group 3 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 398 of 1484 rej09b0103-0600 bits 5 and 4?group 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match that triggers pulse output group 2 (pins po11 to po8). description bit 5 g2cms1 bit 4 g2cms0 output trigger for pulse output group 2 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value) bits 3 and 2?group 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match that triggers pulse output group 1 (pins po7 to po4). however, the chip has no output pins corresponding to pulse output group 1. description bit 3 g1cms1 bit 2 g1cms0 output trigger for pulse output group 1 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value) bits 1 and 0?group 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match that triggers pulse output group 0 (pins po3 to po0). however, the chip has no output pins corresponding to pulse output group 0. description bit 1 g0cms1 bit 0 g0cms0 output trigger for pulse output group 0 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 399 of 1484 rej09b0103-0600 11.2.6 ppg output mode register (pmr) bit:76543210 g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov initial value:11110000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pmr is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. the output trigger period of a non-overlapping operation ppg output waveform is set in tgrb and the non-overlap margin is set in tgra. the output values change at compare match a and b. for details, see section 11.3.4, non-overlapping pulse output. pmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?group 3 inversion (g3inv): selects direct output or inverted output for pulse output group 3 (pins po15 to po12). bit 7 g3inv description 0 inverted output for pulse output group 3 (low-level output at pin for a 1 in podrh) 1 direct output for pulse output group 3 (high-level output at pin for a 1 in podrh) (initial value ) bit 6?group 2 inversion (g2inv): selects direct output or inverted output for pulse output group 2 (pins po11 to po8). bit 6 g2inv description 0 inverted output for pulse output group 2 (low-level output at pin for a 1 in podrh) 1 direct output for pulse output group 2 (high-level output at pin for a 1 in podrh) (initial value )
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 400 of 1484 rej09b0103-0600 bit 5?group 1 inversion (g1inv): selects direct output or inverted output for pulse output group 1 (pins po7 to po4). however, the chip has no pins corresponding to pulse output group 1. bit 5 g1inv description 0 inverted output for pulse output group 1 (low-level output at pin for a 1 in podrl) 1 direct output for pulse output group 1 (high-level output at pin for a 1 in podrl) (initial value) bit 4?group 0 inversion (g0inv): selects direct output or inverted output for pulse output group 0 (pins po3 to po0). however, the chip has no pins corresponding to pulse output group 0. bit 4 g0inv description 0 inverted output for pulse output group 0 (low-level output at pin for a 1 in podrl) 1 direct output for pulse output group 0 (high-level output at pin for a 1 in podrl) (initial value) bit 3?group 3 non-overlap (g3nov): selects normal or non-overlapping operation for pulse output group 3 (pins po15 to po12). bit 3 g3nov description 0 normal operation in pulse output group 3 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match a or b in the selected tpu channel) bit 2?group 2 non-overlap (g2nov): selects normal or non-overlapping operation for pulse output group 2 (pins po11 to po8). bit 2 g2nov description 0 normal operation in pulse output group 2 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match a or b in the selected tpu channel)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 401 of 1484 rej09b0103-0600 bit 1?group 1 non-overlap (g1nov): selects normal or non-overlapping operation for pulse output group 1 (pins po7 to po4). however, the chip has no pins corresponding to pulse output group 1. bit 1 g1nov description 0 normal operation in pulse output group 1 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match a or b in the selected tpu channel) bit 0?group 0 non-overlap (g0nov): selects normal or non-overlapping operation for pulse output group 0 (pins po3 to po0). however, the chip has no pins corresponding to pulse output group 0. bit 0 g0nov description 0 normal operation in pulse output group 0 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match a or b in the selected tpu channel)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 402 of 1484 rej09b0103-0600 11.2.7 port 1 data direction register (p1ddr) bit:76543210 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value:00000000 r/w:wwwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. port 1 is multiplexed with pins po15 to po8. bits corresponding to pins used for ppg output must be set to 1. for further information about p1ddr, see section 9.2, port 1. 11.2.8 module stop control register a (mstpcra) bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is a 16-bit readable/writable register that performs module stop mode control. when the mstpa3 bit in mstpcra is set to 1, ppg operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 3?module stop (mstpa3): specifies the ppg module stop mode. bit 3 mstpa3 description 0 ppg module stop mode cleared 1 ppg module stop mode set (initial value)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 403 of 1484 rej09b0103-0600 11.3 operation 11.3.1 overview ppg pulse output is enabled when the corresponding bits in p1ddr and nder are set to 1. in this state the corresponding podr contents are output. when the compare match event specified by pcr occurs, the corresponding ndr bit contents are transferred to podr to update the output values. figure 11-2 illustrates the ppg output operation and table 11-3 summarizes the ppg operating conditions. output trigger signal pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd ddr figure 11-2 ppg output operation table 11-3 ppg operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 10 generic input port (but the podr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the podr bit) 1 ppg pulse output sequential output of data of up to 16 bits is possible by writing new output data to ndr before the next compare match. for details of non-overlapping operation, see section 11.3.4, non- overlapping pulse output.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 404 of 1484 rej09b0103-0600 11.3.2 output timing if pulse output is enabled, ndr contents are transferred to podr and output when the specified compare match event occurs. figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt n n + 1 tgra n compare match a signal ndrh mn podrh po8 to po15 n mn figure 11-3 timing of transfer and output of ndr contents (example)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 405 of 1484 rej09b0103-0600 11.3.3 normal pulse output sample setup procedure for normal pulse output: figure 11-4 shows a sample procedure for setting up normal pulse output. select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu setup port and ppg setup tpu setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior to make tgra an output compare register (with output disabled) [2] set the ppg output trigger period [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next output values in ndr. figure 11-4 setup procedure for normal pulse output (example)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 406 of 1484 rej09b0103-0600 example of normal pulse output (example of five-phase pulse output): figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. tcnt value tcnt tgra h'0000 ndrh 00 80 c0 40 60 20 30 10 18 08 88 podrh po15 po14 po13 po12 po11 time compare match c0 80 c0 80 40 60 20 30 10 18 08 88 80 c0 40 figure 11-5 normal pulse output example (five-phase pulse output) [1] set up the tpu channel to be used as the output trigger channel so that tgra is an output compare register and the counter will be cleared by compare match a. set the trigger period in tgra and set the tgiea bit in tier to 1 to enable the compare match a (tgia) interrupt. [2] write h'f8 in p1ddr and nderh, and set the g3cms1, g3cms0, g2cms1, and g2cms0 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. write output data h'80 in ndrh. [3] the timer counter in the tpu channel starts. when compare match a occurs, the ndrh contents are transferred to podrh and output. the tgia interrupt handling routine writes the next output data (h'c0) in ndrh. [4] five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing h'40, h'60, h'20, h'30. h'10, h'18, h'08, h'88... at successive tgia
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 407 of 1484 rej09b0103-0600 interrupts. if the dtc is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu. 11.3.4 non-overlapping pulse output sample setup procedure for non-overlapping pulse output: figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match? no yes tpu setup ppg setup tpu setup non-overlapping ppg output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior to make tgra and tgrb an output compare registers (with output disabled) [2] set the pulse output trigger period in tgrb and the non-overlap margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlap mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 11-6 setup procedure for non-overlapping pulse output (example)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 408 of 1484 rej09b0103-0600 example of non-overlapping pulse output (example of four-phase complementary non- overlapping output): figure 11-7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrh po15 po14 po13 po12 po11 po10 po9 po8 time non-overlap margin figure 11-7 non-overlapping pulse output example (four-phase complementary)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 409 of 1484 rej09b0103-0600 [1] set up the tpu channel to be used as the output trigger channel so that tgra and tgrb are output compare registers. set the trigger period in tgrb and the non-overlap margin in tgra, and set the counter to be cleared by compare match b. set the tgiea bit in tier to 1 to enable the tgia interrupt. [2] write h'ff in p1ddr and nderh, and set the g3cms1, g3cms0, g2cms1, and g2cms0 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. set the g3nov and g2nov bits in pmr to 1 to select non-overlapping output. write output data h'95 in ndrh. [3] the timer counter in the tpu channel starts. when a compare match with tgrb occurs, outputs change from 1 to 0. when a compare match with tgra occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in tgra). the tgia interrupt handling routine writes the next output data (h'65) in ndrh. [4] four-phase complementary non-overlapping pulse output can be obtained subsequently by writing h'59, h'56, h'95... at successive tgia interrupts. if the dtc is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu.
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 410 of 1484 rej09b0103-0600 11.3.5 inverted pulse output if the g3inv, g2inv, g1inv, and g0inv bits in pmr are cleared to 0, values that are the inverse of the podr contents can be output. figure 11-8 shows the outputs when g3inv and g2inv are cleared to 0, in addition to the settings of figure 11-7. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrl po15 po14 po13 po12 po11 po10 po9 po8 time figure 11-8 inverted pulse output (example)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 411 of 1484 rej09b0103-0600 11.3.6 pulse output triggered by input capture pulse output can be triggered by tpu input capture as well as by compare match. if tgra functions as an input capture register in the tpu channel selected by pcr, pulse output will be triggered by the input capture signal. figure 11-9 shows the timing of this output. n m n tioc pin input capture signal ndr podr mn po figure 11-9 pulse output triggered by input capture (example)
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 412 of 1484 rej09b0103-0600 11.4 usage notes operation of pulse output pins: pins po8 to po15 are also used for other peripheral functions such as the tpu. when output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. note, however, that data transfer from ndr bits to podr bits takes place, regardless of the usage of the pins. pin functions should be changed only under conditions in which the output trigger event will not occur. note on non-overlapping output: during non-overlapping operation, the transfer of ndr bit values to podr bits takes place as follows. ? ndr bits are always transferred to podr bits at compare match a. ? at compare match b, ndr bits are transferred only if their value is 0. bits are not transferred if their value is 1. figure 11-10 illustrates the non-overlapping pulse output operation. compare match a compare match b pulse output pin normal output/inverted output c podr qd nder q ndr qd internal data bus ddr figure 11-10 non-overlapping pulse output
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 413 of 1484 rej09b0103-0600 therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. the ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the tgia interrupt handling routine write the next data in ndr, or by having the tgia interrupt activate the dtc. note, however, that the next data must be written before the next compare match b occurs. figure 11-11 shows the timing of this operation. 0/1 output 0 output 0/1 output 0 output do not write to ndr here write to ndr here compare match a compare match b ndr podr do not write to ndr here write to ndr here write to ndr write to ndr figure 11-11 non-overlapping operation and ndr write timing
section 11 programmable pulse generator (ppg) rev. 6.00 feb 22, 2005 page 414 of 1484 rej09b0103-0600
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 415 of 1484 rej09b0103-0600 section 12 watchdog timer 12.1 overview the chip has two channel inbuilt watchdog timers (wdt0/wdt1). the wdt can also generate an internal reset signal for the chip if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. 12.1.1 features wdt features are listed below. ? switchable between watchdog timer mode and interval timer mode ? an internal reset can be issued if the timer counter overflows ? in the watchdog timer mode, the wdt can generate an internal reset ? interrupt generation when in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt ? wdt0 and wdt1 respectively allow eight and sixteen types * 1 of counter input clock to be selected ? the maximum interval of the wdt is given as a system clock cycle 131072 256 ? a subclock * 2 may be selected for the input counter of wdt1 ? where a subclock is selected, the maximum interval is given as a subclock cycle 256 256 notes: 1. other than the u-mask and w-mask versions, and h8s/2635 group have eight types of counter input clock as well as wdt0. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. see section 22a.7, subclock osc illator, for the met hod of fixing pins when osc1 and osc2 are not used. the h8s/2639 and h8s/2635 groups have no osc1 and osc2 pins.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 416 of 1484 rej09b0103-0600 12.1.2 block diagram figures 12-1 (a) and 12-1 (b) show block diagrams of the wdt. overflow interrupt control wovi 0 (interrupt request signal) internal reset signal * 1 reset control rstcsr tcnt tscr /2 * 2 /64 * 2 /128 * 2 /512 * 2 /2048 * 2 /8192 * 2 /32768 * 2 /131072 * 2 clock clock select internal clock sources bus interface module bus legend: tcsr: tcnt: rstcsr: notes: 1. the type of internal reset signal depends on a register setting. 2. in the u-mask and w-mask versions, and h8s/2635 group, in subactive and subsleep modes operates as sub. timer control/status register timer counter reset control/status register internal bus wdt figure 12-1 (a) block diagram of wdt0
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 417 of 1484 rej09b0103-0600 overflow interrupt control reset control wovi1 (interrupt request signal) internal reset signal * 1 tcnt tcsr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock bus interface internal bus module bus tcsr : tcnt : notes: 1. 2. an internal reset signal can be generated by setting the register the reset thus generated is a reset subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the u-mask and w-mask versions, and h8s/2635 group only. timer control/status register timer counter wdt legend: internal nmi interrupt request signal sub/2 * 2 sub/4 * 2 sub/8 * 2 sub/16 * 2 sub/32 * 2 sub/64 * 2 sub/128 * 2 sub/256 * 2 figure 12-1 (b) block diagram of wdt1
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 418 of 1484 rej09b0103-0600 12.1.3 pin configuration there are no pins related to the wdt. 12.1.4 register configuration the wdt has five registers, as summarized in table 12-1. these registers control clock selection, wdt mode switching, and the reset signal. table 12-1 wdt registers address * 1 channel name abbreviation r/w initial value write * 2 read 0 timer control/status register 0 tcsr0 r/(w) * 3 h'18 h'ff74 h'ff74 timer counter 0 tcnt0 r/w h'00 h'ff74 h'ff75 reset control/status register rstcsr0 r/(w) * 3 h'1f h'ff76 h'ff77 1 timer control/status register 1 tcsr1 r/(w) * 3 h'00 h'ffa2 h'ffa2 timer counter 1 tcnt1 r/w h'00 h'ffa2 h'ffa3 notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 12.2.4, notes on register access. 3. only a write of 0 is permitted to bit 7, to clear the flag.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 419 of 1484 rej09b0103-0600 12.2 register descriptions 12.2.1 timer counter (tcnt) bit:76543210 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w tcnt is an 8-bit readable/writable * up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), an interval timer interrupt (wovi) is generated, depending on the mode selected by the wt/ it bit in tcsr. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * tcnt is write-protected by a password to prevent accidental overwriting. for details see section 12.2.4, notes on register access.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 420 of 1484 rej09b0103-0600 12.2.2 timer control/status register (tcsr) tcsr0 bit:76543210 ovf wt/ it tme ? ? cks2 cks1 cks0 initial value:00011000 r/w : r/(w) * r/w r/w ? ? r/w r/w r/w note: * only a 0 may be written to this bit to clear the flag. tcsr1 bit:76543210 ovf wt/ it tme pss * 2 rst/ nmi cks2 cks1 cks0 initial value:00000000 r/w : r/(w) * 1 r/w r/w r/w r/w r/w r/w r/w notes: 1. only a 0 may be written to this bit to clear the flag. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. tcsr is an 8-bit readable/writable * register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcsr0 (tcsr1) is initialized to h'18 (h'00) by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * tcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.4, notes on register access.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 421 of 1484 rej09b0103-0600 bit 7?overflow flag (ovf): indicates that tcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] (initial value) ? cleared when 0 is written to the tme bit (only applies to wdt1) ? cleared by reading tcsr * when ovf = 1, then writing 0 to ovf 1 [setting condition] ? when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. note: * when interval timer interrupts are disabled and ovf is polled, read the ovf = 1 state at least twice. in the interval timer mode, the ovf flag can be cleared in the interval timer interrupt routine by writing 0 to ovf after reading tcsr when ovf is set to 1, in accordance with the conditions for clearing the ovf flag. however, when attempting to poll the ovf flag when interval timer interrupts are prohibited the ovf value will not be recognized as 1 (even though it is set to 1) if there is a conflict between the timing used to set the ovf flag and the timing used to read the ovf flag. in such cases it is possible to completely satisfy the conditions for clearing the ovf flag by reading ovf two or more times while its value is 1. in a situation such as the above, the ovf flag should be read two or more times while its value is 1 and then cleared. bit 6?timer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. this selection determines whether wdt0 issues an internal reset when tcnt overflows while bit rste of the reset control/status register (rstcsr) is set to 1. in the interval timer mode, wdt0 sends a wovi interrupt request to the cpu. wdt1, on the other hand, requests a reset or an nmi interrupt from the cpu if the watchdog timer mode is chosen, whereas it requests a wovi interrupt from the cpu if the interval timer mode is chosen.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 422 of 1484 rej09b0103-0600 wdt0 mode select tcsr0 wt/ it description 0 interval timer mode: wdt0 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows (initial value) 1 watchdog timer mode: a reset is issued when the tcnt overflows if the rste bit of rstcsr is set to 1 * note: * for details see section 12.2.3, reset control/status register (rstcsr). wdt1 mode select tcsr1 wt/ it description 0 interval timer mode: wdt1 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows (initial value) 1 watchdog timer mode: wdt1 requests a reset or an nmi interrupt from the cpu when the tcnt overflows bit 5?timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt counts wdt0 tcsr bit 4?reserved bit: a read operation on this bit always causes a 1 to be read out. every write operation on this bit is invalidated. wdt1 tcsr bit 4?prescaler select (pss): this bit is used to select an input clock source for the tcnt of wdt1. see the descriptions of clock select 2 to 0 for details.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 423 of 1484 rej09b0103-0600 wdt1 tcsr bit 4 pss description 0 the tcnt counts frequency-division clock pulses of the based prescaler (psm) (initial value) 1 the tcnt counts frequency-division clock pulses of the sub * -based prescaler (pss) note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available only in the u-mask and w-mask versions, but are not available in the other versions. wdt0 tcsr bit 3?reserved: a read operation on this bit always causes a 1 to be read out. every write operation on this bit is invalidated. wdt1 tcsr bit 3?reset or nmi (rst/ nmi ): this bit is used to choose between an internal reset request and an nmi request when the tcnt overflows during the watchdog timer mode. bit 3 rst/ nmi description 0 nmi request (initial value) 1 internal reset request bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by dividing the system clock ( ) or subclock * ( sub), for input to tcnt. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions, and in them the pss bit is reserved. only 0 should be written to this bit.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 424 of 1484 rej09b0103-0600 wdt0 input clock select description bit 2 cks2 bit 1 cks1 bit 0 cks0 clock overflow period * 1 (where = 20 mhz) 000 /2 * 2 (initial value) 25.6 s 1 /64 * 2 819.2 s 10 /128 * 2 1.6 ms 1 /512 * 2 6.6 ms 100 /2048 * 2 26.2 ms 1 /8192 * 2 104.9 ms 10 /32768 * 2 419.4 ms 1 /131072 * 2 1.68 s notes: 1. an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. 2. in the u-mask and w-mask versions, and h8s/2635 group, in subactive and subsleep modes operates as sub.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 425 of 1484 rej09b0103-0600 wdt1 input clock select description bit 4 pss * 2 bit 2 cks2 bit 1 cks1 bit 0 cks0 clock overflow period * 1 (where = 20 mhz) (where sub * 2 = 32.768 khz) 0000 /2 (initial value) 25.6 s 1 /64 819.2 s 10 /128 1.6 ms 1 /512 6.6 ms 100 /2048 26.2 ms 1 /8192 104.9 ms 10 /32768 419.4 ms 0111 /131072 1.68 s 1000 sub/2 * 2 15.6 ms 1 sub/4 * 2 31.3 ms 10 sub/8 * 2 62.5 ms 1 sub/16 * 2 125 ms 100 sub/32 * 2 250 ms 1 sub/64 * 2 500 ms 10 sub/128 * 2 1 s 1 sub/256 * 2 2 s notes: 1. an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions, therefore pss bit is reserved. 0 should be written when writing.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 426 of 1484 rej09b0103-0600 12.2.3 reset control/status register (rstcsr) bit:76543210 wovf rste rsts ? ? ? ? ? initial value:00011111 r/w : r/(w) * r/wr/w????? note: * can only be written with 0 for flag clearing. rstcsr is an 8-bit readable/writable * register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the wdt internal reset signal caused by overflows. note: * rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.4, notes on register access. bit 7?watchdog overflow flag (wovf): indicates that tcnt has overflowed (changed from h'ff to h'00) during watchdog timer operation. this bit is not set in interval timer mode. bit 7 wovf description 0 [clearing condition] (initial value) ? cleared by reading rstcsr when wovf = 1, then writing 0 to wovf 1 [setting condition] ? set when tcnt overflows (changed from h'ff to h'00) during watchdog timer operation bit 6?reset enable (rste): specifies whether or not a reset signal is generated in the h8s/2636 if tcnt overflows during watchdog timer operation. bit 6 rste description 0 reset signal is not generated if tcnt overflows * (initial value) 1 reset signal is generated if tcnt overflows note: * the modules within the chip are not reset, but tcnt and tcsr within the wdt are reset.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 427 of 1484 rej09b0103-0600 bit 5?reset select (rsts): selects the type of internal reset generated if tcnt overflows during watchdog timer operation. for details of the types of reset, see section 4, exception handling. bit 5 rsts description 0 reset (initial value) 1 do not set bits 4 to 0?reserved: always read as 1 and cannot be modified. 12.2.4 notes on register access the watchdog timer?s tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transfer instruction. they cannot be written to with byte instructions. figure 12-2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ff74 address: h'ff74 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 12-2 format of data written to tcnt and tcsr (wdt0)
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 428 of 1484 rej09b0103-0600 writing to rstcsr: rstcsr must be written to by word transfer instruction to address h'ff76. it cannot be written to with byte instructions. figure 12-3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit differs from that for writing to the rste bit. to write 0 to the wovf bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0, but has no effect on the rste bit. to write to the rste bit, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the values in bits 6 and 5 of the lower byte into the rste bit, but has no effect on the wovf bit. h'a5 h'00 15 8 7 0 h'5a write data 15 8 7 0 writing 0 to wovf bit writing to rste bit address: h'ff76 address: h'ff76 figure 12-3 format of data written to rstcsr (wdt0) reading tcnt, tcsr, and rstcsr (wdt0): these registers are read in the same way as other registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 429 of 1484 rej09b0103-0600 12.3 operation 12.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it bit in tcsr and the tme bit to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally by writing h'00) before overflow occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system malfunction or other error, an internal reset is issued, in the case of wdt0, if the rste bit in rstcsr is set to 1. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. in the case of wdt1, the chip is reset, or an nmi interrupt request is generated, for 516 system clock periods (516 ) (515 or 516 clock periods when the clock source is /sub * (pss = 1)). this is illustrated in figure 12-4 (b). an nmi request from the watchdog timer and an interrupt request from the nmi pin are both treated as having the same vector. so, avoid handling an nmi request from the watchdog timer and an interrupt request from the nmi pin at the same time. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 430 of 1484 rej09b0103-0600 tcnt value h'00 time h'ff wt/ it = 1 tme = 1 write h'00 to tcnt wt/ it = 1 tme = 1 write h'00 to tcnt 518 states internal reset signal * wt/ it : tme: note: * the internal reset signal is generated only if the rste bit is set to 1. overflow internal reset is generated wovf = 1 timer mode select bit timer enable bit legend: figure 12-4 (a) wdt0 watchdog timer operation tcnt value h'00 time h'ff wt/ it = 1 tme = 1 write h'00 to tcnt wt/ it = 1 tme = 1 write h'00 to tcnt 515/516 states internal reset signal wt/ it : tme : legend: overflow internal reset is generated wovf = 1 * timer mode select bit timer enable bit note: * the wovf bit is set to 1 and then cleared to 0 by an internal reset. figure 12-4 (b) wdt1 watchdog timer operation
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 431 of 1484 rej09b0103-0600 12.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 12-5. this function can be used to generate interrupt requests at regular intervals. tcnt value h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt request generation wovi wovi wovi figure 12-5 interval timer operation 12.3.3 timing of setting overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 12-6. with wdt1, the ovf bit of the tcsr is set to 1 and a simultaneous nmi interrupt is requested when the tcnt overflows if the nmi request has been chosen in the watchdog timer mode.
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 432 of 1484 rej09b0103-0600 tcnt h'ff h'00 overflow signal (internal signal) ovf figure 12-6 timing of setting of ovf 12.3.4 timing of setting of watchdog timer overflow flag (wovf) in the wdt0, the wovf flag is set to 1 if tcnt overflows during watchdog timer operation. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire chip. figure 12-7 shows the timing in this case. tcnt h'ff h'00 overflow signal (internal signal) wovf internal reset signal 518 states (wdt0) 515/516 states (wdt1) figure 12-7 timing of setting of wovf
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 433 of 1484 rej09b0103-0600 12.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. if an nmi request has been chosen in the watchdog timer mode, an nmi request is generated when a tcnt overflow occurs. 12.5 usage notes 12.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 12-8 shows this operation. a ddress internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 12-8 contention between tcnt write and increment
section 12 watchdog timer rev. 6.00 feb 22, 2005 page 434 of 1484 rej09b0103-0600 12.5.2 changing value of pss* and cks2 to cks0 if bits pss and cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits pss * and cks2 to cks0. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. 12.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 12.5.4 internal reset in watchdog timer mode the chip is not reset internally if tcnt overflows while the rste bit is cleared to 0 during watchdog timer operation, but tcnt and tscr of the wdt are reset. 12.5.5 ovf flag clearing in interval timer mode if conflict occurs between ovf flag clearing and ovf flag reading in interval timer mode, the flag may not be cleared by writing 0 to ovf even though the ovf = 1 state has been read. when interval timer interrupts are disabled and the ovf flag is polled, for instance, and there is a possibility of conflict between ovf flag setting and reading, the ovf = 1 state s hould be read at least twice before writing 0 to ovf in order to clear the flag.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 435 of 1484 rej09b0103-0600 section 13 serial communication interface (sci) note: the h8s/2635 group is not equipped with a dtc. 13.1 overview the chip is equipped with 3 independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 13.1.1 features sci features are listed below. ? choice of asynchronous or clocked synchronous serial communication mode asynchronous mode ? serial data communication executed using asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length : 7 or 8 bits stop bit length : 1 or 2 bits parity : even, odd, or none multiprocessor bit : 1 or 0 ? receive error detection : parity, overrun, and framing errors ? break detection : break can be detected by reading the rxd pin level directly in case of a framing error clocked synchronous mode ? serial data communication synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 436 of 1484 rej09b0103-0600 ? one serial data transfer format data length : 8 bits ? receive error detection : overrun errors detected ? full-duplex communication capab ility ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the trans mitter and the r eceiver, enabling continuous transmission and continuous reception of serial data ? choice of lsb-first or msb-first transfer ? can be selected regardless of the communication mode * (except in the case of asynchronous mode 7-bit data) note: * descriptions in this section refer to lsb-first transfer. ? on-chip baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources ? four interrupt sources ? transmit-data-empty, transmit-end, receive-data-full, and receive error ? that can issue requests independently ? the transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (dtc) to execute data transfer ? module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 437 of 1484 rej09b0103-0600 13.1.2 block diagram figure 13-1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock /4 /16 /64 txi tei rxi eri smr legend: rsr: rdr: tsr: tdr: smr: scr: ssr: scmr: brr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register smart card mode register bit rate register figure 13-1 block diagram of sci
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 438 of 1484 rej09b0103-0600 13.1.3 pin configuration table 13-1 shows the serial pins for each sci channel. table 13-1 sci pins channel pin name symbol * i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 439 of 1484 rej09b0103-0600 13.1.4 register configuration the sci has the internal registers shown in table 13-2. these registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/r eceiver. table 13-2 sci registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h 'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h 'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h 'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all module stop control register b mstpcrb r/w h'ff h'fde9 notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 440 of 1484 rej09b0103-0600 13.2 register descriptions 13.2.1 receive shift register (rsr) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit r/w : : rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 13.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, in standby mode, watch mode * , subactive mode * , and subsleep mode * or module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 441 of 1484 rej09b0103-0600 13.2.3 transmit shift register (tsr) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit r/w : : tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 13.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, in standby mode, watch mode * , subactive mode * , and subsleep mode * or module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 442 of 1484 rej09b0103-0600 13.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : smr is an 8-bit register used to set the sci?s serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset and in hardware standby mode. bit 7?communication mode (c/ a ): selects asynchronous mode or clocked synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6?character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in clocked synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 443 of 1484 rej09b0103-0600 bit 5?parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2 when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 444 of 1484 rej09b0103-0600 bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bits setting is only valid in asynchronous mode. if clocked synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent (initial value) 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2?multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. for details of the multiprocessor communication function, see section 13.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 445 of 1484 rej09b0103-0600 bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from , /4, /16, and /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, bit rate register (brr). bit 1 bit 0 cks1 cks0 description 00 clock (initial value) 1 /4 clock 10 /16 clock 1 /64 clock 13.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset and in standby mode. bit 7?transmit interrupt enable (tie): enables or disables transmit data empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit data empty interrupt (txi) requests disabled * (initial value) 1 transmit data empty interrupt (txi) requests enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 446 of 1484 rej09b0103-0600 bit 6?receive interrupt enable (rie): enables or disables receive data full interrupt (rxi) request and receive error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled * (initial value) 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. bit 4?receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 447 of 1484 rej09b0103-0600 bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in smr is set to 1. the mpie bit setting is invalid in clocked synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2?transmit end interrupt enable (teie): enables or disables transmit end interrupt (tei) request generation when there is no valid transmit data in tdr in msb data transmission. bit 2 teie description 0 transmit end interrupt (tei) request disabled * (initial value) 1 transmit end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 448 of 1484 rej09b0103-0600 bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (cke1 = 1). note that the sci?s operating mode must be decided using smr before setting the cke1 and cke0 bits. for details of clock source selection, see table 13.9 in section 13.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 449 of 1484 rej09b0103-0600 13.2.7 serial status register (ssr) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : note: * only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, in standby mode, watch mode * , subactive mode * , and subsleep mode * or module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bit 7?transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 450 of 1484 rej09b0103-0600 bit 6?receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5?overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 ? when 0 is written to orer after reading orer = 1 1 [setting condition] ? when the next serial reception is completed while rdrf = 1 * 2 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 451 of 1484 rej09b0103-0600 bit 4?framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 ? when 0 is written to fer after reading fer = 1 1 [setting condition] ? when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 3?parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 ? when 0 is written to per after reading per = 1 1 [setting condition] ? when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 2?transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 452 of 1484 rej09b0103-0600 bit 2 tend description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac or dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1?multiprocessor bit (mpb): when reception is performed using multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * ? when data with a 0 multiprocessor bit is received 1 [setting condition] ? when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0?multiprocessor bit transfer (mpbt): when transmission is performed using multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 453 of 1484 rej09b0103-0600 13.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in standby mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 13-3 shows sample brr settings in asynchronous mode, and table 13-4 shows sample brr settings in clocked synchronous mode. table 13-3 brr settings for various bit rates (asynchronous mode) = 4 mhz = 4.9152 mhz = 5 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 ? ? ? 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 ? ? ? 0 3 0.00 0 3 1.73
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 454 of 1484 rej09b0103-0600 = 6 mhz = 6.144 mhz = 7.3728 mhz = 8 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ? ? ? 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 ? ? ? = 9.8304 mhz = 10 mhz = 12 mhz = 12.288 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 455 of 1484 rej09b0103-0600 = 14 mhz = 14.7456 mhz = 16 mhz = 17.2032 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 16 1.20 38400 ? ? ? 0 11 0.00 0 12 0.16 0 13 0.00 = 18 mhz = 19.6608 mhz = 20 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 456 of 1484 rej09b0103-0600 table 13-4 brr settings for various bit rates (clocked synchronous mode) = 4 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz bit rate (bit/s) n n n n n n n n n n 110 ? ? 250 2 249 3 124 ? ? 3 249 500 2 124 2 249 ? ? 3 124 ? ? 1 k 1 249 2 124 ? ? 2 249 ? ? 2.5 k 1 99 1 199 1 249 2 99 2 124 5 k 0 199 1 99 1 124 1 199 1 249 10 k 0 99 0 199 0 249 1 99 1 124 25 k 0 39 0 79 0 99 0 159 0 199 50 k 0 19 0 39 0 49 0 79 0 99 100 k 0 9 0 19 0 24 0 39 0 49 250 k 0 3 0 7 0 9 0 15 0 19 500 k 0 1 0 3 0 4 0 7 0 9 1 m 0 0 * 01 03 04 2.5 m 0 0 * 01 5 m 00 * note: as far as possible, the setting should be made so that the error is no more than 1%. legend: blank: cannot be set. ?: can be set, but there will be a degree of error. * : continuous transfer is not possible.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 457 of 1484 rej09b0103-0600 the brr setting is found from the following formulas. asynchronous mode: n = 64 2 2n?1 b 10 6 ? 1 clocked synchronous mode: n = 8 2 2n?1 b 10 6 ? 1 where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0 00 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is found from the following formula: error (%) = { 10 6 (n + 1) b 64 2 2n?1 ? 1 } 100
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 458 of 1484 rej09b0103-0600 table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. tables 13-6 and 13-7 show the maximum bit rates with external clock input. table 13-5 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 459 of 1484 rej09b0103-0600 table 13-6 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 table 13-7 maximum bit rate with external clock input (clocked synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 460 of 1484 rej09b0103-0600 13.2.9 smart card mode register (scmr) 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value r/w : : : scmr selects lsb-first or msb-first by means of bit sdir. except in the case of asynchronous mode 7-bit data, lsb-first or msb-first can be selected regardless of the serial communication mode. the descriptions in this chapter refer to lsb-first transfer. for details of the other bits in scmr, see section 14.2.1, smart card mode register (scmr). scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?reserved: these bits are always read as 1 and cannot be modified. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. this bit is valid when 8-bit data is used as the transmit/receive format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 461 of 1484 rej09b0103-0600 bit 2?smart card data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr. bit 2 sinv description 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1?reserved: this bit is always read as 1 and cannot be modified. bit 0?smart card interface mode select (smif): when the smart card interface operates as a normal sci, 0 should be written in this bit. bit 0 smif description 0 operates as normal sci (smart card interface function disabled) (initial value) 1 smart card interface function enabled 13.2.10 module stop control register b (mstpcrb) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w : : : mstpcrb mstpcrb is 8-bit readable/writable registers that perform module stop mode control. setting any of bits mstpb7 to mstbp5 to 1 stops sci0 to sci2 operating and enter module stop mode on completion of the bus cycle. for details, see section 23a.5, 23b.5, module stop mode. mstpcrb is initialized to h'ff by a reset and in hardware standby mode. they are not initialized by a manual reset and in software standby mode.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 462 of 1484 rej09b0103-0600 bit 7?module stop (mstpb7): specifies the sci0 module stop mode. bit 7 mstpb7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value) bit 6?module stop (mstpb6): specifies the sci1 module stop mode. bit 6 mstpb6 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) bit 5?module stop (mstpb5): specifies the sci2 module stop mode. bit 5 mstpb5 description 0 sci2 module stop mode is cleared 1 sci2 module stop mode is set (initial value)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 463 of 1484 rej09b0103-0600 13.3 operation 13.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or clocked synchronous mode and the transmission format is made using smr as shown in table 13-8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 13-9. asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overrun errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) clocked synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 464 of 1484 rej09b0103-0600 table 13-8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 c/ a chr mp pe stop mode data length multi processor bit parity bit stop bit length 0 0 0 0 0 8-bit data no no 1 bit 1 2 bits 10 yes1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 10 yes1 bit 1 asynchronous mode 2 bits 0 1 ? 0 8-bit data yes no 1 bit ?1 2 bits 1 ? 0 7-bit data 1 bit ?1 asynchronous mode (multi- processor format) 2 bits 1 ????clocked synchronous mode 8-bit data no none table 13-9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 bit 1 bit 0 c/ a cke1 cke0 mode clock source sck pin function 0 0 0 internal sci does not use sck pin 1 outputs clock with same frequency as bit rate 1 0 external 1 asynchronous mode inputs clock with frequency of 16 times the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 clocked synchronous mode
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 465 of 1484 rej09b0103-0600 13.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the r eceiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 13-2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, the sci performs synchronization at the fa lling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits1 bit, or none one unit of transfer data (character or frame) figure 13-2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 466 of 1484 rej09b0103-0600 data transfer format: table 13-10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. table 13-10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 467 of 1484 rej09b0103-0600 clock: either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci?s serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 13-9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 13-3 relation between output clock and transfer data phase (asynchronous mode) data transfer operations: ? sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 468 of 1484 rej09b0103-0600 figure 13-4 shows a sample sci initialization flowchart. wait start initialization set data transfer format in smr and scmr [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 13-4 sample sci initialization flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 469 of 1484 rej09b0103-0600 ? serial data transmission (asynchronous mode) figure 13-5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and date is written to tdr. [4] break output at the end of serial transmission: to output a break in serial transmission, set ddr for the port corresponding to the txd pin to 1, clear dr to 0, then clear the te bit in scr to 0. figure 13-5 sample serial transmission flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 470 of 1484 rej09b0103-0600 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 471 of 1484 rej09b0103-0600 figure 13-6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 13-6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 472 of 1484 rej09b0103-0600 ? serial data reception (asynchronous mode) figure 13-7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer = 1 rdrf= 1 all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. the rdrf flag is cleared automatically when dtc is activated by an rxi interrupt and the rdr value is read. [1] [2] [3] [4] [5] figure 13-7 sample serial reception data flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 473 of 1484 rej09b0103-0600 [3] error processing parity error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer = 1 fer = 1 break? per = 1 clear re bit in scr to 0 figure 13-7 sample serial reception data flowchart (cont)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 474 of 1484 rej09b0103-0600 in serial reception, the sci operates as described below. [1] the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] the received data is stored in rsr in lsb-to-msb order. [3] the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. [a] parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. [b] stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. [c] status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error * is detected in the error check, the operation is as shown in table 13-11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive error interrupt (eri) request is generated.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 475 of 1484 rej09b0103-0600 table 13-11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr figure 13-8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine figure 13-8 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 476 of 1484 rej09b0103-0600 13.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 13-9 shows an example of inter-processor communication using the multiprocessor format. data transfer format: there are four data transfer formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 13-10. clock: see the section on asynchronous mode.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 477 of 1484 rej09b0103-0600 transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 13-9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer operations: ? multiprocessor serial data transmission figure 13-10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 478 of 1484 rej09b0103-0600 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? clear tdre flag to 0 sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. break output at the end of serial transmission: to output a break in serial transmission, set the port ddr to 1, clear dr to 0, then clear the te bit in scr to 0. [1] [2] [3] [4] figure 13-10 sample multiprocessor serial transmission flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 479 of 1484 rej09b0103-0600 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] multiprocessor bit one multiprocessor bit (mpbt value) is output. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmission end interrupt (tei) request is generated.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 480 of 1484 rej09b0103-0600 figure 13-11 shows an example of sci operation for transmission using the multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 13-11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) ? multiprocessor serial data reception figure 13-12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 481 of 1484 rej09b0103-0600 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer orer = 1 rdrf = 1 all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station?s id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer = 1 read receive data in rdr rdrf = 1 sci initialization: the rxd pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr to 1. sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station's id. if the data is not this station's id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station's id, clear the rdrf flag to 0. sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. [1] [2] [3] [4] [5] figure 13-12 sample multiprocessor serial reception flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 482 of 1484 rej09b0103-0600 error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer = 1 fer = 1 break? clear re bit in scr to 0 [5] figure 13-12 sample multiprocessor serial reception flowchart (cont)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 483 of 1484 rej09b0103-0600 figure 13-13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this station ? s id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station ? s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this station ? s id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches station ? s id data2 id1 figure 13-13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 484 of 1484 rej09b0103-0600 13.3.4 operation in clocked synchronous mode in clocked synchronous mode, data is trans mitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 13-14 shows the general format for clocked synchronous serial communication. don ? t care don ? t care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 13-14 data format in synchronous communication in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in clocked serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in clocked synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 485 of 1484 rej09b0103-0600 data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 13-9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. if you want to perform receive operations in units of one character, you should select an external clock as the clock source.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 486 of 1484 rej09b0103-0600 data transfer operations: ? sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 13-15 shows a sample sci initialization flowchart. wait note: in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. set cke1 and cke0 bits in scr (te, re bits 0) figure 13-15 sample sci initialization flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 487 of 1484 rej09b0103-0600 ? serial data transmission (clocked synchronous mode) figure 13-16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. figure 13-16 sample serial transmission flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 488 of 1484 rej09b0103-0600 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). [3] the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. [4] after completion of serial transmission, the sck pin is fixed high. figure 13-17 shows an example of sci operation in transmission.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 489 of 1484 rej09b0103-0600 transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 13-17 example of sci operation in transmission ? serial data reception (clocked synchronous mode) figure 13-18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to clocked synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 490 of 1484 rej09b0103-0600 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 rdrf = 1 all data received? read orer flag in ssr [1] [2] [3] [4] [5] sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. error processing overrun error processing [3] clear orer flag in ssr to 0 figure 13-18 sample serial reception flowchart
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 491 of 1484 rej09b0103-0600 in serial reception, the sci operates as described below. [1] the sci performs internal initialization in synchronization with serial clock input or output. [2] the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 13-11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive error interrupt (eri) request is generated. figure 13-19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated eri interrupt request generated by overrun error figure 13-19 example of sci operation in reception ? simultaneous serial data transmission and reception (clocked synchronous mode) figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 492 of 1484 rej09b0103-0600 yes [1] no initialization start transmission/reception [5] error processing [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 all data received? [2] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf = 1 read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. also, the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. figure 13-20 sample flowchart of simultaneous serial transmit and receive operations
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 493 of 1484 rej09b0103-0600 13.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 13-13 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in the scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by an eri interrupt request. table 13-12 sci interrupt sources channel interrupt source description dtc activation priority * 0 eri interrupt due to receive error (orer, fer, or per) not possible high rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 1 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 2 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible low note: * this table shows the initial state immediately after a reset. relative priorities among channels can be changed by means of the interrupt controller. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 494 of 1484 rej09b0103-0600 txi interrupt are requested simultaneously, the txi interrupt may have priority for acceptance, with the result that the tdre and tend flags are cleared. note that the tei interrupt will not be accepted in this case. 13.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 13-14. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 13-13 state of ssr status flags and transfer of receive data ssr status flags rdrf orer fer per receive data transfer rsr to rdr receive error status 1100x overrun error 0010 framing error 0001 parity error 1110x overrun error + framing error 1101x overrun error + parity error 0011 framing error + parity error 1111x overrun error + framing error + parity error notes: : receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 495 of 1484 rej09b0103-0600 break detection and processing (asynchronous mode only): when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. sending a break (asynchronous mode only): the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin are first set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (clocked synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the fa lling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 13-21.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 496 of 1484 rej09b0103-0600 internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 13-21 receive data sampling timing in asynchronous mode thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 ? 1 2n ) ? (l ? 0.5) f ? | d ? 0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 ? 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 497 of 1484 rej09b0103-0600 restrictions on use of dtc * note: * the dtc is not implemented in the h8s/2635 and h8s/2634. ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after tdr is updated by the dtc. misoperation may occur if the transmit clock is i nput within 4 clocks after tdr is updated (figure 13-22). ? when rdr is read by the dtc, be sure to set the activation source to the relevant sci reception end interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t > 4 clocks. tdre figure 13-22 example of clocked synchronous transmission by dtc operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted w ill be undefined. when trans mitting wit hout changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read -> tdr write -> tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 13-23 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 13-24 and 13-25. operation should also be stopped (by clearing te, tie, and teie to 0) before making a transition from transmission by dtc * transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. to perform transmission with the dtc * after the relevant mode is cleared, setting te and tie to 1 will set the txi flag and start dtc * transmission. note: * the dtc is not implemented in the h8s/2635 and h8s/2634.
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 498 of 1484 rej09b0103-0600 ? reception receive operation should be stopped (by clearing re to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. rsr, rdr, and ssr are reset. if a transition is made without stopping operation, the data being received will be invalid. to continue receiving without changing the reception mode after the relevant mode is cleared, set re to 1 before starting reception. to receive with a different receive mode, the procedure must be started again from initialization. figure 13-26 shows a sample flowchart for mode transition during reception. read tend flag in ssr te = 0 transition to software standby mode, etc. exit from software standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes no no [1] [3] [2] te = 1 initialization [1] data being transmitted is interrupted. after exiting software standby mode, etc., normal cpu transmission is possible by setting te to 1, reading ssr, writing tdr, and clearing tdre to 0, but note that if the dtc has been activated, the remaining data in dtcram will be transmitted when te and tie are set to 1. [2] if tie and teie are set to 1, clear them to 0 in the same way. [3] includes module stop mode, watch mode, subactive mode, and sub- sleep mode. figure 13-23 sample flowchart for mode transition during transmission
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 499 of 1484 rej09b0103-0600 sck output pin te bit txd output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to software standby exit from software standby figure 13-24 asynchronous transmission using internal clock port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized by software standby. sck output pin te bit txd output pin sci txd output start of transmission end of transmission transition to software standby exit from software standby figure 13-25 synchronous transmission using internal clock
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 500 of 1484 rej09b0103-0600 re = 0 transition to software standby mode, etc. read receive data in rdr read rdrf flag in ssr exit from software standby mode, etc. change operating mode? no rdrf = 1 yes yes no [1] [2] re = 1 initialization [1] receive data being received becomes invalid. [2] includes module stop mode, watch mode, subactive mode, and subsleep mode. figure 13-26 sample flowchart for mode transition during reception
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 501 of 1484 rej09b0103-0600 switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 13-27) sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3. c/ a = 0 2. te = 0 half-cycle low-level output figure 13-27 operation when switching from sck pin function to port pin function
section 13 serial communication interface (sci) rev. 6.00 feb 22, 2005 page 502 of 1484 rej09b0103-0600 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/port pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 3. cke1 = 1 5. cke1 = 0 4. c/ a = 0 2. te = 0 high-level output te figure 13-28 operation when switching from sck pin function to port pin function (example of preventing low-level output)
section 14 smart card interface rev. 6.00 feb 22, 2005 page 503 of 1484 rej09b0103-0600 section 14 smart card interface note: the h8s/2635 group is not equipped with a dtc. 14.1 overview sci supports an ic card (smart card) interface conforming to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 14.1.1 features features of the smart card interface supported by the chip are as follows. ? asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? on-chip baud rate generator allows any bit rate to be selected ? three interrupt sources ? three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) * to execute data transfer note: * the dtc is not implemented in the h8s/2635 and h8s/2634.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 504 of 1484 rej09b0103-0600 14.1.2 block diagram figure 14-1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock /4 /16 /64 txi rxi eri smr legend: scmr: rsr: rdr: tsr: tdr: smr: scr: ssr: brr: smart card mode register receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register figure 14-1 block diagram of smart card interface
section 14 smart card interface rev. 6.00 feb 22, 2005 page 505 of 1484 rej09b0103-0600 14.1.3 pin configuration table 14-1 shows the smart card interface pin configuration. table 14-1 smart card interface pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output
section 14 smart card interface rev. 6.00 feb 22, 2005 page 506 of 1484 rej09b0103-0600 14.1.4 register configuration table 14-2 shows the registers used by the smart card interface. details of smr, brr, scr, tdr, rdr, and mstpcr are the same as for the normal sci function: see the register descriptions in section 13, serial communication interface (sci). table 14-2 smart card interface registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h 'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h 'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h 'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all module stop control register b mstpcrb r/w h'ff h'fde9 notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 507 of 1484 rej09b0103-0600 14.2 register descriptions registers added with the smart card interface and bits for which the function changes are described here. 14.2.1 smart card mode register (scmr) bit:76543210 ????sdirsinv?smif initial value:11110010 r/w:????r/wr/w?r/w scmr is an 8-bit readable/writable register that selects the smart card interface function. scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?reserved: these bits are always read as 1 and cannot be modified. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
section 14 smart card interface rev. 6.00 feb 22, 2005 page 508 of 1484 rej09b0103-0600 bit 2?smart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the sdir bit for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 14.3.4, register settings. bit 2 sinv description 0 tdr contents are transmitted as they are (initial value) receive data is stored as it is in rdr 1 tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr bit 1?reserved: this bit is always read as 1 and cannot be modified. bit 0?smart card interface mode select (smif): enables or disables the smart card interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled
section 14 smart card interface rev. 6.00 feb 22, 2005 page 509 of 1484 rej09b0103-0600 14.2.2 serial status register (ssr) bit:76543210 tdre rdrf orer ers per tend mpb mpbt initial value:10000100 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: * only 0 can be written, to clear these flags. bit 4 of ssr has a different function in smart card interface mode. coupled with this, the setting conditions for bit 2, tend, are also different. bits 7 to 5? operate in the same way as for the normal sci. for details, see section 13.2.7, serial status register (ssr). bit 4?error signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, with no error signal [clearing conditions] (initial value) ? upon reset, and in standby mode or module stop mode ? when 0 is written to ers after reading ers = 1 1 error signal sent from receiver indicating detection of parity error [setting condition] ? when the low level of the error signal is sampled note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 510 of 1484 rej09b0103-0600 bits 3 to 0? operate in the same way as for the normal sci. for details, see section 13.2.7, serial status register (ssr). however, the setting conditions for the tend bit, are as shown below. bit 2 tend description 0 transmission is in progress [clearing conditions] (initial value) ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and write data to tdr 1 transmission has ended [setting conditions] ? upon reset, and in standby mode or module stop mode ? when the te bit in scr is 0 and the ers bit is also 0 ? when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 ? when tdre = 1 and ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 ? when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 ? when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 note: etu: elementary time unit (time for transfer of 1 bit)
section 14 smart card interface rev. 6.00 feb 22, 2005 page 511 of 1484 rej09b0103-0600 14.2.3 serial mode register (smr) bit:76543210 gm blk pe o/ e bcp1 bcp0 cks1 cks0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: when the smart card interface is used, be sure to make the 1 setting shown for bit 5. the function of bits 7, 6, 3, and 2 of smr changes in smart card interface mode. bit 7?gsm mode (gm): sets the smart card interface function to gsm mode. this bit is cleared to 0 when the normal smart card interface is used. in gsm mode, this bit is set to 1, the timing of setting of the tend flag that indicates transmission completion is advanced and clock output control mode addition is performed. the contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (scr). bit 7 gm description 0 normal smart card interface mode operation (initial value) ? tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit ? clock output on/off control only 1 gsm mode smart card interface mode operation ? tend flag generation 11.0 etu after beginning of start bit ? high/low fixing control possible in addition to clock output on/off control (set by scr) note: etu: elementary time unit (time for transfer of 1 bit)
section 14 smart card interface rev. 6.00 feb 22, 2005 page 512 of 1484 rej09b0103-0600 bit 6?block transfer mode (blk): selects block transfer mode. bit 6 blk description 0 normal smart card interface mode operation ? error signal transmission/detection and automatic data retransmission performed ? txi interrupt generated by tend flag ? tend flag set 12.5 etu after start of transmission (11.0 etu in gsm mode) 1 block transfer mode operation ? error signal transmission/detection and automatic data retransmission not performed ? txi interrupt generated by tdre flag ? tend flag set 11.5 etu after start of transmission (11.0 etu in gsm mode) note: etu: elementary time unit (time for transfer of 1 bit) bits 3 and 2?basic clock pulse 1 and 2 (bcp1, bcp0): these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. bit 3 bit 2 bcp1 bcp0 description 0 0 32 clock periods (initial value) 1 64 clock periods 1 0 372 clock periods 1 256 clock periods bits 5, 4, 1, and 0: operate in the same way as for the normal sci. for details, see section 13.2.5, serial mode register (smr).
section 14 smart card interface rev. 6.00 feb 22, 2005 page 513 of 1484 rej09b0103-0600 14.2.4 serial control register (scr) bit:76543210 tie rie te re mpie teie cke1 cke0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w in smart card interface mode, the function of bits 1 and 0 of scr changes when bit 7 of the serial mode register (smr) is set to 1. bits 7 to 2 ?operate in the same way as for the normal sci. for details, see section 13.2.6, serial control register (scr). bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. scmr smr scr setting smif c/ a , gm cke1 cke0 sck pin function 0 see the sci 1 0 0 0 operates as port i/o pin 1 0 0 1 outputs clock as sck output pin 1 1 0 0 operates as sck output pin, with output fixed low 1 1 0 1 outputs clock as sck output pin 1 1 1 0 operates as sck output pin, with output fixed high 1 1 1 1 outputs clock as sck output pin
section 14 smart card interface rev. 6.00 feb 22, 2005 page 514 of 1484 rej09b0103-0600 14.3 operation 14.3.1 overview the main functions of the smart card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer (except in block transfer mode). ? only asynchronous communication is supported; there is no clocked synchronous communication function. note: etu: elementary time unit (time for transfer of 1 bit) 14.3.2 pin connections figure 14-2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected with the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card uses an internal clock. lsi port output is used as the reset signal. other pins must normally be connected to the power supply or ground.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 515 of 1484 rej09b0103-0600 txd rxd sck rx (port) chip i/o clk rst v cc connected equipment ic card data line clock line reset line figure 14-2 schematic diagram of smart card interface pin connections note: if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 516 of 1484 rej09b0103-0600 14.3.3 data format normal transfer mode: figure 14-3 shows the normal smart card interface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. if an error signal is sampled during transmission, the same data is retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output start bit data bits parity bit error signal legend: ds: d0 to d7: dp: de: figure 14-3 normal smart card interface data format the operation sequence is as follows. [1] when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 517 of 1484 rej09b0103-0600 [4] the receiving station carries out a parity check. if there is no parity error and the data is received normally, the receiving station waits for reception of the next data. if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. [5] if the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. if it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. block transfer mode: the operation sequence in block transfer mode is as follows. [1] when the data line in not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] after reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. when an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] the transmitting station proceeds to transmit the next data frame.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 518 of 1484 rej09b0103-0600 14.3.4 register settings table 14-3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 14-3 smart card interface register settings bit register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr gm blk 1 o/ e bcp1 bcp0 cks1 cks0 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr tie rie te re 0 0 cke1 * cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf orer ers per tend 0 0 rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr????sdirsinv?smif notes: ?: unused bit. * : the cke1 bit must be cleared to 0 when the gm bit in smr is cleared to 0. smr setting: the gm bit is cleared to 0 in normal smart card interface mode, and set to 1 in gsm mode. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. bits bcp1 and bcp0 select the number of basic clock periods in a 1-bit transfer interval. for details, see section 14.3.5, clock. the blk bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. brr setting: brr is used to set the bit rate. see section 14.3.5, clock, for the method of calculating the value to be set. scr setting: the function of the tie, rie, te, and re bits is the same as for the normal sci. for details, see section 13, serial communication interface (sci). bits cke1 and cke0 specify the clock output. when the gm bit in smr is cleared to 0, set these bits to b'00 if a clock is not to be output, or to b'01 if a clock is to be output. when the gm bit in smr is set to 1, clock output is performed. the clock output can also be fixed high or low.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 519 of 1484 rej09b0103-0600 smart card mode register (scmr) setting: the sdir bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the sinv bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the smif bit is set to 1 in the case of the smart card interface. examples of register settings and the waveform of the start character are shown below for the two types of ic card (direct convention and inverse convention). ? direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. ? inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data above is h'3f. the parity bit is 0, corresponding to state z, since even parity is stipulated for the smart card. with the h8s/2636, h8s/2638, h8s/2639, and h8s/2630 inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr is set to odd parity mode (the same applies to both transmission and reception).
section 14 smart card interface rev. 6.00 feb 22, 2005 page 520 of 1484 rej09b0103-0600 14.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with brr and the cks1, cks0, bcp1 and bcp0 bits in smr. the formula for calculating the bit rate is as shown below. table 14-5 shows some sample bit rates. if clock output is selected by setting cke0 to 1, a clock is output from the sck pin. the clock frequency is determined by the bit rate and the setting of bits bcp1 and bcp0. b = s 2 2n+1 (n + 1) 10 6 where: n = value set in brr (0 n 255) b = bit rate (bit/s) = operating frequency (mhz) n = see table 14-4 s = number of internal clocks in 1-bit period, set by bcp1 and bcp0 table 14-4 correspondence between n and cks1, cks0 n cks1 cks0 000 11 210 31 table 14-5 examples of bit rate b (bit/s) for various brr settings (when n = 0 and s = 372) (mhz) n 10.00 10.714 13.00 14.285 16.00 18.00 20.00 0 13441 14400 17473 19200 21505 24194 26882 1 6720 7200 8737 9600 10753 12097 13441 2 4480 4800 5824 6400 7168 8065 8961 note: bit rates are rounded to the nearest whole number.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 521 of 1484 rej09b0103-0600 the method of calculating the value to be set in the bit rate register (brr) from the operating frequency and bit rate, on the other hand, is shown below. n is an integer, 0 n 255, and the smaller error is specified. n = s 2 2n+1 b 10 6 ? 1 table 14-6 examples of brr settings for bit rate b (bit/s) (when n = 0 and s = 372) (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 bit/s n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60 note: a blank means no setting is available. table 14-7 maximum bit rate at various frequencies (smart card interface mode) (when s = 372) (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 the bit rate error is given by the following formula: error (%) = ( s 2 2n+1 b (n + 1) 10 6 ? 1) 100
section 14 smart card interface rev. 6.00 feb 22, 2005 page 522 of 1484 rej09b0103-0600 14.3.6 data transfer operations initialization: before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] clear the te and re bits in scr to 0. [2] clear the error flags ers, per, and orer in ssr to 0. [3] set the gm, blk, o/ e , bcp1, bcp0, cks1, cks0 bits in smr. set the pe bit to 1. [4] set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. [5] set the value corresponding to the bit rate in brr. [6] set the cke0 and cke1 bits in scr. clear the tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. [7] wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 523 of 1484 rej09b0103-0600 serial data transmission (except block transfer mode): as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the ers error flag in ssr is cleared to 0. [3] repeat steps [2] and [3] until it can be confirmed that the tend flag in ssr is set to 1. [4] write the transmit data to tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. [5] when transmitting data continuously, go back to step [2]. [6] to end transmission, clear the te bit to 0. with the above processing, interrupt servicing or data transfer by the dtc is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (eri) request will be generated. the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 14-6. if the dtc * is activated by a txi request, the number of bytes set in the dtc * can be transmitted automatically, including automatic retransmission. for details, see interrupt operation and data transfer operation by dtc below. notes: for block transfer mode, see section 13.3.2, operation in asynchronous mode. * the dtc is not implemented in the h8s/2635 and h8s/2634.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 524 of 1484 rej09b0103-0600 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend = 1? all data transmitted? tend = 1? ers = 0? ers = 0? figure 14-4 example of transmission processing flow
section 14 smart card interface rev. 6.00 feb 22, 2005 page 525 of 1484 rej09b0103-0600 (1) data write tdr tsr (shift register) data 1 (2) transfer from tdr to tsr data 1 data 1 ; data remains in tdr (3) serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the next transfer data to be transmitted has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps (2) and (3) above are repeated until the tend flag is set i/o signal line output data 1 data 1 figure 14-5 relation between transmit operation and internal registers ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5 etu txi (tend interrupt) 11.0 etu de guard time when gm = 1 legend: ds: start bit d0 to d7: data bits dp: parity bit de: error signal note: etu: elementary time unit (time for transfer of 1 bit) when gm = 0 figure 14-6 tend flag generation timing in transmission operation
section 14 smart card interface rev. 6.00 feb 22, 2005 page 526 of 1484 rej09b0103-0600 serial data reception (except block transfer mode): data reception in smart card mode uses the same processing procedure as for the normal sci. figure 14-7 shows an example of the transmission processing flow. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the orer flag and per flag in ssr are cleared to 0. if either is set, perform the appropriate receive error processing, then clear both the orer and the per flag to 0. [3] repeat steps [2] and [3] until it can be confirmed that the rdrf flag is set to 1. [4] read the receive data from rdr. [5] when receiving data continuously, clear the rdrf flag to 0 and go back to step [2]. [6] to end reception, clear the re bit to 0. initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf = 1? all data received? yes figure 14-7 example of reception processing flow
section 14 smart card interface rev. 6.00 feb 22, 2005 page 527 of 1484 rej09b0103-0600 with the above processing, interrupt servicing or data transfer by the dtc* is possible. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (rxi) request will be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transfer error interrupt (eri) request will be generated. if the dtc* is activated by an rxi request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the dtc* are transferred. for details, see interrupt operation and data transfer operation by dtc* followings. if a parity error occurs during reception and the per is set to 1, the received data is still transferred to rdr, and therefore this data can be read. note: for block transfer mode, see section 13.3.2, operation in asynchronous mode. * the dtc is not implemented in the h8s/2635 and h8s/2634. mode switching operation: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re bit to 0 and setting te bit to 1. the rdrf flag or the per and orer flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing te bit to 0 and setting re bit to 1. the tend flag can be used to check that the transmit operation has been completed. fixing clock output level: when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke1 and cke0 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 14-8 shows the timing for fixing the clock output level. in this example, gsm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled. sck specified pulse width scr write (cke0 = 0) scr write (cke0 = 1) specified pulse width figure 14-8 timing for fixing clock output level
section 14 smart card interface rev. 6.00 feb 22, 2005 page 528 of 1484 rej09b0103-0600 interrupt operation (except block transfer mode): there are three interrupt sources in smart card interface mode: transmit data empty interrupt (txi) requests, transfer error interrupt (eri) requests, and receive data full interrupt (rxi) requests. the transmit end interrupt (tei) request is not used in this mode. when the tend flag in ssr is set to 1, a txi interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and ers in ssr is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 14-8. note: for block transfer mode, see section 13.4, sci interrupts. table 14-8 smart card mode operating states and interrupt sources operating state flag enable bit interrupt source dtc activation transmit mode normal operation tend tie txi possible error ers rie eri not possible receive mode normal operation rdrf rie rxi possible error per, orer rie eri not possible data transfer operation by dtc * : in smart card mode, as with the normal sci, transfer can be carried out using the dtc. in a transmit operation, the tdre flag is also set to 1 at the same time as the tend flag in ssr, and a txi interrupt is generated. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transfer of the transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data transfer is performed by the dtc. in the event of an error, the sci retransmits the same data automatically. during this period, tend remains cleared to 0 and the dtc is not activated. therefore, the sci and dtc will automatically transmit the specified number of bytes, including retransmission in the event of an error. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request w ill be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, see section 8, data transfer controller (dtc).
section 14 smart card interface rev. 6.00 feb 22, 2005 page 529 of 1484 rej09b0103-0600 in a receive operation, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. if an error occurs, an error flag is set but the rdrf flag is not. consequently, the dtc is not activated, but instead, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared. notes: for block transfer mode, see section 13.4, sci interrupts. * the dtc is not implemented in the h8s/2635 and h8s/2634. 14.3.7 operation in gsm mode switching the mode: when switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. ? when changing from smart card interface mode to software standby mode [1] set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. [2] write 0 to the te bit and re bit in the serial control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. [3] write 0 to the cke0 bit in scr to halt the clock. [4] wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. [5] make the transition to the software standby state. ? when returning to smart card interface mode from software standby mode [6] exit the software standby state. [7] write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 530 of 1484 rej09b0103-0600 [1] [2] [3] [4] [5] [6] [7] software standby normal operation normal operation figure 14-9 clock halt and restart procedure powering on: to secure the clock duty from power-on, the following switching procedure should be followed. [1] the initial state is port input and high impedance. use a pull-up resistor or pull-down resistor to fix the potential. [2] fix the sck pin to the specified output level with the cke1 bit in scr. [3] set smr and scmr, and switch to smart card mode operation. [4] set the cke0 bit in scr to 1 to start clock output. 14.3.8 operation in block transfer mode operation in block transfer mode is the same as in sci asynchronous mode, except for the following points. for details, see section 13.3.2, operation in asynchronous mode. data format: the data format is 8 bits with parity. there is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. transmit/receive clock: only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. the number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits bcp1 and bcp0. for details, see section 14.3.5, clock. ers (fer) flag: as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0.
section 14 smart card interface rev. 6.00 feb 22, 2005 page 531 of 1484 rej09b0103-0600 14.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and reception margin in smart card interface mode: in smart card interface mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits bcp1 and bcp0). in reception, the sci samples the fa lling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. figure 14-10 shows the receive data sampling t iming when using a clock of 372 times the transfer rate. internal basic clock 372 clocks 186 clocks receive data (rxd) synchro- nization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 14-10 receive data sampling timing in smart card mode (using clock of 372 times the transfer rate)
section 14 smart card interface rev. 6.00 feb 22, 2005 page 532 of 1484 rej09b0103-0600 thus the reception margin in asynchronous mode is given by the following formula. formula for reception margin in smart card interface mode m = ? (0.5 ? 1 2n ) ? (l ? 0.5) f ? ? d ? 0.5 ? n (1 + f ) ? 100% where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. when d = 0.5 and f = 0, m = (0.5 ? 1/2 372) 100% = 49.866%
section 14 smart card interface rev. 6.00 feb 22, 2005 page 533 of 1484 rej09b0103-0600 retransfer operations (except block transfer mode): retransfer operations are performed by the sci in receive mode and transmit mode as described below. ? retransfer operation when sci is in receive mode figure 14-11 illustrates the retransfer operation when the sci is in receive mode. [1] if an error is found when the received parity bit is checked, the per bit in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the per bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [2] the rdrf bit in ssr is not set for a frame in which an error has occurred. [3] if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1. [4] if no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. if dtc * data transfer by an rxi source is enabled, the contents of rdr can be read automatically. when the rdr data is read by the dtc * , the rdrf flag is automatically cleared to 0. [5] when a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n + 1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [4] figure 14-11 retransfer operation in sci receive mode ? retransfer operation when sci is in transmit mode figure 14-12 illustrates the retransfer operation when the sci is in transmit mode. [6] if an error signal is sent back from the receiving end after transmission of one frame is completed, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri
section 14 smart card interface rev. 6.00 feb 22, 2005 page 534 of 1484 rej09b0103-0600 interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [7] the tend bit in ssr is not set for a frame for which an error signal indicating an abnormality is received. [8] if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. [9] if an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. if data transfer by the dtc * by means of the txi source is enabled, the next data can be written to tdr automatically. when data is written to tdr by the dtc * , the tdre bit is automatically cleared to 0. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n + 1 retransferred frame nth transfer frame tdre tend [6] fer/ers transfer to tsr from tdr [7] [9] [8] transfer to tsr from tdr transfer to tsr from tdr figure 14-12 retransfer operation in sci transmit mode
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 535 of 1484 rej09b0103-0600 section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) a two-channel i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630 (the product equipped with the i 2 c bus interface is the w-mask version). observe the following notes when using this option. a ?w? is added to the part number in products in which this optional function is used. examples: hd64f2638wf * note: * when the optional function is used in a u-mask version, ?u? is replaced with ?w?. example: hd64f2638uf hd64f2638wf 15.1 overview a two-channel i 2 c bus interface is available for the h8s/2638, h8s/2639, and h8s/2630 as an option. the i 2 c bus interface conforms to and provides a subset of the ph ilips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. each i 2 c bus interface channel uses only one data line (sda) and one clock line (scl) to transfer data, saving board and connector space. 15.1.1 features ? selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? serial format: non-addressing format without acknowledge bit, for master operation only ? conforms to philips i 2 c bus interface (i 2 c bus format) ? two ways of setting slave address (i 2 c bus format) ? start and stop conditions generated automatically in master mode (i 2 c bus format) ? selection of acknowledge output levels when receiving (i 2 c bus format) ? automatic loading of acknowledge bit when transmitting (i 2 c bus format) ? wait function in master mode (i 2 c bus format) ? a wait can be inserted by driving the scl pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 536 of 1484 rej09b0103-0600 ? wait function in slave mode (i 2 c bus format) ? a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible. ? three interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matches or the general call address is received in slave receive mode (i 2 c bus format) ? stop condition detection ? selection of 16 internal clocks (in master mode) ? direct bus drive (with scl and sda pins) ? two pins?p35/scl0 and p34/sda0?(normally nmos push-pull outputs) function as nmos open-drain outputs when the bus drive function is selected. ? two pins?p33/scl1 and p32/sda1?(normally cmos pins) function as nmos-only outputs when the bus drive function is selected. 15.1.2 block diagram figure 15-1 shows a block diagram of the i 2 c bus interface. figure 15-2 shows an example of i/o pin connections to external circuits. channel 0 i/o pins are nmos open drains, and it is possible to apply voltages in excess of the power supply (v cc ) voltage for this lsi. set the upper limit of voltage applied to the power supply (v cc ) power supply range + 0.3 v, i.e. 5.8 v. channel 1 i/o pins are driven solely by nmos, so in terms of appearance they carry out the same operations as an nmos open drain. however, the voltage which can be applied to the i/o pins depends on the voltage of the power supply (v cc ) of this lsi.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 537 of 1484 rej09b0103-0600 ps noise canceler noise canceler clock control bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register second slave address register x prescaler figure 15-1 block diagram of i 2 c bus interface
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 538 of 1484 rej09b0103-0600 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) chip scl sda v cc v cc scl sda figure 15-2 i 2 c bus interface connections (example: the chip as master) 15.1.3 input/output pins table 15-1 summarizes the input/output pins used by the i 2 c bus interface. table 15-1 i 2 c bus interface pins channel name abbreviation i/o function 0 serial clock scl0 i/o iic0 serial clock input/output serial data sda0 i/o iic0 serial data input/output 1 serial clock scl1 i/o iic1 serial clock input/output serial data sda1 i/o iic1 serial data input/output note: in the text, the channel subscript is omitted, and only scl and sda are used.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 539 of 1484 rej09b0103-0600 15.1.4 register configuration table 15-2 summarizes the registers of the i 2 c bus interface. table 15-2 register configuration channel name abbreviation r/w initial value address * 1 0i 2 c bus control register iccr0 r/w h'01 h 'ff78 * 3 i 2 c bus status register icsr0 r/w h'00 h'ff79 * 3 i 2 c bus data register icdr0 r/w ? h 'ff7e * 2 * 3 i 2 c bus mode register icmr0 r/w h'00 h'ff7f * 2 * 3 slave address register sar0 r/w h'00 h'ff7f * 2 * 3 second slave address register sarx0 r/w h'01 h'ff7e * 2 * 3 1i 2 c bus control register iccr1 r/w h'01 h 'ff80 * 3 i 2 c bus status register icsr1 r/w h'00 h'ff81 * 3 i 2 c bus data register icdr1 r/w ? h 'ff86 * 2 * 3 i 2 c bus mode register icmr1 r/w h'00 h'ff87 * 2 * 3 slave address register sar1 r/w h'00 h'ff87 * 2 * 3 second slave address register sarx1 r/w h'01 h'ff86 * 2 * 3 common serial control register x scrx r/w h'08 h'fdb4 ddc switch register ddcswr r/w h'0f h'fdb5 module stop control register b mstpcrb r/w h'ff h'fde9 notes: 1. lower 16 bits of the address. 2. the register that can be written or read depends on the ice bit in the i 2 c bus control register. the slave address register can be accessed when ice = 0, and the i 2 c bus mode register can be accessed when ice = 1. 3. the i 2 c bus interface registers are assigned to the same addresses as other registers. register selection is performed by means of the iice bit in the serial control register x (scrx).
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 540 of 1484 rej09b0103-0600 15.2 register descriptions 15.2.1 i 2 c bus data register (icdr) bit : initial value : r/w : 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w ? icdrr bit : initial value : r/w : 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r ? icdrs bit : initial value : r/w : 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrr5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? ? icdrt bit : initial value : r/w : 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w ? tdre, rdrf (internal flags) bit : initial value : r/w : ? rdrf 0 ? ? tdre 0 ?
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 541 of 1484 rej09b0103-0600 icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when r eceiving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and transmit buffer (icdrt). icdrs cannot be read or written by the cpu, icdrr is read-only, and icdrt is write-only. data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. if iic is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if iic is in receive mode and no previous data remains in icdrr (the rdrf flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr is assigned to the same address as sarx, and can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 542 of 1484 rej09b0103-0600 tdre description 0 the next transmit data is in icdr (icdrt), or transmission cannot (initial value) be started [clearing conditions] ? when transmit data is written in icdr (icdrt) in transmit mode (trs = 1) ? when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected ? when a stop condition is detected with the i 2 c bus format selected ? in receive mode (trs = 0) (a 0 write to trs during transfer is valid after reception of a frame containing an acknowledge bit) 1 the next transmit data can be written in icdr (icdrt) [setting conditions] ? in transmit mode (trs = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected ? when data is transferred from icdrt to icdrs (data transfer from icdrt to icdrs when trs = 1 and tdre = 0, and icdrs is empty) ? in receive mode (trs = 0), when a switch is made from slave receive mode (trs = 0) to transmit mode (trs = 1) after detection of a start condition (first time only) rdrf description 0 the data in icdr (icdrr) is invalid (initial value) [clearing condition] ? when icdr (icdrr) receive data is read in receive mode 1 the icdr (icdrr) receive data can be read [setting condition] ? when data is transferred from icdrs to icdrr (data transfer from icdrs to icdrr in case of normal termination with trs = 0 and rdrf = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 543 of 1484 rej09b0103-0600 15.2.2 slave address register (sar) bit : initial value : r/w : 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w sar is an 8-bit readable/writable register that stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sar is assigned to the same address as icmr, and can be written and read only when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 1?slave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0?format select (fs): used together with the fsx bit in sarx to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only the fs bit also specifies whether or not sar slave address recognition is performed in slave mode.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 544 of 1484 rej09b0103-0600 sar bit 0 sarx bit 0 fs fsx operating mode 00 i 2 c bus format ? sar and sarx slave addresses recognized 1i 2 c bus format (initial value) ? sar slave address recognized ? sarx slave address ignored 10 i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 synchronous serial format ? sar and sarx slave addresses ignored 15.2.3 second slave address register (sarx) bit : initial value : r/w : 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w sarx is an 8-bit readable/writable register that stores the second slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sarx is assigned to the same address as icdr, and can be written and read only when the ice bit is cleared to 0 in iccr. sarx is initialized to h'01 by a reset and in hardware standby mode. bits 7 to 1?second slave address (svax6 to svax0): set a unique address in bits svax6 to svax0, differing from the addresses of other slave devices connected to the i 2 c bus.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 545 of 1484 rej09b0103-0600 bit 0?format select x (fsx): used together with the fs bit in sar to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only the fsx bit also specifies whether or not sarx slave address recognition is performed in slave mode. for details, see the description of the fs bit in sar. 15.2.4 i 2 c bus mode register (icmr) bit : initial value : r/w : 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'00 by a reset and in hardware standby mode. bit 7?msb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. do not set this bit to 1 when the i 2 c bus format is used. bit 7 mls description 0 msb-first (initial value) 1 lsb-first
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 546 of 1484 rej09b0103-0600 bit 6?wait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. the setting of this bit is invalid in slave mode. bit 6 wait description 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 547 of 1484 rej09b0103-0600 bits 5 to 3?serial clock select (cks2 to cks0): these bits, together with the iicx1 (channel 1) or iicx0 (channel 0) bit in the scrx register, select the serial clock frequency in master mode. they should be set according to the required transfer rate. scrx bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0000 /28 179 khz 286 khz 357 khz 571 khz * 714 khz * 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz * 10 /48 104 khz 167 khz 208 khz 333 khz 417 khz * 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 100 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 10 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1000 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 10 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 100 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 10 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz note: * these rates are outside the ranges stipulated in the i 2 c bus interface specifications (normal mode: max. 100 khz, high-speed mode: max. 400 khz).
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 548 of 1484 rej09b0103-0600 bits 2 to 0?bit counter (bc2 to bc0): bits bc2 to bc0 specify the number of bits to be transferred next. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initialized to 000 by a reset and when a start condition is detected. the value returns to 000 at the end of a data transfer, including the acknowledge bit. bit 2 bit 1 bit 0 bits/frame bc2 bc1 bc0 synchronous serial format i 2 c bus format 0 0 0 8 9 (initial value) 11 2 10 2 3 13 4 100 4 5 15 6 10 6 7 17 8
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 549 of 1484 rej09b0103-0600 15.2.5 i 2 c bus control register (iccr) bit : initial value : r/w : note: * only 0 can be written, for flag clearing. 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * iccr is an 8-bit readable/writable register that enables or disables the i 2 c bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the i 2 c bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. iccr is initialized to h'01 by a reset and in hardware standby mode. bit 7?i 2 c bus interface enable (ice): selects whether or not the i 2 c bus interface is to be used. when ice is set to 1, port pins function as scl and sda input/output pins and transfer operations are enabled. when ice is cleared to 0, the i 2 c bus interface module is halted and its internal states are cleared. the sar and sarx registers can be accessed when ice is 0. the icmr and icdr registers can be accessed when ice is 1. bit 7 ice description 0i 2 c bus interface module disabled, with scl and sda signal pins set to port function (initial value) i 2 c bus interface module internal states initialized sar and sarx can be accessed 1i 2 c bus interface module enabled for transfer operations (pins scl and sca are driving the bus) icmr and icdr can be accessed
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 550 of 1484 rej09b0103-0600 bit 6?i 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6 ieic description 0 interrupts disabled (initial value) 1 interrupts enabled bit 5?master/slave select (mst) bit 4?transmit/receive select (trs) mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. in slave receive mode with the addressing format (fs = 0 or fsx = 0), hardware automatically selects transmit or receive mode according to the r/w bit in the first frame after a start condition. modification of the trs bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. mst and trs select the operating mode as follows. bit 5 bit 4 mst trs operating mode 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 551 of 1484 rej09b0103-0600 bit 5 mst description 0 slave mode (initial value) [clearing conditions] (1) when 0 is written by software (2) when bus arbitration is lost after transmission is started in i 2 c bus format master mode 1 master mode [setting conditions] (1) when 1 is written by software (in cases other than clearing condition (2)) (2) when 1 is written in mst after reading mst = 0 (in case of clearing condition (2)) bit 4 trs description 0 receive mode (initial value) [clearing conditions] (1) when 0 is written by software (in cases other than setting condition (3)) (2) when 0 is written in trs after reading trs = 1 (in case of clearing condition (3)) (3) when bus arbitration is lost after transmission is started in i 2 c bus format master mode 1 transmit mode [setting conditions] (1) when 1 is written by software (in cases other than clearing conditions (3) and 4) (2) when 1 is written in trs after reading trs = 0 (in case of clearing conditions (3) and 4) (3) when a 1 is received as the r/w bit of the first frame in i 2 c bus format slave mode
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 552 of 1484 rej09b0103-0600 bit 3?acknowledge bit judgement selection (acke): specifies whether the value of the acknowledge bit returned from the receiving device when using the i 2 c bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. when the acke bit is 0, the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. in this lsi, the dtc can be used to perform continuous transfer. the dtc is activated when the irtr interrupt flag is set to 1 (irtr is one of two interrupt flags, the other being iric). when the acke bit is 0, the tdre, iric, and irtr flags are set on completion of data transmission, regardless of the value of the acknowledge bit. when the acke bit is 1, the tdre, iric, and irtr flags are set on completion of data transmission when the acknowledge bit is 0, and the iric flag alone is set on completion of data transmission when the acknowledge bit is 1. when the dtc is activated, the tdre, iric, and irtr flags are cleared to 0 after the specified number of data transfers have been executed. consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the acke bit is set to 1, the dtc is not activated and an interrupt is generated, if enabled. depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. bit 3 acke description 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 553 of 1484 rej09b0103-0600 bit 2?bus busy (bbsy): the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. in master mode, this bit is also used to issue start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high transition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, use a mov instruction to write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode; the i 2 c bus interface must be set to master transmit mode before issuing a start condition. mst and trs should both be set to 1 before writing 1 in bbsy and 0 in scp. bit 2 bbsy description 0 bus is free (initial value) [clearing condition] ? when a stop condition is detected 1 bus is busy [setting condition] ? when a start condition is detected bit 1?i 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. iric is set at different times depending on the fs bit in sar and the wait bit in icmr. see section 15.3.7, iric setting timing and scl control. the c onditions under which iric is set also differ depending on the setting of the acke bit in iccr. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. when the dtc is used, iric is cleared automatically and transfer can be performed continuously without cpu intervention.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 554 of 1484 rej09b0103-0600 bit 1 iric description 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] ? when 0 is written in iric after reading iric = 1 ? when icdr is written or read by the dtc (when the tdre or rdrf flag is cleared to 0) (this is not always a clearing condition; see the description of dtc operation for details) 1 interrupt requested [setting conditions] i 2 c bus format master mode ? when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the end of data transfer (at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) ? when a slave address is received after bus arbitration is lost (when the al flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) i 2 c bus format slave mode ? when the slave address ( sva, svax) matches (w hen the aas and aasx flags are set to 1) ? and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when the general call address is detected (when fs = 0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1) synchronous serial format ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected when any other condition arises in which the tdre or rdrf flag is set to 1
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 555 of 1484 rej09b0103-0600 when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the tdre or rdrf internal flag is set, the readable irtr flag may or may not be set. the irtr flag (the dtc start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. the iric and irtr flags are not cleared at the end of the specified number of transfers in continuous transfer using the dtc. the tdre or rdrf flag is cleared, however, since the specified number of icdr reads or writes have been completed. table 15-3 shows the relationship between the flags and the transfer states.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 556 of 1484 rej09b0103-0600 table 15-3 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/01/0000000000 idle state (flag clearing required) 11000000000 start condition issuance 11100100000 start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 master mode wait 11/0100100000/1master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 arbitration lost 00100000100 sar match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 general call address match 00100010000 sarx match 01/0100000000/1 slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected bit 0?start condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. bit 0 scp description 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored (initial value)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 557 of 1484 rej09b0103-0600 15.2.6 i 2 c bus status register (icsr) bit : initial value : r/w : note: * only 0 can be written, for flag clearing. 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * icsr is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. icsr is initialized to h'00 by a reset and in hardware standby mode. bit 7?error stop condition detection flag (estp): indicates that a stop condition has been detected during frame transfer in i 2 c bus format slave mode. bit 7 estp description 0 no error stop condition (initial value) [clearing conditions] ? when 0 is written in estp after reading estp = 1 ? when the iric flag is cleared to 0 1in i 2 c bus format slave mode error stop condition detected [setting condition] ? when a stop condition is detected during frame transfer in other modes no meaning
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 558 of 1484 rej09b0103-0600 bit 6?normal stop condition detection flag (stop): indicates that a stop condition has been detected after completion of frame transfer in i 2 c bus format slave mode. bit 6 stop description 0 no normal stop condition (initial value) [clearing conditions] ? when 0 is written in stop after reading stop = 1 ? when the iric flag is cleared to 0 1in i 2 c bus format slave mode normal stop condition detected [setting condition] ? when a stop condition is detected after completion of frame transfer in other modes no meaning bit 5?i 2 c bus interface continuous transmission/reception interrupt request flag (irtr): indicates that the i 2 c bus interface has issued an interrupt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time. irtr flag setting is performed when the tdre or rdrf flag is set to 1. irtr is cleared by reading irtr after it has been set to 1, then writing 0 in irtr. irtr is also cleared automatically when the iric flag is cleared to 0.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 559 of 1484 rej09b0103-0600 bit 5 irtr description 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] ? when 0 is written in irtr after reading irtr = 1 ? when the iric flag is cleared to 0 1 continuous transfer state [setting conditions] ? in i 2 c bus interface slave mode when the tdre or rdrf flag is set to 1 when aasx = 1 ? in other modes when the tdre or rdrf flag is set to 1 bit 4?second slave address recognition flag (aasx): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. aasx is cleared by reading aasx after it has been set to 1, then writing 0 in aasx. aasx is also cleared automatically when a start condition is detected. bit 4 aasx description 0 second slave address not recognized (initial value) [clearing conditions] ? when 0 is written in aasx after reading aasx = 1 ? when a start condition is detected ? in master mode 1 second slave address recognized [setting condition] ? when the second slave address is detected in slave receive mode and fsx = 0
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 560 of 1484 rej09b0103-0600 bit 3?arbitration lost (al): this flag indicates that arbitration was lost in master mode. the i 2 c bus interface monitors the bus. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3 al description 0 bus arbitration won (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in al after reading al = 1 1 arbitration lost [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? if the internal scl line is high at the fall of scl in master transmit mode bit 2?slave address recognition flag (aas): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 561 of 1484 rej09b0103-0600 bit 2 aas description 0 slave address or general call address not recognized (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in aas after reading aas = 1 ? in master mode 1 slave address or general call address recognized [setting condition] ? when the slave address or general call address is detected in slave receive mode and fs = 0 bit 1?general call address recognition flag (adz): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 1 adz description 0 general call address not recognized (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in adz after reading adz = 1 ? in master mode 1 general call address recognized [setting condition] ? when the general call address is detected in slave receive mode and (fsx = 0 or fs = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 562 of 1484 rej09b0103-0600 bit 0?acknowledge bit (ackb): stores acknowledge data. in transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ackb. in receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. when this bit is read, in transmission (when trs = 1), the value loaded from the bus line (returned by the receiving device) is read. in reception (when trs = 0), the value set by internal software is read. in addition, when this bit is written to in reception the transmission acknowledge data setting is overwritten regardless of the value of trs. the value loaded from the reception device is maintained unchanged, so caution is necessary when using bit operation instructions to overwrite this register. bit 0 ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 563 of 1484 rej09b0103-0600 15.2.7 serial control register x (scrx) bit : initial value : r/w : 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 ? 1 r 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w scrx is an 8-bit readable/writable register that controls register access, the i 2 c interface operating mode. if a module controlled by scrx is not used, do not write 1 to the corresponding bit. scrx is initialized to h'08 by a reset and in hardware standby mode. bit 7?reserved: do not set 1. bit 6?i 2 c transfer select 1 (iicx1): this bit, together with bits cks2 to cks0 in icmr of iic1, selects the transfer rate in master mode. for details, see section 15.2.4, i 2 c bus mode register (icmr). bit 5?i 2 c transfer select 0 (iicx0): this bit, together with bits cks2 to cks0 in icmr of iic0, selects the transfer rate in master mode. for details, see section 15.2.4, i 2 c bus mode register (icmr). bit 4?i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data and control registers (iccr, icsr, icdr/sarx, icmr/sar). bit 4 iice description 0 cpu access to i 2 c bus interface data and control registers is disabled (initial value) 1 cpu access to i 2 c bus interface data and control registers is enabled bit 3? reserved: always returns a value of 1 if it is read. bits 2 to 0?reserved: do not set 1.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 564 of 1484 rej09b0103-0600 15.2.8 ddc switch register (ddcswr) bit : initial value : r/w : notes: 1. should always be written with 0. 2. always read as 1. 7 ? 0 r/(w) * 1 6 ? 0 r/(w) * 1 5 ? 0 r/(w) * 1 4 ? 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 ddcswr is an 8-bit readable/writable register that is used to initialize the iic module. ddcswr is initialized to h'0f by a reset and in hardware standby mode. bits 7 to 4?reserved: should always be written with 0. bits 3 to 0?iic clear 3 to 0 (clr3 to clr0): these bits control initialization of the internal state of iic0 and iic1. these bits can only be written to; if read they will always return a value of 1. when a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the iic module(s) is initialized. the write data for these bits is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. when clearing is required again, all the bits must be written to in accordance with the setting. bit 3 bit 2 bit 1 bit 0 clr3 clr2 clr1 clr0 description 0 0 ? ? setting prohibited 1 0 0 setting prohibited 1 iic0 internal latch cleared 1 0 iic1 internal latch cleared 1 iic0 and iic1 internal latches cleared 1 ? ? ? invalid setting
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 565 of 1484 rej09b0103-0600 15.2.9 module stop control register b (mstpcrb) 7 mstpb7 1 r/w bit : initial value : r/w : 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w mstpcrb is an 8-bit readable/writable register that perform module stop mode control. when the mstpb4 or mstpb3 bit is set to 1, operation of the corresponding iic channel is halted at the end of the bus cycle, and a transition is made to module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcrb is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 4?module stop (mstpb4): specifies iic channel 0 module stop mode. bit 4 mstpb4 description 0 iic channel 0 module stop mode is cleared 1 iic channel 0 module stop mode is set (initial value) bit 3?module stop (mstpb3): specifies iic channel 1 module stop mode. bit 3 mstpb3 description 0 iic channel 1 module stop mode is cleared 1 iic channel 1 module stop mode is set (initial value)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 566 of 1484 rej09b0103-0600 15.3 operation 15.3.1 i 2 c bus data format the i 2 c bus interface has serial and i 2 c bus formats. the i 2 c bus formats are addressing formats with an acknowledge bit. these are shown in figures 15-3 (a) and (b). the first frame following a start condition always consists of 8 bits. the serial format is a non-addressing format with no acknowledge bit. although start and stop conditions must be issued, this format can be used as a synchronous serial format. this is shown in figure 15-4. figure 15-5 shows the i 2 c bus timing. the symbols used in figures 15-3 to 15-5 are explained in table 15-4. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 111 n1 7 1 m1 s sla r/ w a data a/ a p 111 n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 15-3 i 2 c bus data formats (i 2 c bus formats)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 567 of 1484 rej09b0103-0600 s data data p 11 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 15-4 i 2 c bus data format (serial format) sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 15-5 i 2 c bus timing table 15-4 i 2 c bus data format symbols legend s start condition. the master device drives sda from high to low while scl is high sla slave address, by which the master device selects a slave device r/ w indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0 a acknowledge. the receiving device (the slave in master transmit mode, or the master in master receive mode) drives sda low to acknowledge a transfer data transferred data. the bit length is set by bits bc2 to bc0 in icmr. the msb-first or lsb-first format is selected by bit mls in icmr p stop condition. the master device drives sda from low to high while scl is high
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 568 of 1484 rej09b0103-0600 15.3.2 initial setting at startup the following procedure is used to initialize the iic. clear module stop start initialization set iice = 1 (scrx) set ice = 0 (iccr) set sar and sarx set ice = 1 (iccr) set icsr set scrx set imcr set iccr set mstp4 = 0 (iic0) mstp3 = 0 (iic1) (mstpcrb) enable cpu access by iic control register and data register enable sar and sarx access set transfer format for 1st slave address, 2nd slave address, and iic (sva8 ? sva0, fs, svax6 ? svax0, fsx) enable imcr and imdr access. use scl and sda pins is iic port set acknowledge bit (ackb) set transfer rate (iicx) set transfer format, wait insertion, and transfer rate (mls, wait, cks2 ? cks0) set interrupt enable, transfer mode, and acknowledge judgment (ieic, mst, trs, acke) transmit/receive start figure 15-6 flowchart for iic initialization (example) note: the icmr register should be written to only after transmit or receive operations have completed. writing to the icmr register while a transmit or receive operation is in progress could cause an erroneous value to be written to bit counter bits bc2 to bc0. this could result in improper operation. 15.3.3 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. figure 15-7 is a flowchart showing an example of the master transmit mode.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 569 of 1484 rej09b0103-0600 start initial settings write bbsy = 1 and scp = 0 (iccr) bbsy = 0? yes yes yes yes yes yes yes no no no [1] initial settings [2] determine status of scl and sda lines [3] set to master transmit mode [4] generate start condition [5] wait for start condition to be met [6] set 1st byte (slave address + r/w) transmit data (perform icdr write and iric flag clear operations continuously) [7] wait for end of 1 byte transmission [8] judge acknowledge signal from specified slave device [9] set transmit data for 2nd byte onward (perform icdr write and iric flag clear operations continuously) [10] wait for end of 1 byte transmission [11] judge end of transmission [12] generate stop condition. set mst = 1 and trs = 1 (iccr) read iric flag in iccr read iric flag in iccr clear iric flag in iccr write transmit data to icdr read bbsy flag in iccr read ackb bit in icsr iric = 1? no no no iric = 1? transmit mode? ackb = 0? clear iric flag in iccr write transmit data to icdr read iric flag in iccr read ackb bit in icsr clear iric flag in iccr transmit complete? (ackb = 1?) no iric = 1? write bbsy = 0 and scp = 0 (iccr) end master receive mode figure 15-7 flowchart for master transmit mode (example)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 570 of 1484 rej09b0103-0600 the procedure for transmitting data sequentially, synchronized with icdr (icdrt) write operations, is described below. [1] perform initial settings as described in section 15.3.2, initial setting. [2] read the bbsy flag in iccr to confirm that the bus is free. [3] set bits mst and tsr in iccr to 1 to switch to the master transmit mode. [4] write 1 to bbsy and 0 to scp in iccr. this changes sda from high to low when scl is high, and generates the start condition. [5] the iric and irtr flags are set to 1 when the start condition is generated. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. [6] after the start condition is detected, write the data (slave address + r/ w ) to icdr. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (r/w). next, clear the iric flag to 0 to indicate the end of the transfer. continue successively writing to icdr and clearing the iric flag to ensure that processing of other interrupts does not intervene. if the time required to transmit one byte of data elapses by the time the iric flag is cleared, it will not be possible to determine the end of the transmission. the master device sequentially sends the transmit clock and the data written to icdr. the selected slave device (i.e., the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. [7] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [8] read the ackb bit in icsr to confirm that its value is 0. if the slave device has not returned an acknowledge signal and the value of ackb is 1, perform the transmit end processing described in step [12] and then recommence the transmit operation from the beginning. [9] write the transmit data to icdr. next, clear the iric flag to 0 to indicate the end of the transfer. then continue successively writing to icdr and clearing the iric flag as described in step [6]. transmission of the next frame is synchronized with the internal clock. [10] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [11] read the ackb bit in icsr to confirm that the slave device has returned an acknowledge signal and the value of ackb is 0. if the slave device has not returned an acknowledge signal and the value of ackb is 1, perform the transmit end processing described in step [12]. [12] clear the iric flag to 0. write 0 to the acke bit in iccr and clear the received ackb bit to 0.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 571 of 1484 rej09b0103-0600 write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. 1 [5] r/ w [7] a 23456789 12 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 data 1 data 1 data 1 slave address generate start condition interrupt request interrupt request address + r/w address + r/w [9] iric clearance [9] icdr write [6] iric clearance [6] icdr write [4] write bbsy = 1 and scp = 0 (generate start condition) scl (master output) sda (master output) sda (slave output) icdre iric irtr icdrt icdrs user processing improper operation will result note: icdr data setting timing normal operation figure 15-8 example of master transmit mode operation timing (mls = wait = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 572 of 1484 rej09b0103-0600 [7] [10] a a 123456789 generate start condition 89 scl (master output) sda (master output) sda (slave output) icdre iric irtr icdr bit 7 bit 0 bit 6 data 2 data 2 data 1 data 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [12] write bbsy = 0 and scp = 0 (generate stop condition) [12] iric clearance [11] ackb read [9] iric clearance [9] icdr write user processing figure 15-9 example of master transmit mode stop condition generation timing (mls = wait = 0) 15.3.4 master receive operation in i 2 c bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the master device transmits the data containing the slave address + r/w (0: read) in the 1st frame after a start condition is generated in the master transmit mode. after the slave device is selected the switch to receive operation takes place. (1) receive operation using wait states figures 15-10 and 15-11 are flowcharts showing examples of the master receive mode (wait = 1).
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 573 of 1484 rej09b0103-0600 set wait = 1 (icmr) clear iric flag in iccr set ackb = 0 (icsr) set trs = 0 (iccr) read icdr clear iric flag in iccr read iric flag in iccr irtr = 1? iric = 1? no no yes yes no yes yes no yes no [1] set to receive mode [2] receive start, dummy read [5] read receive data [6] clear iric flag (cancel wait state) [7] set acknowledge data for final receive [8] wait time until trs setting [9] set trs to generate stop condition [10] read receive data [14] clear iric flag (cancel wait state) [16] read final receive data [15] cancel wait mode clear iric flag (iric flag should be cleared when wait = 0) [17] generate stop condition [13] data receive completed judgment [12] receive wait state (iric set at falling edge of 8th clock cycle) or wait for end of reception of 1 byte (iric set at rising edge of 9th clock cycle) [3] receive wait state (iric set at falling edge of 8th clock cycle) or wait for end of reception of 1 byte (iric set at rising edge of 9th clock cycle) [4] data receive completed judgment final receive? read icdr read icdr [11] clear iric flag (cancel wait state) clear iric flag in iccr set ackb = 1 (icsr) 1 clock cycle wait state set trs = 1 (iccr) read iric flag in iccr clear iric flag in iccr set wait = 0 (icmr) clear iric flag in iccr read icdr irtr = 1? iric = 1? write bbsy = 0 and scp = 0 (iccr) end master receive mode figure 15-10 flowchart for master receive mode (receiving multiple bytes) (wait = 1) (example)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 574 of 1484 rej09b0103-0600 set wait = 1 (icmr) clear iric flag in iccr set ackb = 0 (icsr) set trs = 0 (iccr) read icdr read iric flag in iccr iric = 1? no yes yes no [1] set to receive mode [2] receive start, dummy read [7] set acknowledge data for final receive [9] set trs to generate stop condition [11] clear iric flag (cancel wait state) [16] read final receive data [15] cancel wait mode clear iric flag (iric flag should be cleared when wait = 0) [17] generate stop condition [12] wait for end of reception of 1 byte (iric set at rising edge of 9th clock cycle) clear iric flag in iccr set ackb = 1 (icsr) set trs = 1 (iccr) read iric flag in iccr set wait = 0 (icmr) clear iric flag in iccr read icdr iric = 1? write bbsy = 0 and scp = 0 (iccr) end master receive mode [3] receive wait state (iric set at falling edge of 8th clock cycle) or wait for end of reception of 1 byte (iric set at rising edge of 9th clock cycle) figure 15-11 flowchart for master receive mode (receiving 1 byte) (wait = 1) (example) the procedure for receiving data sequentially, using the wait states (wait bit) for synchronization with icdr (icdrr) read operations, is described below. the procedure below describes the operation for receiving multiple bytes. note that some of the steps are omitted when receiving only 1 byte. refer to figure 15-11 for details.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 575 of 1484 rej09b0103-0600 [1] clear the trs bit in iccr to 0 to switch from transmit mode to receive mode. clear the ackb bit in icsr to 0 (acknowledge data setting). clear the iric flag to 0, then set the wait bit in icmr to 1. [2] when icdr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. [3] the iric flag is set to 1 by the following two conditions. at that point, an interrupt request is issued to the cpu if the ieic bit in iccr is set to 1. 1. the flag is set at the falling edge of the 8th clock cycle of the r eceive clock for 1 frame. scl is automatically held low, in synchronization with the internal clock, until the iric flag is cleared. 2. the flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. the iric flag and icdrf flag are set to 1, indicating that reception of 1 frame of data has ended. the master device continues to output the receive clock for the receive data. [4] read the irtr flag in icsr. if the irtr flag value is 0, the wait state is cancelled by clearing the iric flag as described in step [6] below. if the irtr flag value is 1 and the next receive data is the final receive data, perform the end processing described in step [7] below. [5] if the irtr flag value is 1, read the icdr receive data. [6] clear the irtr flag to 0. if condition [3]-1 is true, the master device drives sda to low level and returns an acknowledge signal when the receive clock outputs the 9th clock cycle. further data can be received by repeating steps [3] through [6]. [7] set the ackb bit in icsr to 1 to set the acknowledge data for the final receive. [8] wait for at least 1 clock cycle after the iric flag is set to 1 and then wait for the rising edge of the 1st clock cycle of the next receive data. [9] set the tsr bit in iccr to 1 to switch from the receive mode to the transmit mode. the tsr bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle is input. [10] read the icdr receive data. [11] clear the irtr flag to 0. [12] the iric flag is set to 1 by the following two conditions. 1. the flag is set at the falling edge of the 8th clock cycle of the r eceive clock for 1 frame. scl is automatically held low, in synchronization with the internal clock, until the iric flag is cleared. 2. the flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. the iric flag and icdrf flag are set to 1, indicating that reception of 1 frame of data has ended. the master device continues to output the receive clock for the receive data. [13] read the irtr flag in icsr. if the irtr flag value is 0, the wait state is cancelled by clearing the iric flag as described in step [14] below. if the irtr flag value is 1 and the
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 576 of 1484 rej09b0103-0600 receive operation has finished, perform the issue stop condition processing described in step [15] below. [14] if the irtr flag value is 0, clear the iric flag to 0 to cancel the wait state. return to reading the iric flag, as described in step [12], to detect the end of the receive operation. [15] clear the wait bit in icmr to 0 to cancel the wait mode. then clear the iric flag to 0. the iric flag should be cleared when the value of wait is 0 (the stop condition may not be output properly when the issue stop condition instruction is executed if the wait bit was cleared to 0 after the iric flag is cleared to 0). [16] read the final receive data in icdr. [17] write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. 1 9 a 2345 12345 678 9 data 1 data 1 master receive mode master transmit mode data 2 [3] [3] a [4] irtr = 1 [4] irtr = 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scl (master output) sda (slave output) sda (master output) iric irtr icdr user processing [1] trs cleared to 0 iric clearance [2] icdr read (dummy read) [6] iric clearance (cancel wait) [5] icdr read (data 1) [6] iric clearance figure 15-12 example of master receive mode operation timing (mls = ackb = 0, wait = 1)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 577 of 1484 rej09b0103-0600 9 82 1345678 9 a a data 2 data 3 data 3 data 2 data 1 [3] [3] [8] [12] [12] stop condition generated [4] irtr = 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 1 clock cycle wait time bit 7 [4] irtr = 1 [13] irtr = 1 [13] irtr = 0 [15] wait cleared to 0 iric clearance [14] iric clearance [11] iric clearance [6] iric clearance user processing [10] icdr read (data 2) [16] icdr read (data 3) [9] trs set to 1 [7] ackb set to 1 scl (master output) sda (slave output) sda (master output) iric irtr icdr [17] stop condition issued figure 15-13 example of master receive mode stop condition generation timing (mls = ackb = 0, wait = 1) 15.3.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the slave device compares its own address with the slave address in the first frame following the establishment of the start condition issued by the master device. if the addresses match, the slave device operates as the slave device designated by the master device. figure 15-14 is a flowchart showing an example of slave receive mode operation.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 578 of 1484 rej09b0103-0600 start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] last receive? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 0 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode [2] wait for the first byte to be received (slave address) [3] start receiving. the first read is a dummy read [4] wait for the transfer to end [5] set acknowledge data for the last receive [6] start the last receive [7] wait for the transfer to end [8] read the last receive data figure 15-14 flowchart for slave transmit mode (example)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 579 of 1484 rej09b0103-0600 the reception procedure and operations in slave receive mode are described below. (1) set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. (2) when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. (3) when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ w ) is 0, the trs bit in iccr remains cleared to 0, and slave receive operation is performed. (4) at the 9th clock pulse of the receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if the rdrf internal flag has been set to 1, the slave device drives scl low from the fall of the receive clock until data is read into icdr. (5) read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. receive operations can be performed continuously by repeating steps (4) and (5). when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 580 of 1484 rej09b0103-0600 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issuance scl (slave output) interrupt request generation address + r/ w address + r/ w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/ w figure 15-15 example of slave receive mode operation timing (1) (mls = ackb = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 581 of 1484 rej09b0103-0600 sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generation interrupt request generation data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a a figure 15-16 example of slave receive mode operation timing (2) (mls = ackb = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 582 of 1484 rej09b0103-0600 15.3.6 slave transmit operation in slave transmit operation, the slave device compares its own address with the slave address transmitted by the master device in the first frame (address r eceive frame) following detection of the start condition. if the addresses match and the 8th bit (r/w) is set to 1 (read), the trs bit in iccr is automatically set to 1 and slave transmit mode is activated. figure 15-17 is a flowchart showing an example of slave transmit mode operation. slave transmit mode write transmit data in icdr read iric in iccr iric = 1? clear iric in iccr clear iric in iccr clear iric in iccr read ackb in icsr set trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end [1] [2] [3] read icdr [5] [4] [1] set transmit data for the second and subsequent bytes [2] wait for 1 byte to be transmitted [3] test for end of transfer [4] select slave receive mode [5] dummy read (to release the scl line) figure 15-17 flowchart for slave receive mode (example)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 583 of 1484 rej09b0103-0600 in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. the transmission procedure and operations in slave transmit mode are described below. (1) set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. (2) when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th clock pulse and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the 8th data bit (r/ w ) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the tdrf flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written. (3) after clearing the iric flag to 0, write data to icdr. the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. after clearing the iric flag to 0, write the next data to icdr. the slave device sequentially sends the data written into icdr in accordance with the clock output by the master device at the timing shown in figure 15-18. (4) when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed normally. when the tdre internal flag is 0, the data written into icdr is transferred to icdrs, transmission is started, and the tdre internal flag and the iric and irtr flags are set to 1 again. (5) to continue transmission, clear the iric flag to 0, then write the next data to be transmitted into icdr. the tdre flag is cleared to 0. transmit operations can be performed continuously by repeating steps (4) and (5). to end transmission, write h'ff to icdr to release sda on the slave side. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 584 of 1484 rej09b0103-0600 sda (slave output) sda (slave output) sda (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generation interrupt request generation interrupt request generation slave receive mode slave transmit mode data 1 data 2 [3] iric clearance [5] iric clearance [3] icdr write [3] icdr write [3] icdr write user processing data 1 data 1 data 2 data 2 a r/ w a [4] [2] figure 15-18 example of slave transmit mode operation timing (mls = 0)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 585 of 1484 rej09b0103-0600 15.3.7 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 15-19 shows the iric set timing and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 1 a 7 1 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) clear iric write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 15-19 iric setting timing and scl control
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 586 of 1484 rej09b0103-0600 15.3.8 operation using the dtc the i 2 c bus format provides for selection of the slave device and transfer direction by means of the slave address and the r/ w bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. therefore, continuous data transfer using the dtc must be carried out in conjunction with cpu processing by means of interrupts. table 15-5 shows some examples of processing using the dtc. these examples assume that the number of transfer data bytes is known in slave mode. table 15-5 examples of operation using the dtc item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/ w bit transmission/ reception transmission by dtc (icdr write) transmission by cpu (icdr write) reception by cpu (icdr read) reception by cpu (icdr read) dummy data read ? processing by cpu (icdr read) ?? actual data transmission/ reception transmission by dtc (icdr write) reception by dtc (icdr read) transmission by dtc (icdr write) reception by dtc (icdr read) dummy data (h'ff) write ? ? processing by dtc (icdr write) ? last frame processing not necessary reception by cpu (icdr read) not necessary reception by cpu (icdr read) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: end condition issuance by cpu not necessary automatic clearing on detection of end condition during transmission of dummy data (h'ff) not necessary setting of number of dtc transfer data frames transmission: actual data count + 1 (+1 equivalent to slave address + r/ w bits) reception: actual data count transmission: actual data count + 1 (+1 equivalent to dummy data (h'ff)) reception: actual data count
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 587 of 1484 rej09b0103-0600 15.3.9 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 15-20 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 15-20 block diagram of noise canceler 15.3.10 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed by (1) setting bits clr3 to clr0 in the ddcswr register or (2) clearing the ice bit. for details of settings for bits clr3 to clr0, see section 15.2.8, ddc switch register (ddcswr). scope of initialization: the initialization executed by this function covers the following items: ? tdre and rdrf internal flags ? transmit/receive sequencer and internal operating clock counter ? internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.)
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 588 of 1484 rej09b0103-0600 the following items are not initialized: ? actual register values (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, and stcr) ? internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, icsr, and ddcswr registers ? the value of the icmr register bit counter (bc2 to bc0) ? generated interrupt sources (interrupt sources transferred to the interrupt controller) notes on initialization: ? interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. ? basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. ? when initialization is performed by means of the ddcswr register, the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. ? if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release t iming of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. 1. execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 2. execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbst bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 4. initialize (re-set) the iic registers.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 589 of 1484 rej09b0103-0600 15.4 usage notes ? in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition w ill be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. ? either of the following two conditions w ill start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read access to icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) ? table 15-6 shows the timing of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. table 15-6 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28 t cyc to 256 t cyc ns scl output high pulse width t sclho 0.5 t sclo ns figure 24-28 (reference) scl output low pulse width t scllo 0.5 t sclo ns sda output bus free time t bufo 0.5 t sclo ? 1 t cyc ns start condition output hold time t staho 0.5 t sclo ? 1 t cyc ns retransmission start condition output setup time t staso 1 t sclo ns stop condition output setup time t stoso 0.5 t sclo + 2 t cyc ns data output setup time (master) t sdaso 1 t scllo ? 3 t cyc ns data output setup time (slave) 1 t scll ? 3 t cyc data output hold time t sdaho 3 t cyc ns
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 590 of 1484 rej09b0103-0600 ? scl and sda input is sampled in synchronization with the internal clock. the ac t iming therefore depends on the system clock cycle t cyc , as shown in tables 24-19, 24-31, 24-43 in section 24, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. ? the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in the table 15-7. table 15-7 permissible scl rise time (t sr ) values time indication iicx t cyc indication i 2 c bus specification (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 7.5 t cyc standard mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 1 17.5 t cyc standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 591 of 1484 rej09b0103-0600 ? the i 2 c bus interface specifications for the scl and sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t scyc and t cyc , as shown in table 15-6. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 15-8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any frequency. the solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input t iming permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst-case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input t iming permits this output timing for use as slave devices connected to the i 2 c bus.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 592 of 1484 rej09b0103-0600 table 15-8 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz t sclho 0.5 t sclo (?t sr ) standard mode ?1000 4000 4000 4000 4000 4000 4000 high-speed mode ?300 600 950 950 950 950 950 t scllo 0.5 t sclo (?t sf ) standard mode ?250 4700 4750 4750 4750 4750 4750 high-speed mode ?250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo standard mode ?1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 0.5 t sclo ? 1 t cyc ( ?t sr ) high-speed mode ?300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 t staho standard mode ?250 4000 4550 4625 4650 4688 4700 0.5 t sclo ? 1 t cyc (?t sf ) high-speed mode ?250 600 800 875 900 938 950 t staso 1 t sclo (?t sr ) standard mode ?1000 4700 9000 9000 9000 9000 9000 high-speed mode ?300 600 2200 2200 2200 2200 2200 t stoso standard mode ?1000 4000 4400 4250 4200 4125 4100 0.5 t sclo + 2 t cyc (?t sr ) high-speed mode ?300 600 1350 1200 1150 1075 1050 t sdaso (master) standard mode ?1000 250 3100 3325 3400 3513 3550 1 t scllo * 2 ? 3 t cyc (?t sr ) high-speed mode ?300 100 400 625 700 813 850 t sdaso (slave) standard mode ?1000 250 3100 3325 3400 3513 3550 1 t scll * 2 ? 3 t cyc * 2 (?t sr ) high-speed mode ?300 100 400 625 700 813 850
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 593 of 1484 rej09b0103-0600 time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz t sdaho 3 t cyc standard mode 0 0 600 375 300 188 150 high-speed mode 0 0 600 375 300 188 150 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.). ? note on icdr read at end of master reception to halt reception at the end of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data w ill not be transferred to icdr, and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive data, first confirm that the bbsy bit in the iccr register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the icdr register with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/r eceive operating mode or settings, must be carried out during interval (a) in figure 15-18 (after confirming that the bbsy bit has been cleared to 0 in the iccr register).
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 594 of 1484 rej09b0103-0600 sda scl internal clock bbsy bit master receive mode icdr reading prohibited bit 0 a 8 9 stop condition (a) start condition execution of stop condition issuance instruction (0 written to bbsy and scp) confirmation of stop condition generation (0 read from bbsy) start condition issuance figure 15-21 points for attention concerning reading of master receive data
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 595 of 1484 rej09b0103-0600 ? notes on start condition issuance for retransmission figure 15-22 shows the timing of start c ondition issuance for retransmission, and the t iming for subsequently writing data to icdr, together with the corresponding flowchart. read scl pin write transmit data to icdr clear iric in icsr write bbsy = 1, scp = 0 (icsr) iric = 1 ? no scl = low ? no yes start condition issuance? no [1] [2] [3] [4] [5] note: program so that processing from [3] to [5] is executed continuously. [1] wait for end of 1-byte transfer [2] determine whether scl is low [3] issue restart condition instruction for retransmission [4] determine whether scl is high [5] set transmit data (slave address + r/ w ) other processing yes yes read scl pin scl = high ? no yes start condition (retransmission) scl bit 7 ack iric [1] iric determination determination of scl = low [2] [3] start condition instruction issuance [4] determination of scl = high [5] icdr write sda figure 15-22 flowchart and timing of start condition instruction issuance for retransmission
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 596 of 1484 rej09b0103-0600 ? notes on i 2 c bus interface stop condition instruction issuance if the rise time of the 9th scl acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives scl low to effect a wait, issue the stop condition instruction after reading scl and determining it to be low, as shown below. stop condition scl iric [1] determination of scl = low 9th clock vih high period secured [2] stop condition instruction issuance sda as waveform rise is late, scl is detected as low figure 15-23 timing of stop condition issuance ? notes on iric flag clearance when using wait function if the scl rise time exceeds the designated duration or if the slave device is of the type that keeps scl low and applies a wait state when the wait function is used in the master mode of the i 2 c bus interface, read scl and clear the iric flag after determining that scl has gone low, as shown below. clearing the iric flag to 0 when wait is set to 1 and scl is being held at high level can cause the sda value to change before scl goes low, resulting in a start condition or stop condition being generated erroneously. scl scl = high duration maintained [1] judgement that scl = low [2] iric clearance v ih sda iric scl = low detected figure 15-24 iric flag clearance in wait = 1 status
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 597 of 1484 rej09b0103-0600 ? notes on icdr reads and iccr access in slave transmit mode in a transmit operation in the slave mode of the i 2 c bus interface, do not read the icdr register or read or write to the iccr register during the period indicated by the shaded portion in figure 15-25. normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the icdr register or reading or writing to the iccr register. to ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (1) make sure that reading received data from the icdr register, or reading or writing to the iccr register, is completed before the next slave address receive operation starts. (2) monitor the bc2 to bc0 counter in the icmr register and, when the value of bc2 to bc0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the icdr register, or reading or writing to the iccr register. sda r/w waveforms if problem occurs bit 7 icdr write data transmission period when icdr reads and iccr reads and writes are prohibited (6 system clock cycles) detection of 9th clock cycle rising edge a 89 scl trs address received figure 15-25 icdr read and iccr access timing in slave transmit mode
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 598 of 1484 rej09b0103-0600 ? notes on trs bit setting in slave mode from the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next scl pin signal is detected (the period indicated as (a) in figure 15-26) in the slave mode of the i 2 c bus interface, the value set in the trs bit in the iccr register is effective immediately. however, at other times (indicated as (b) in figure 15-26) the value set in the trs bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. this results in the actual internal value of the trs bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. when receiving an address in the slave mode, clear the trs bit to 0 during the period indicated as (a) in figure 15-26. to cancel the holding of the scl bit low by the wait function in the slave mode, clear the trs bit to 0 and then perform a dummy read of the icdr register. (a) restart condition icdr dummy read detection of 9th clock cycle rising edge trs bit set detection of 9th clock cycle rising edge 89 (b) data transmission sda scl trs 123456789 a address reception trs bit setting hold time figure 15-26 trs bit setting timing in slave mode
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 599 of 1484 rej09b0103-0600 ? notes on icdr reads in transmit mode and icdr writes in receive mode when attempting to read icdr in the transmit mode (trs = 1) or write to icdr in the receive mode (trs = 0) under certain conditions, the scl pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the scl bus line before the icdr register access operation can take place properly. when accessing icdr, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. ? notes on acke bit and trs bit in slave mode when using the i 2 c bus interface, if an address is received in the slave mode immediately after 1 is received as an acknowledge bit (ackb = 1) in the transmit mode (trs = 1), an interrupt may be generated at the rising edge of the 9th clock cycle if the address does not match. when performing slave mode operations using the iic bus interface module, make sure to do the following. (1) when a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the acke bit in the iccr register to 0 to initialize the ackb bit to 0. (2) in the slave mode, change the setting to the receive mode (trs = 0) before the start condition is input. to ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 15-17. ? notes on arbitration lost in master mode the i 2 c bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. when arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the sar or sarx register as an address. if the receive data matches with the address in the sar or sarx register, the i 2 c bus interface erroneously recognizes that the address call has occurred. (see figure 15-27.) in multi-master mode, a bus conflict could happen. when the i 2 c bus interface is operated in master mode, check the state of the al bit in the icsr register every time after one frame of data has been transmitted or received. when arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures.
section 15 i 2 c bus interface [option] (only for the h8s/2638, h8s/2639, and h8s/2630) rev. 6.00 feb 22, 2005 page 600 of 1484 rej09b0103-0600 sa sla r/ w sa sla r/ w a data2 sa sla r/ w a sla r/ w a data3 a data4 data1 i 2 c bus interface (master transmit mode) transmit data match transmit timing match ? receive address is ignored automatically transferred to slave receive mode receive data is recognized as an address when the receive data matches to the address set in the sar or sarx register, the i 2 c bus interface operates as a slave device. arbitration is lost the al flag in icsr is set to 1 transmit data does not match other device (master transmit mode) i 2 c bus interface (slave receive mode) data contention figure 15-27 diagram of erroneous operation when arbitration is lost though it is prohibited in the normal i 2 c protocol, the same problem may occur when the mst bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. in multi-master mode, pay attention to the setting of the mst bit when a bus conflict may occur. in this case, the mst bit in the iccr register should be set to 1 according to the order below. (a) make sure that the bbsy flag in the iccr register is 0 and the bus is free before setting the mst bit. (b) set the mst bit to 1. (c) to confirm that the bus was not entered to the busy state while the mst bit is being set, check that the bbsy flag in the iccr register is 0 immediately after the mst bit has been set. note: above restriction can be cleared by setting bits fnc1 and fnc0 in the icxr register.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 601 of 1484 rej09b0103-0600 section 16 controller area network (hcan) notes: the h8s/2635 group is not equipped with a dtc. only a single hcan channel, hcan0, is implemented in the h8s/2635 group. 16.1 overview the hcan is a module for contro lling a controller area network (can) for realtime communication in vehicular and industrial equipment systems, etc. the chip has a 2-channel on- chip hcan module. reference: bosch can specification version 2.0, 1991, robert bosch gmbh 16.1.1 features ? can version: bosch 2.0b active compatible ? communication systems: nrz (non-return to zero) system (with bit-stuffing function) broadcast communication system ? transmission path: bidirectional 2-wire serial communication ? communication speed: max. 1 mbps ? data length: 0 to 8 bytes ? number of channel: 2 (hcan0, hcan1) ? data buffers: 16 per channel (one receive-only buffer and 15 buffers settable for transmission/reception) ? data transmission: choice of two methods: ? mailbox (buffer) number order (low-to-high) ? message priority (identifier) high-to-low order ? data reception: two methods: ? message identifier match (transmit/r eceive-setting buffers) ? reception with message identifier masked (receive-only) ? cpu interrupts: two interrupt vectors for 12 interrupt causes per channel: ? error interrupt ? reset processing interrupt ? message reception interrupt (mailbox 1 to 15) ? message reception interrupt (mailbox 0) ? message transmission interrupt
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 602 of 1484 rej09b0103-0600 ? hcan operating modes: support for various modes: ? hardware reset ? software reset ? normal status (error-active, error-passive) ? bus off status ? hcan configuration mode ? hcan sleep mode ? hcan halt mode ? other features: dtc can be activated by message reception mailbox (hcan mailbox 0 only)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 603 of 1484 rej09b0103-0600 16.1.2 block diagram figure 16-1 shows a block diagram of the hcan. peripheral address bus peripheral data bus htxd0 mbi message buffer hrxd0 mpi microprocessor interface (cdlc) can data link controller bosch can 2.0b active cpu interface control register status register hcan0 htxd1 mbi message buffer hrxd1 mpi microprocessor interface cpu interface control register status register hcan1 (cdlc) can data link controller bosch can 2.0b active tx buffer rx buffer message control message data mc0 to mc15, md0 to md15 lafm mailboxes lafm message control message data mc0 to mc15, md0 to md15 tx buffer rx buffer mailboxes figure 16-1 hcan block diagram
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 604 of 1484 rej09b0103-0600 message buffer interface (mbi): the mbi, consisting of mailboxes and a local acceptance filter mask (lafm), stores can transmit/receive messages (identifiers, data, etc.). transmit messages are written by the cpu. for receive messages, the data received by the cdlc is stored automatically. microprocessor interface (mpi): the mpi, consisting of a bus interface, control register, status register, etc., controls hcan internal data, statuses, and so forth. can data link controller (cdlc): the cdlc performs transmission and reception of messages conforming to the bosch can ver. 2.0b active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as crc checking, bus arbitration, and other functions. 16.1.3 pin configuration table 16-1 shows the hcan?s pins. when using hcan pins, settings must be made in the hcan configuration mode (during initialization: mcr0 = 1 and gsr3 = 1). table 16-1 hcan pins channel name abbreviation input/output function 0 hcan transmit data pin 0 htxd0 output channel 0 can bus transmission pin hcan receive data pin 0 hrxd0 input channel 0 can bus reception pin 1 * hcan transmit data pin 1 htxd1 output channel 1 can bus transmission pin hcan receive data pin 1 hrxd1 input channel 1 can bus reception pin note: * the hcan1 is not supported by the h8s/2635 and h8s/2634. a bus driver is necessary between the pins and the can bus. a ha13721 compatible model is recommended.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 605 of 1484 rej09b0103-0600 16.1.4 register configuration table 16-2 lists the hcan?s registers. table 16-2 hcan registers channel name abbre- viation r/w initial value address * 1 access size 0 master control register mcr r/w h'01 h'f800 8 bits 16 bits general status register gsr r/w h'0c h'f801 8 bits bit configuration register bcr r/w h'0000 h'f802 8/16 bits mailbox configuration register mbcr r/w h'0100 h'f804 8/16 bits transmit wait register txpr r/w h'0000 h'f806 8/16 bits transmit wait cancel register txcr r/w h'0000 h'f808 8/16 bits transmit acknowledge register txack r/w h'0000 h'f80a 8/16 bits abort acknowledge register aback r/w h' 0000 h'f80c 8/16 bits receive complete register rxpr r/w h'0000 h'f80e 8/16 bits remote request register rfpr r/w h'0000 h'f810 8/16 bits interrupt register irr r/w h'0100 h'f812 8/16 bits mailbox interrupt mask register mbimr r/w h'ffff h'f814 8/16 bits interrupt mask register imr r/w h'feff h'f816 8/16 bits receive error counter rec r h'00 h'f818 8 bits 16 bits transmit error counter tec r h'00 h'f819 8 bits unread message status register umsr r/w h'0000 h'f81a 8/16 bits local acceptance filter mask l lafml r/w h'0000 h'f81c 8/16 bits local acceptance filter mask h lafmh r/w h'0000 h'f81e 8/16 bits
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 606 of 1484 rej09b0103-0600 channel name abbreviation r/w initial value address * 1 access size 0 message control 0 [1:8] mc0 [1:8] r/w undefined h'f820 8/16 bits message control 1 [1:8] mc1 [1:8] r/w undefined h'f828 8/16 bits message control 2 [1:8] mc2 [1:8] r/w undefined h'f830 8/16 bits message control 3 [1:8] mc3 [1:8] r/w undefined h'f838 8/16 bits message control 4 [1:8] mc4 [1:8] r/w undefined h'f840 8/16 bits message control 5 [1:8] mc5 [1:8] r/w undefined h'f848 8/16 bits message control 6 [1:8] mc6 [1:8] r/w undefined h'f850 8/16 bits message control 7 [1:8] mc7 [1:8] r/w undefined h'f858 8/16 bits message control 8 [1:8] mc8 [1:8] r/w undefined h'f860 8/16 bits message control 9 [1:8] mc9 [1:8] r/w undefined h'f868 8/16 bits message control 10 [1:8] mc10 [1:8] r/w undefined h'f870 8/16 bits message control 11 [1:8] mc11 [1:8] r/w undefined h'f878 8/16 bits message control 12 [1:8] mc12 [1:8] r/w undefined h'f880 8/16 bits message control 13 [1:8] mc13 [1:8] r/w undefined h'f888 8/16 bits message control 14 [1:8] mc14 [1:8] r/w undefined h'f890 8/16 bits message control 15 [1:8] mc15 [1:8] r/w undefined h'f898 8/16 bits message data 0 [1:8] md0 [1:8] r/w undefined h'f8b0 8/16 bits message data 1 [1:8] md1 [1:8] r/w undefined h'f8b8 8/16 bits message data 2 [1:8] md2 [1:8] r/w undefined h'f8c0 8/16 bits message data 3 [1:8] md3 [1:8] r/w undefined h'f8c8 8/16 bits message data 4 [1:8] md4 [1:8] r/w undefined h'f8d0 8/16 bits message data 5 [1:8] md5 [1:8] r/w undefined h'f8d8 8/16 bits message data 6 [1:8] md6 [1:8] r/w undefined h'f8e0 8/16 bits message data 7 [1:8] md7 [1:8] r/w undefined h'f8e8 8/16 bits message data 8 [1:8] md8 [1:8] r/w undefined h'f8f0 8/16 bits message data 9 [1:8] md9 [1:8] r/w undefined h'f8f8 8/16 bits message data 10 [1:8] md10 [1:8] r/w undefined h'f900 8/16 bits message data 11 [1:8] md11 [1:8] r/w undefined h'f908 8/16 bits message data 12 [1:8] md12 [1:8] r/w undefined h'f910 8/16 bits message data 13 [1:8] md13 [1:8] r/w undefined h'f918 8/16 bits message data 14 [1:8] md14 [1:8] r/w undefined h'f920 8/16 bits message data 15 [1:8] md15 [1:8] r/w undefined h'f928 8/16 bits
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 607 of 1484 rej09b0103-0600 channel name abbre- viation r/w initial value address * 1 access size 1 * 2 master control register mcr r/w h'01 h'fa00 8 bits 16 bits general status register gsr r/w h'0c h'fa01 8 bits bit configuration register bcr r/w h'0000 h'fa02 8/16 bits mailbox configuration register mbcr r/w h'0100 h'fa04 8/16 bits transmit wait register txpr r/w h'0000 h'fa06 8/16 bits transmit wait cancel register txcr r/w h'0000 h'fa08 8/16 bits transmit acknowledge register txack r/w h'0000 h'fa0a 8/16 bits abort acknowledge register aback r/w h' 0000 h'fa0c 8/16 bits receive complete register rxpr r/w h'0000 h'fa0e 8/16 bits remote request register rfpr r/w h'0000 h'fa10 8/16 bits interrupt register irr r/w h'0100 h'fa12 8/16 bits mailbox interrupt mask register mbimr r/w h'ffff h'fa14 8/16 bits interrupt mask register imr r/w h'feff h'fa16 8/16 bits receive error counter rec r h'00 h'fa18 8 bits 16 bits transmit error counter tec r h'00 h'fa19 8 bits unread message status register umsr r/w h'0000 h'fa1a 8/16 bits local acceptance filter mask l lafml r/w h'0000 h'fa1c 8/16 bits local acceptance filter mask h lafmh r/w h'0000 h'fa1e 8/16 bits
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 608 of 1484 rej09b0103-0600 channel name abbreviation r/w initial value address * 1 access size 1 * 2 message control 0 [1:8] mc0 [1:8] r/w undefined h'fa20 8/16 bits message control 1 [1:8] mc1 [1:8] r/w undefined h'fa28 8/16 bits message control 2 [1:8] mc2 [1:8] r/w undefined h'fa30 8/16 bits message control 3 [1:8] mc3 [1:8] r/w undefined h'fa38 8/16 bits message control 4 [1:8] mc4 [1:8] r/w undefined h'fa40 8/16 bits message control 5 [1:8] mc5 [1:8] r/w undefined h'fa48 8/16 bits message control 6 [1:8] mc6 [1:8] r/w undefined h'fa50 8/16 bits message control 7 [1:8] mc7 [1:8] r/w undefined h'fa58 8/16 bits message control 8 [1:8] mc8 [1:8] r/w undefined h'fa60 8/16 bits message control 9 [1:8] mc9 [1:8] r/w undefined h'fa68 8/16 bits message control 10 [1:8] mc10 [1:8] r/w undefined h'fa70 8/16 bits message control 11 [1:8] mc11 [1:8] r/w undefined h'fa78 8/16 bits message control 12 [1:8] mc12 [1:8] r/w undefined h'fa80 8/16 bits message control 13 [1:8] mc13 [1:8] r/w undefined h'fa88 8/16 bits message control 14 [1:8] mc14 [1:8] r/w undefined h'fa90 8/16 bits message control 15 [1:8] mc15 [1:8] r/w undefined h'fa98 8/16 bits message data 0 [1:8] md0 [1:8] r/w undefined h'fab0 8/16 bits message data 1 [1:8] md1 [1:8] r/w undefined h'fab8 8/16 bits message data 2 [1:8] md2 [1:8] r/w undefined h'fac0 8/16 bits message data 3 [1:8] md3 [1:8] r/w undefined h'fac8 8/16 bits message data 4 [1:8] md4 [1:8] r/w undefined h'fad0 8/16 bits message data 5 [1:8] md5 [1:8] r/w undefined h'fad8 8/16 bits message data 6 [1:8] md6 [1:8] r/w undefined h'fae0 8/16 bits message data 7 [1:8] md7 [1:8] r/w undefined h'fae8 8/16 bits message data 8 [1:8] md8 [1:8] r/w undefined h'faf0 8/16 bits message data 9 [1:8] md9 [1:8] r/w undefined h'faf8 8/16 bits message data 10 [1:8] md10 [1:8] r/w undefined h'fb00 8/16 bits message data 11 [1:8] md11 [1:8] r/w undefined h'fb08 8/16 bits message data 12 [1:8] md12 [1:8] r/w undefined h'fb10 8/16 bits message data 13 [1:8] md13 [1:8] r/w undefined h'fb18 8/16 bits message data 14 [1:8] md14 [1:8] r/w undefined h'fb20 8/16 bits message data 15 [1:8] md15 [1:8] r/w undefined h'fb28 8/16 bits all module stop control register c mstpcrc r/w h'ff h'fdea 8/16 bits notes: 1. lower 16 bits of the address. 2. the hcan1 is not supported by the h8s/2635 and h8s/2634.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 609 of 1484 rej09b0103-0600 16.2 register descriptions 16.2.1 master control register (mcr) the master control register (mcr) is an 8-bit readable/writable register that controls the can interface. mcr bit:76543210 mcr7 ? mcr5 ? ? mcr2 mcr1 mcr0 initial value:00000001 r/w: r/w r r/w r r r/w r/w r/w bit 7?hcan sleep mode release (mcr7): enables or disables hcan sleep mode release by bus operation. bit 7: mcr7 description 0 hcan sleep mode release by can bus operation disabled (initial value) 1 hcan sleep mode release by can bus operation enabled bit 6?reserved: this bit always reads 0. the write value should always be 0. bit 5?hcan sleep mode (mcr5): enables or disables hcan sleep mode transition. bit 5: mcr5 description 0 hcan sleep mode released (initial value) 1 transition to hcan sleep mode enabled bits 4 and 3?reserved: these bits always read 0. the write value should always be 0. bit 2?message transmission method (mcr2): selects the transmission method for transmit messages. bit 2: mcr2 description 0 transmission order determined by message identifier priority (initial value) 1 transmission order determined by mailbox (buffer) number priority (txpr1 > txpr15)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 610 of 1484 rej09b0103-0600 bit 1?halt request (mcr1): controls halting of the hcan module. bit 1: mcr1 description 0 hcan normal operating mode (initial value) 1 hcan halt mode transition request bit 0?reset request (mcr0): controls resetting of the hcan module. bit 0: mcr0 description 0 normal operating mode (mcr0 = 0 and gsr3 = 0) [setting condition] ? when 0 is written after an hcan reset 1 hcan reset mode transition request (initial value) in order for gsr3 to change from 1 to 0 after 0 is written to mcr0, time is required before the hcan is internally reset. there is consequently a delay before gsr3 is cleared to 0 after mcr0 is cleared to 0. 16.2.2 general status register (gsr) the general status register (gsr) is an 8-bit readable register that indicates the status of the can bus. gsr bit:76543210 ????gsr3gsr2gsr1gsr0 initial value:00001100 r/w:rrrrrrrr bits 7 to 4?reserved: these bits always read 0.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 611 of 1484 rej09b0103-0600 bit 3?reset status bit (gsr3): indicates whether the hcan module is in the normal operating state or the reset state. writes are invalid. bit 3: mcr3 description 0 normal operating state [setting condition] ? after an hcan internal reset 1 configuration mode [reset condition] ? mcr0 reset mode and sleep mode (initial value) bit 2?message transmission status flag (gsr2): flag that indicates whether the module is currently in the message transmission period. the ?message transmission period? is the period from the start of message transmission (sof) until the end of a 3-bit intermission interval after eof (end of frame). writes are invalid. bit 2: gsr2 description 0 message transmission period 1 [reset condition] (initial value) ? idle period bit 1?transmit/receive warning flag (gsr1): flag that indicates an error warning. writes are invalid. bit 1: gsr1 description 0 [reset condition] ? when tec < 96 and rec < 96 or tec 256 (initial value) 1 when tec 96 or rec 96 bit 0?bus off flag (gsr0): flag that indicates the bus off state. writes are invalid. bit 0: gsr0 description 0 [reset condition] ? recovery from bus off state (initial value) 1 when tec 256 (bus off state)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 612 of 1484 rej09b0103-0600 16.2.3 bit configuration register (bcr) the bit configuration register (bcr) is a 16-bit readable/writable register that is used to set can bit timing parameters and the baud rate prescaler. bcr bit: 15 14 13 12 11 10 9 8 bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 bcr15 bcr14 bcr13 bcr12 bcr11 bcr10 bcr9 bcr8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14?resynchronization jump width (sjw): these bits set the bit synchronization range. bit 15: bcr7 bit 14: bcr6 description 0 0 bit synchronization width = 1 time quantum (initial value) 1 bit synchronization width = 2 time quanta 1 0 bit synchronization width = 3 time quanta 1 bit synchronization width = 4 time quanta bits 13 to 8?baud rate prescaler (brp): these bits are used to set the can bus baud rate. bit 13: bcr5 bit 12: bcr4 bit 11: bcr3 bit 10: bcr2 bit 9: bcr1 bit 8: bcr0 description 0000002 system clock (initial value) 0000014 system clock 0000106 system clock ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 128 system clock
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 613 of 1484 rej09b0103-0600 bit 7?bit sample point (bsp): sets the point at which data is sampled. bit 7: bcr15 description 0 bit sampling at one point (end of time segment 1 (tseg1)) (initial value) 1 bit sampling at three points (end of time segment 1 (tseg1) and preceding and following time quanta) bits 6 to 4?time segment 2 (tseg2): these bits are used to set the segment for correcting 1- bit time error. a value from 2 to 8 can be set. bit 6: bcr14 bit 5: bcr13 bit 4: bcr12 description 0 0 0 setting prohibited (initial value) 1 tseg2 = 2 time quanta 1 0 tseg2 = 3 time quanta 1 tseg2 = 4 time quanta 1 0 0 tseg2 = 5 time quanta 1 tseg2 = 6 time quanta 1 0 tseg2 = 7 time quanta 1 tseg2 = 8 time quanta bits 3 to 0?time segment 1 (tseg1): these bits are used to set the segment for absorbing output buffer, can bus, and input buffer delay. a value from 1 to 16 can be set. bit 3: bcr11 bit 2: bcr10 bit 1: bcr9 bit 0: bcr8 description 0 0 0 0 setting prohibited (initial value) 0 0 0 1 setting prohibited 0 0 1 0 setting prohibited 0 0 1 1 tseg1 = 4 time quanta 0 1 0 0 tseg1 = 5 time quanta ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 tseg1 = 16 time quanta
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 614 of 1484 rej09b0103-0600 16.2.4 mailbox configuration register (mbcr) the mailbox configuration register (mbcr) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. mbcr bit: 15 14 13 12 11 10 9 8 mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? initial value:00000001 r/w: r/w r/w r/w r/w r/w r/w r/w r bit:76543210 mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 9 and 7 to 0?mailbox setting register (mbcr7 to mbcr1, mbcr15 to mbcr8): these bits set the polarity of the corresponding mailboxes. bit x: mbcrx description 0 corresponding mailbox is set for transmission (initial value) 1 corresponding mailbox is set for reception (x = 15 to 9, 7 to 0) bit 8?reserved: this bit always reads 1. the write value should always be 1.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 615 of 1484 rej09b0103-0600 16.2.5 transmit wait register (txpr) the transmit wait register (txpr) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (can bus arbitration wait). txpr bit: 15 14 13 12 11 10 9 8 txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r bit:76543210 txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 9 and 7 to 0?transmit wait register (txpr7 to txpr1, txpr15 to txpr8): these bits set a transmit wait for the corresponding mailboxes. bit x: txprx description 0 transmit message idle state in corresponding mailbox (initial value) [clearing condition] ? message transmission completion and cancellation completion 1 transmit message transmit wait in corresponding mailbox (can bus arbitration) (x = 15 to 9, 7 to 0) bit 8?reserved: this bit always reads 0. the write value should always be 0.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 616 of 1484 rej09b0103-0600 16.2.6 transmit wait cancel register (txcr) the transmit wait cancel register (txcr) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). txcr bit: 15 14 13 12 11 10 9 8 txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r bit:76543210 txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w (x = 15 to 9, 7 to 0) bits 15 to 9 and 7 to 0?transmit wait cancel register (txcr7 to txcr1, txcr15 to txcr8): these bits control cancellation of transmit wait messages in the corresponding hcan mailboxes. bit x: txcrx description 0 transmit message cancellation idle state in corresponding mailbox (initial value) [clearing condition] ? completion of txpr clearing (when transmit message is canceled normally) 1 txpr cleared for corresponding mailbox (transmit message cancellation) (x = 15 to 9, 7 to 0) bit 8?reserved: this bit always reads 0. the write value should always be 0.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 617 of 1484 rej09b0103-0600 16.2.7 transmit acknowledge register (txack) the transmit acknowledge register (txack) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. txack bit: 15 14 13 12 11 10 9 8 txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r bit:76543210 txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only a write of 1 is permitted, to clear the flag. bits 15 to 9 and 7 to 0?transmit acknowledge register (txack7 to txack1, txack15 to txack8): these bits indicate that a transmit message in the corresponding hcan mailbox has been transmitted normally. bit x: txackx description 0 [clearing condition] ? writing 1 (initial value) 1 completion of message transmission for corresponding mailbox (x = 15 to 9, 7 to 0) bit 8?reserved: this bit always reads 0. the write value should always be 0.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 618 of 1484 rej09b0103-0600 16.2.8 abort acknowledge register (aback) the abort acknowledge register (aback) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. aback bit: 15 14 13 12 11 10 9 8 aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r bit:76543210 aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only a write of 1 is permitted, to clear the flag. bits 15 to 9 and 7 to 0?abort acknowledge register (aback7 to aback1, aback15 to aback8): these bits indicate that a transmit message in the corresponding mailbox has been canceled (aborted) normally. bit x: abackx description 0 [clearing condition] ? writing 1 (initial value) 1 completion of transmit message cancellation for corresponding mailbox (x = 15 to 9, 7 to 0) bit 8?reserved: this bit always reads 0. the write value should always be 0.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 619 of 1484 rej09b0103-0600 16.2.9 receive complete register (rxpr) the receive complete register (rxpr) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). in the case of remote frame reception, the corresponding remote request register (rfpr) is also set simultaneously. rxpr bit: 15 14 13 12 11 10 9 8 rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * bit:76543210 rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only a write of 1 is permitted, to clear the flag. bits 15 to 0?receive complete register (rxpr7 to rxpr0, rxpr15 to rxpr8): these bits indicate that a receive message has been received normally in the corresponding mailbox. bit x: rxprx description 0 [clearing condition] ? writing 1 (initial value) 1 completion of message (data frame or remote frame) reception in corresponding mailbox (x = 15 to 0)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 620 of 1484 rej09b0103-0600 16.2.10 remote request register (rfpr) the remote request register (rfpr) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). when a bit in this register is set, the corresponding reception complete bit is set simultaneously. rfpr bit: 15 14 13 12 11 10 9 8 rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * bit:76543210 rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only a write of 1 is permitted, to clear the flag. bits 15 to 0?remote request register (rfpr7 to rfpr0, rfpr15 to rfpr8): these bits indicate that a remote frame has been received normally in the corresponding mailbox. bit x: rfprx description 0 [clearing condition] ? writing 1 (initial value) 1 completion of remote frame reception in corresponding mailbox (x = 15 to 0)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 621 of 1484 rej09b0103-0600 16.2.11 interrupt register (irr) the interrupt register (irr) is a 16-bit readable/writable register containing status flags for the various interrupt sources. irr bit: 15 14 13 12 11 10 9 8 irr7 irr6 irr5 irr4 irr3 irr2 irr1 irr0 initial value:00000001 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/(w) * bit:76543210 ? ? ? irr12 ? ? irr9 irr8 initial value:00000000 r/w: ? ? ? r/(w) * ?? rr/(w) * note: * only a write of 1 is permitted, to clear the flag. bit 15?overload frame interrupt flag (irr7): status flag indicating that the hcan has transmitted an overload frame. bit 15: irr7 description 0 [clearing condition] ? writing 1 (initial value) 1 overload frame transmission [setting condition] ? when overload frame is transmitted
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 622 of 1484 rej09b0103-0600 bit 14?bus off interrupt flag (irr6): status flag indicating the bus off state caused by the transmit error counter. bit 14: irr6 description 0 [clearing condition] ? writing 1 (initial value) 1 bus off state caused by transmit error [setting condition] ? when tec 256 bit 13?error passive interrupt flag (irr5): status flag indicating the error passive state caused by the transmit/receive error counter. bit 13: irr5 description 0 [clearing condition] ? writing 1 (initial value) 1 error passive state caused by transmit/receive error [setting condition] ? when tec 128 or rec 128 bit 12?receive overload warning interrupt flag (irr4): status flag indicating the error warning state caused by the receive error counter. bit 12: irr4 description 0 [clearing condition] ? writing 1 (initial value) 1 error warning state caused by receive error [setting condition] ? when rec 96
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 623 of 1484 rej09b0103-0600 bit 11?transmit overload warning interrupt flag (irr3): status flag indicating the error warning state caused by the transmit error counter. bit 11: irr3 description 0 [clearing condition] ? writing 1 (initial value) 1 error warning state caused by transmit error [setting condition] ? when tec 96 bit 10?remote frame request interrupt flag (irr2): status flag indicating that a remote frame has been received in a mailbox (buffer). bit 10: irr2 description 0 [clearing condition] ? clearing of all bits in rfpr (remote request register) of mailbox for which receive interrupt requests are enabled by mbimr (initial value) 1 remote frame received and stored in mailbox [setting conditions] ? when remote frame reception is completed, when corresponding mbimr = 0 bit 9?receive message interrupt flag (irr1): status flag indicating that a mailbox (buffer) receive message has been received normally. bit 9: irr1 description 0 [clearing condition] ? clearing of all bits in rxpr (receive complete register) of mailbox for which receive interrupt requests are enabled by mbimr (initial value) 1 data frame or remote frame received and stored in mailbox [setting conditions] ? when data frame or remote frame reception is completed, when corresponding mbimr = 0
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 624 of 1484 rej09b0103-0600 bit 8?reset interrupt flag (irr0): status flag indicating that the hcan module has been reset. this bit cannot be masked in the interrupt mask register (imr). if this bit is not cleared after reset input or recovery from software standby mode, interrupt handling will be performed as soon as interrupts are enabled by the interrupt controller. bit 8: irr0 description 0 [clearing condition] ? writing 1 1 hardware reset (hcan module stop * , software standby) (initial value) [setting condition] ? when reset processing is completed after a hardware reset (hcan module stop * , software standby) note: * after reset or hardware standby release, the module stop bit is initialized to 1, and so the hcan enters the module stop state. bits 7 to 5, 3, and 2?reserved: these bits always read 0. the write value should always be 0. bit 4?bus operation interrupt flag (irr12): status flag indicating detection of a dominant bit due to bus operation when the hcan module is in hcan sleep mode. bit 4: irr12 description 0 can bus idle state (initial value) [clearing condition] ? writing 1 1 can bus operation in hcan sleep mode [setting condition] ? bus operation (dominant bit detection) in hcan sleep mode
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 625 of 1484 rej09b0103-0600 bit 1?unread interrupt flag (irr9): status flag indicating that a receive message has been overwritten while still unread. bit 1: irr9 description 0 [clearing condition] ? clearing of all bits in umsr (unread message status register) (initial value) 1 unread message overwrite [setting condition] ? when umsr (unread message status register) is set bit 0?mailbox empty interrupt flag (irr8): status flag indicating that the next transmit message can be stored in the mailbox. bit 0: irr8 description 0 [clearing condition] ? writing 1 (initial value) 1 transmit message has been transmitted or aborted, and new message can be stored [setting condition] ? when txpr (transmit wait register) is cleared by completion of transmission or completion of transmission abort
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 626 of 1484 rej09b0103-0600 16.2.12 mailbox interrupt mask register (mbimr) the mailbox interrupt mask register (mbimr) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. mbimr bit: 15 14 13 12 11 10 9 8 mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?mailbox interrupt mask (mbimrx): flags that enable or disable individual mailbox interrupt requests. bit x: mbimrx description 0 [transmitting] ? interrupt request to cpu due to txpr clearing [receiving] ? interrupt request to cpu due to rxpr setting 1 interrupt requests to cpu disabled (initial value) (x = 15 to 0)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 627 of 1484 rej09b0103-0600 16.2.13 interrupt mask register (imr) the interrupt mask register (imr) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. imr bit: 15 14 13 12 11 10 9 8 imr7 imr6 imr5 imr4 imr3 imr2 imr1 ? initial value:11111110 r/w: r/w r/w r/w r/w r/w r/w r/w r bit:76543210 ? ? ? imr12 ? ? imr9 imr8 initial value:11111111 r/w: r r r r/w r r r/w r/w bit 15?overload frame/bus off recovery interrupt mask (imr7): enables or disables overload frame/bus off recovery interrupt requests. bit 15: imr7 description 0 overload frame/bus off recovery interrupt request (ovr0) to cpu by irr7 enabled 1 overload frame/bus off recovery interrupt request (ovr0) to cpu by irr7 disabled (initial value) bit 14?bus off interrupt mask (imr6): enables or disables bus off interrupt requests caused by the transmit error counter. bit 14: imr6 description 0 bus off interrupt request (ers0) to cpu by irr6 enabled 1 bus off interrupt request (ers0) to cpu by irr6 disabled (initial value)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 628 of 1484 rej09b0103-0600 bit 13?error passive interrupt mask (imr5): enables or disables error passive interrupt requests caused by the transmit/receive error counter. bit 13: imr5 description 0 error passive interrupt request (ers0) to cpu by irr5 enabled 1 error passive interrupt request (ers0) to cpu by irr5 disabled (initial value) bit 12?receive overload warning interrupt mask (imr4): enables or disables error warning interrupt requests caused by the receive error counter. bit 12: imr4 description 0 rec error warning interrupt request (ovr0) to cpu by irr4 enabled 1 rec error warning interrupt request (ovr0) to cpu by irr4 disabled (initial value) bit 11?transmit overload warning interrupt mask (imr3): enables or disables error warning interrupt requests caused by the transmit error counter. bit 11: imr3 description 0 tec error warning interrupt request (ovr0) to cpu by irr3 enabled 1 tec error warning interrupt request (ovr0) to cpu by irr3 disabled (initial value) bit 10?remote frame request interrupt mask (imr2): enables or disables remote frame reception interrupt requests. bit 10: imr2 description 0 remote frame reception interrupt request (ovr0) to cpu by irr2 enabled 1 remote frame reception interrupt request (ovr0) to cpu by irr2 disabled (initial value)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 629 of 1484 rej09b0103-0600 bit 9?receive message interrupt mask (imr1): enables or disables message reception interrupt requests. bit 9: imr1 description 0 message reception interrupt request (rm1) to cpu by irr1 enabled 1 message reception interrupt request (rm1) to cpu by irr1 disabled (initial value) bit 8?reserved: the reset flag cannot be masked. this bit always reads 0. the write value should always be 0. bits 7 to 5, 3, and 2?reserved: these bits always read 1. the write value should always be 1. bit 4?bus operation interrupt mask (imr12): enables or disables interrupt requests due to bus operation in sleep mode. bit 4: imr12 description 0 bus operation interrupt request (ovr0) to cpu by irr12 enabled 1 bus operation interrupt request (ovr0) to cpu by irr12 disabled (initial value) bit 1?unread interrupt mask (imr9): enables or disables unread receive message overwrite interrupt requests. bit 1: imr9 description 0 unread message overwrite interrupt request (ovr0) to cpu by irr9 enabled 1 unread message overwrite interrupt request (ovr0) to cpu by irr9 disabled (initial value) bit 0?mailbox empty interrupt mask (imr8): enables or disables mailbox empty interrupt requests. bit 0: imr8 description 0 mailbox empty interrupt request (sle0) to cpu by irr8 enabled 1 mailbox empty interrupt request (sle0) to cpu by irr8 disabled (initial value)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 630 of 1484 rej09b0103-0600 16.2.14 receive error counter (rec) the receive error counter (rec) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the can bus. the count value is stipulated in the can protocol. rec bit:76543210 initial value:00000000 r/w:rrrrrrrr 16.2.15 transmit error counter (tec) the transmit error counter (tec) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the can bus. the count value is stipulated in the can protocol. tec bit:76543210 initial value:00000000 r/w:rrrrrrrr
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 631 of 1484 rej09b0103-0600 16.2.16 unread message status register (umsr) the unread message status register (umsr) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. when a message is overwritten by a new receive message, the old data is lost. umsr bit: 15 14 13 12 11 10 9 8 umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * bit:76543210 umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 1 can be written, to clear the flag to 0. bits 15 to 0?unread message status flags (umsrx): status flags indicating that an unread receive message has been overwritten. bit x: umsrx description 0 [clearing condition] ? writing 1 (initial value) 1 unread receive message is overwritten by a new message [setting condition] ? when a new message is received before rxpr is cleared
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 632 of 1484 rej09b0103-0600 16.2.17 local acceptance filter masks (lafml, lafmh) the local acceptance filter masks (lafml, lafmh) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (mc0, md0) according to the identifier. in these registers, consist of lafmh15: msb to lafmh5: lsb are 11 standard/extended identifier bits, and lafmh1: msb to lafml0: lsb are 18 extended identifier bits. lafml bit: 15 14 13 12 11 10 9 8 lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w lafmh bit: 15 14 13 12 11 10 9 8 lafmh7 lafmh6 lafmh5 ??? lafmh1 lafmh0 initial value:00000000 r/w: r/w r/w r/w r r r r/w r/w bit:76543210 lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 633 of 1484 rej09b0103-0600 lafmh bits 7 to 0 and 15 to 13?11-bit identifier filter (lafmh7 to lafmh5, lafmh15 to lafmh8): filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). bit x: lafmhx description 0 stored in mc0 and md0 (receive-only mailbox) depending on bit match between mc0 message identifier and receive message identifier (initial value) 1 stored in mc0 and md0 (receive-only mailbox) regardless of bit match between mc0 message identifier and receive message identifier (x = 15 to 0) lafmh bits 12 to 10?reserved: these bits always read 0. the write value should always be 0. lafmh bits 9 and 8, lafml bits 15 to 0?18-bit identifier filter (lafmh1, lafmh0, lafml7 to lafml0, lafml15 to lafml8): filter mask bits for the 18 bits of the receive message identifier (extended). bit x: lafmhx lafmlx description 0 stored in mc0 (receive-only mailbox) depending on bit match between mc0 message identifier and receive message identifier (initial value) 1 stored in mc0 (receive-only mailbox) regardless of bit match between mc0 message identifier and receive message identifier (x = 15 to 0)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 634 of 1484 rej09b0103-0600 16.2.18 message control (mc0 to mc15) the message control register sets (mc0 to mc15) consist of eight 8-bit readable/writable registers (mcx[1] to mcx[8]). the hcan has 16 sets of these registers (mc0 to mc15). the initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). mcx [1] bit:76543210 ????dlc3dlc2dlc1dlc0 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [2] bit:76543210 ???????? initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [3] bit:76543210 ???????? initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [4] bit:76543210 ???????? initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w * :undefined
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 635 of 1484 rej09b0103-0600 mcx [5] bit:76543210 std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [6] bit:76543210 std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [7] bit:76543210 exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mcx [8] bit:76543210 exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w * :undefined (x = 15 to 0) mcx[1] bits 7 to 4?reserved: the initial value of these bits is undefined; they must be initialized (by writing 0 or 1).
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 636 of 1484 rej09b0103-0600 mcx[1] bits 3 to 0?data length code (dlc): these bits indicate the required length of data frames and remote frames. bit 3: dlc3 bit 2: dlc2 bit 1: dlc1 bit 0: dlc0 description 0000data l ength = 0 bytes 1 data length = 1 byte 1 0 data length = 2 bytes 1 data length = 3 bytes 100data l ength = 4 bytes 1 data length = 5 bytes 1 0 data length = 6 bytes 1 data length = 7 bytes 1 0/1 0/1 0/1 data length = 8 bytes mcx[2] bits 7 to 0?reserved: the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). mcx[3] bits 7 to 0?reserved: the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). mcx[4] bits 7 to 0?reserved: the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). mcx[6] bits 7 to 0?standard identifier (std_id10 to std_id3) mcx[5] bits 7 to 5?standard identifier (std_id2 to std_id0) these bits set the identifier (standard identifier) of data frames and remote frames. standard identifier sof id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr std_idxx ide srr figure 16-2 standard identifier
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 637 of 1484 rej09b0103-0600 mcx[5] bit 4?remote transmission request (rtr): used to distinguish between data frames and remote frames. bit 4: rtr description 0 data frame 1 remote frame mcx[5] bit 3?identifier extension (ide): used to distinguish between the standard format and extended format of data frames and remote frames. bit 3: ide description 0 standard format 1 extended format mcx[5] bit 2?reserved: the initial value of this bit is undefined; it must be initialized (by writing 0 or 1). mcx[5] bits 1 and 0?extended identifier (exd_id17, exd_id16) mcx[8] bits 7 to 0?extended identifier (exd_id15 to exd_id8) mcx[7] bits 7 to 0?extended identifier (exd_id7 to exd_id0) these bits set the identifier (extended identifier) of data frames and remote frames. extended identifier ide id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 id6 id5 exd_idxx id4 id3 id2 id1 id0 rtr r1 exd_idxx figure 16-3 extended identifier
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 638 of 1484 rej09b0103-0600 16.2.19 message data (md0 to md15) the message data register sets (md0 to md15) consist of eight 8-bit readable/writable registers (mdx[1] to mdx[8]). the hcan has 16 sets of these registers (md0 to md15). the initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). mdx [1] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [2] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [3] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [4] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 639 of 1484 rej09b0103-0600 mdx [5] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [6] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [7] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w mdx [8] bit:76543210 initial value: ******** r/w: r/w r/w r/w r/w r/w r/w r/w r/w * :undefined (x = 0 to 15)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 640 of 1484 rej09b0103-0600 16.2.20 module stop control register c (mstpcrc) bit:76543210 mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 * mstpc1 mstpc0 initial value: 11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * the mstpc2 is not available and is reserved in the h8s/2635 and h8s/2634. mstpcrc is an 8-bit readable/writable register that performs module stop mode control. when the mstpc3 and mstpc2 bits are set to 1, hcan0 and 1 operation is stopped at the end of the bus cycle, and module stop mode is entered. register read/write accesses are not possible in module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcrc is initialized to h'ff by a reset, and in hardware standby mode. it is not initialized in software standby mode. bit 3?module stop (mstpc3): specifies the hcan module stop mode. bit 3: mstpc3 description 0 hcan0 module stop mode is cleared 1 hcan0 module stop mode is set (initial value) bit 2?module stop (mstpc2) * : specifies the hcan module stop mode. note: * the mstpc2 is not available and is reserved in the h8s/2635 and h8s/2634. bit 2: mstpc2 description 0 hcan1 module stop mode is cleared 1 hcan1 module stop mode is set (initial value)
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 641 of 1484 rej09b0103-0600 16.3 operation this lsi device is equipped with 2-channel hcan modules, which are controlled independently. both modules have identical specifications, and they are controlled in the same manner. 16.3.1 hardware and software resets the hcan can be reset by a hardware reset or software reset. hardware reset (hcan module stop, reset * , hardware * /software standby): initialization is performed by automatic setting of the mcr reset request bit (mcr0) in mcr and the reset state bit (gsr3) in gsr within the hcan (hardware reset). at the same time, all internal registers are initialized. however mailbox contents are retained. a flowchart of this reset is shown in figure 16-4. note: * in a reset and in hardware standby mode, the module stop bit is initialized to 1 and the hcan enters the module stop state. software reset (write to mcr0): in normal operation initialization is performed by setting the mcr reset request bit (mcr0) in mcr (software reset). with this kind of reset, if the can controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. during initialization, the reset state bit (gsr3) in gsr is set. in this kind of initialization, the error counters (tec and rec) are initialized but other registers and ram (mailboxes) are not. a flowchart of this reset is shown in figure 16-5.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 642 of 1484 rej09b0103-0600 irr0 = 1 (automatic) * 1 gsr3 = 1 (automatic) initialization of hcan module clear irr0 bcr setting mbcr setting mailbox (ram) initialization message transmission method initialization hardware reset mcr0 = 1 (automatic) gsr3 = 0? gsr3 = 0 & 11 recessive bits received? can bus communication enabled imr setting (interrupt mask setting) mbimr setting (interrupt mask setting) mc[x] setting (receive identifier setting) lafm setting (receive identifier mask setting) mcr0 = 0 bit configuration mode period in which bcr, mbcr, etc., are initialized : settings by user : processing by hardware yes yes no no notes: 1. when irr0 is set to 1 (automatically) due to a hardware reset * 2 , a "hardware reset initiated reset processing" interrupt is generated. 2. in a reset and in hardware standby mode, the module stop bit is initialized to 1 and the hcan enters the module stop state. figure 16-4 hardware reset flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 643 of 1484 rej09b0103-0600 initialization of rec and tec only mcr0 = 1 gsr3 = 1 (automatic) bus idle? can bus communication enabled : settings by user : processing by hardware yes yes yes no no mcr0 = 0 gsr3 = 0? no gsr3 = 1? no imr setting mbimr setting mc[x] setting lafm setting ok? no yes yes yes correction correction no bcr setting mbcr setting mailbox (ram) initialization message transmission method initialization ok? gsr3 = 0 & 11 recessive bits received? figure 16-5 software reset flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 644 of 1484 rej09b0103-0600 16.3.2 initialization after hardware reset after a hardware reset, the following initialization processing should be carried out: ? clearing of irr0 bit in interrupt register (irr) ? bit rate setting ? mailbox transmit/receive settings ? mailbox (ram) initialization ? message transmission method setting these initial settings must be made while the hcan is in bit configuration mode. configuration mode is a state in which the reset request bit (mcr0) in the master control register (mcr) is 1 and the reset status bit in the general status register (gsr) is also 1 (gsr3 = 1). configuration mode is exited by clearing the reset request bit in mcr to 0; when mcr0 is cleared to 0, the hcan automatically clears the reset state bit (gsr3) in the general status register (gsr). the power-up sequence then begins, and communication with the can bus is possible as soon as the sequence ends. the power-up sequence consists of the detection of 11 consecutive recessive bits. irr0 clearing: the reset interrupt flag (irr0) is always set after a reset or recovery from software standby mode. as an hcan interrupt is initiated immediately when interrupts are enabled, irr0 should be cleared. bit rate and bit timing settings: as bit rate settings, a baud rate setting and bit timing setting must be made each time a can node begins communication. the baud rate and bit t iming settings are made in the bit configuration register (bcr). a. note bcr can be written to at all times, but should only be modified in configuration mode. settings should be made so that all can controllers connected to the can bus have the same baud rate and bit width. limits for the settable variables (tseg1, tseg2, brp, sample point, and sjw) are shown in table 16-3.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 645 of 1484 rej09b0103-0600 table 16-3 bcr register value setting ranges name abbreviation bits initial value min. value max. value time segment 1 tseg140315 time segment 2 tseg23017 baud rate prescaler brp 60063 sample point sam 1001 synchronization jump widthsjw 2013 b. value setting ranges ? the minimum value of sjw is stipulated in the can specifications. 3 sjw 0 ? the minimum value of tseg1 is stipulated in the can specifications. tseg1 > tseg2 ? the minimum value of tseg2 is stipulated in the can specifications. tseg2 sjw the following formula is used to calculate the baud rate. f clk 2 (brp + 1) (3 + tseg1 + tseg2) bit rate = [b/s] note: f clk = (system clock) the bcr value are used for brp, tseg1, and tseg2. example: with a 1 mb/s baud rate and a 20 mhz input clock: 20 mhz 2 (0 + 1) (3 + 4 + 3) 1 mb/s =
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 646 of 1484 rej09b0103-0600 item set values actual values f clk 20 mhz ? brp 0 (b'000000) system clock 2 tseg1 4 (b'0100) 5tq tseg2 3 (b'011) 4tq sync_seg prseg phseg1 phseg2 1-bit time 1-bit time (8 to 25 time quanta) quantum 1 time segment 1 (tseg1) * 2 to16 time segment 2 (tseg2) * 2 to 8 legend: sync_seg: segment for establishing synchronization of nodes on the can bus (normal bit edge transitions occur in this segment). prseg: segment for compensating for physical delay between networks. phseg1: buffer segment for correcting phase drift (positive). (this segment is extended when synchronization (resynchronization) is established). phseg2: buffer segment for correcting phase drift (negative). (this segment is shortened when synchronization (resynchronization) is established). note: * the time quanta values of tseg1 and tseg2 become the value of tseg + 1. figure 16-6 detailed description of one bit hcan bit rate calculation: f clk 2 (brp + 1) (3 + tseg1 + tseg2) bit rate = f clk : peripheral clock ( ) note: the bcr values are used for brp, tseg1, and tseg2. bcr setting constraints tseg1 > tseg2 sjw (sjw = 0 to 3) these constraints allow the setting range shown in table 16-4 for tseg1 and tseg2 in bcr.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 647 of 1484 rej09b0103-0600 table 16-4 setting range for tseg1 and tseg2 in bcr tseg2 (bcr [14:12]) 001 010 011 100 101 110 111 tseg1 0011 no yes no no no no no (bcr [11 : 8]) 0100 yes * yes yes no no no no 0101 yes * yes yes yes no no no 0110 yes * yes yes yes yes no no 0111 yes * yes yes yes yes yes no 1000 yes * yes yes yes yes yes yes 1001 yes * yes yes yes yes yes yes 1010 yes * yes yes yes yes yes yes 1011 yes * yes yes yes yes yes yes 1100 yes * yes yes yes yes yes yes 1101 yes * yes yes yes yes yes yes 1110 yes * yes yes yes yes yes yes 1111 yes * yes yes yes yes yes yes note: * setting is enabled except when brp [13:8] = b'000000. mailbox transmit/receive settings: hcan0, 1 each have 16 mailboxes. mailbox 0 is receive- only, while mailboxes 1 to 15 can be set for transmission or reception. mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. the initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). mailbox trans mit/r eceive settings are not initialized by a software reset. ? setting for transmission transmit mailbox setting (mailboxes 1 to 15) clearing a corresponding mailbox in the mailbox configuration register (mbcr) to 0 designates the specified mailbox for transmission use. after a reset, mailboxes are initialized for transmission use, so this setting is not necessary. ? setting for reception transmit/receive mailbox setting (mailboxes 1 to 15) setting a bit to 1 in the mailbox configuration register (mbcr) designates the corresponding mailbox for reception use. when setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15).
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 648 of 1484 rej09b0103-0600 ? receive-only mailbox (mailbox 0) no setting is necessary, as this mailbox is always used for reception. mailbox (message control/data (mcx[x], mdx[x]) initial settings: after power is supplied, all registers and ram (message control/data, control registers, status registers, etc.) are initialized. message control/data (mcx[x], mdx[x]) only are in ram, and so their values are undefined. initial values must therefore be set in all the mailboxes (by writing 0s or 1s). setting the message transmission method: either of the following message transmission methods can be selected with the message transmission method bit (mcr2) in the master control register (mcr): a. transmission order determined by message identifier priority b. transmission order determined by mailbox number priority when a is selected, if a number of messages are designated as waiting for transmission (txpr = 1), the message with the highest priority set in the message identifier (mcx[5] to mcx[8]) is stored in the transmit buffer. can bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. when the txpr bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. when b is selected, if a number of messages are designated as waiting for transmission (txpr = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). can bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 649 of 1484 rej09b0103-0600 16.3.3 transmit mode message transmission is performed using mailboxes 1 to 15. the transmission procedure is described below, and a transmission flowchart is shown in figure 16-6. initialization (after hardware reset only) a. clearing of irr0 bit in interrupt register (irr) b. bit rate settings c. mailbox transmit/receive settings d. mailbox (ram) initialization e. message transmission method setting interrupt and transmit data settings a. cpu interrupt source setting b. arbitration field setting c. control field setting d. data field setting message transmission and interrupts a. message transmission wait b. message transmission completion and interrupt c. message transmission cancellation d. message retransmission initialization (after hardware reset only): these settings should be made while the hcan is in bit configuration mode. ? irr0 clearing the reset interrupt flag (irr0) is always set after a reset or recovery from software standby mode. as an hcan interrupt is initiated immediately when interrupts are enabled, irr0 should be cleared. ? bit rate settings set values relating to the can bus communication speed and resynchronization. refer to bit rate and bit timing settings in 16.3.2, initialization after hardware reset, for details.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 650 of 1484 rej09b0103-0600 ? mailbox transmit/receive settings mailbox transmit/receive settings should be made in advance. a total of 30 mailbox can be set for transmission or reception (mailboxes 1 to 15 in hcan0 and hcan1). to set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (mbcr). refer to mailbox trans mit/receive settings in 16.3.2, initialization after hardware reset, for details. ? mailbox (ram) initialization as message control/data registers (mcx[x], mdx[x]) are configured in ram, their initial values after powering on are undefined, and so bit initialization is necessary. write 0s or 1s to the mailboxes. see mailbox (message control/data (mcx[x], mdx[x]) initial setting in 16.3.2, initialization after a hardware reset, for details. ? message transmission method setting set the transmission method for mailboxes designated for transmission. the following two transmission methods can be used. refer to message transmission method setting in 16.3.2, initialization after hardware reset, for details. a. transmission order determined by message identifier priority b. transmission order determined by mailbox number priority
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 651 of 1484 rej09b0103-0600 irr0 clearing bcr setting mbcr setting mailbox (ram) initialization message transmission method setting interrupt settings transmit data setting arbitration field setting control field setting data field setting message transmission wait txpr setting bus idle? no message transmission gsr2 = 0 (during transmission only) transmission completed? no txack = 1 irr8 = 1 imr8 = 1? yes interrupt to cpu clear txack clear irr8 end of transmission : settings by user : processing by hardware yes yes no initialization (after hardware reset only) figure 16-7 transmission flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 652 of 1484 rej09b0103-0600 interrupt and transmit data settings: when mailbox initialization is finished, cpu interrupt source settings and data settings must be made. interrupt source settings are made in the mailbox interrupt register (mbimr) and interrupt mask register (imr), while transmit data settings are made by writing the necessary data from the arbitration field, control field, and data field, described below, in the corresponding message control (mcx[1] to mcx[8]) and message data (mdx[1] to mdx[8]). ? cpu interrupt source setting transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (mbimr). interrupt register (irr) interrupts can be masked in the interrupt mask register (imr). ? arbitration field setting in the arbitration field, the 11-bit identifier (std_id0 to std_id10) and rtr bit (standard format) or 29-bit identifier (std_id0 to std_id10, ext_id0 to ext_id17) and ide, rtr bit (extended format) are set. the registers to be set are mcx[5] to mcx[8]. ? control field setting in the control field, the byte length of the data to be transmitted is set in dlc0 to dlc3. the register to be set is mcx[1]. ? data field setting in the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. the registers to be set are mdx[1] to mdx[8]. the number of bytes in the data actually transmitted depends on the data length code (dlc) in the control field. if a value exceeding the value set in dlc is set in the data field, only the number of bytes set in dlc will actually be transmitted. message transmission and interrupts: ? message transmission wait if message transmission is to be performed after completion of the message control (mcx[1] to mcx[8]) and message data (mdx[1] to mdx[8]).settings, transmission is started by setting the corresponding mailbox transmit wait bit (txpr1 to txpr15) to 1 in the transmit wait register (txpr). the following two transmission methods can be used: a. transmission order determined by message identifier priority b. transmission order determined by mailbox number priority
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 653 of 1484 rej09b0103-0600 when a is selected, if a number of messages are designated as waiting for transmission (txpr = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). can bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. when b is selected, if a number of messages are designated as waiting for transmission (txpr = 1), the message with the highest priority set in the message identifier (mcx[5] to mcx[8]) is stored in the transmit buffer. can bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. when the txpr bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, can bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. ? message transmission completion and interrupt when a message is transmitted error-free using the above procedure, the corresponding acknowledge bit (txack1 to txack15) in the transmit acknowledge register (txack) and transmit wait bit (txpr1 to txpr15) in the transmit wait register (txpr) are automatically initialized. also, if the corresponding bit (mbimr1 to mbimr15) in the mailbox interrupt mask register (mbimr) and the mailbox empty interrupt bit (irr8) in the interrupt mask register (imr) are set to the interrupt enable state at the same time, an interrupt can be sent to the cpu. ? message transmission cancellation transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. a transmit wait message is canceled by setting the bit for the corresponding mailbox (txcr1 to txcr15) to 1 in the transmit cancel register (txcr). when cancellation is executed, the transmit wait register (txpr) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (aback). an interrupt can be requested. also, if the mailbox empty interrupt (irr8) is enabled for the bits (mbimr1 to mbimr15) corresponding to the mailbox interrupt mask register (mbimr) and interrupt mask register (imr), interrupts may be sent to the cpu. however, a transmit wait message cannot be canceled at the following times: a. during internal arbitration or can bus arbitration b. during data frame or remote frame transmission also, transmission cannot be canceled by clearing the transmit wait register (txpr). figure 16-5 shows a flowchart of transmit message cancellation.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 654 of 1484 rej09b0103-0600 ? message retransmission if transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. can bus arbitration failure (failure to acquire the bus) b. error during transmission (bit error, stuff error, crc error, frame error, ack error) message transmit wait txpr setting set txcr bit corresponding to message to be canceled cancellation possible? no message not sent clear txcr, txpr aback = 1 irr8 = 1 imr8 = 1? yes interrupt to cpu clear txack clear aback clear irr8 end of transmission/transmission cancellation completion of message transmission txack = 1 clear txcr, txpr irr8 = 1 yes no : settings by user : processing by hardware figure 16-8 transmit message cancellation flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 655 of 1484 rej09b0103-0600 16.3.4 receive mode message reception is performed using mailboxes 0 and 1 to 15. the reception procedure is described below, and a reception flowchart is shown in figure 16-9. initialization (after hardware reset only) a. clearing of irr0 bit in interrupt register (irr) b. bit rate settings c. mailbox transmit/receive settings d. mailbox (ram) initialization interrupt and receive message settings a. cpu interrupt source setting b. arbitration field setting c. local acceptance filter mask (lafm) settings message reception and interrupts a. message reception crc check b. data frame reception c. remote frame reception d. unread message reception initialization (after hardware reset only): these settings should be made while the hcan is in bit configuration mode. ? irr0 clearing the reset interrupt flag (irr0) is always set after a reset or recovery from software standby mode. as an hcan interrupt is initiated immediately when interrupts are enabled, irr0 should be cleared. ? bit rate settings set values relating to the can bus communication speed and resynchronization. refer to bit rate and bit timing settings in 16.3.2, initialization after hardware reset, for details.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 656 of 1484 rej09b0103-0600 ? mailbox transmit/receive settings each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for reception. thus a total of 32 mailboxes can be used for reception. to set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (mbcr). the initial setting for mailboxes is 0, designating transmission use. refer to mailbox transmit/receive settings in 16.3.2, initialization after hardware reset, for details. ? mailbox (ram) initialization as message control/data registers (mcx[x], mdx[x]) are configured in ram, their initial values after powering on are undefined, and so bit initialization is necessary. write 0s or 1s to the mailboxes. see mailbox (message control/data (mcx[x], mdx[x]) initial setting in 16.3.2, initialization after a hardware reset, for details.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 657 of 1484 rej09b0103-0600 initialization irr0 clearing bcr setting mbcr setting mailbox (ram) initialization interrupt settings arbitration field setting local acceptance filter settings receive data setting message reception (match of identifier in mailbox?) no same rxpr = 1? yes data frame? no rxpr irr1 = 1 yes imr1 = 1? interrupt to cpu message control read message data read irr1 = 0 end of reception yes no yes no unread message rxpr, rfpr = 1 irr2 = 1, irr1 = 1 yes imr2 = 1? interrupt to cpu message control read message data read irr2 = 0, irr1 = 0 transmission of data frame corresponding to remote frame clear all rxprn bits of mailbox for which receive interrupt requests are enabled by mbimr clear all rxprn bits of mailbox for which receive interrupt requests are enabled by mbimr no : settings by user : processing by hardware figure 16-9 reception flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 658 of 1484 rej09b0103-0600 interrupt and receive message settings: when mailbox initialization is finished, cpu interrupt source settings and receive message specifications must be made. interrupt source settings are made in the mailbox interrupt register (mbimr) and interrupt mask register (imr). to receive a message, the identifier must be set in advance in the message control (mcx[1] to mcx[8]) for the receiving mailbox. when a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. mailbox 0 (mb0) has a local acceptance filter mask (lafm) that allows don?t care settings to be made. ? cpu interrupt source settings when transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (mbimr). when receiving, data frame and remote frame receive wait interrupts can be masked. interrupt register (irr) interrupts can be masked in the interrupt mask register (imr). ? arbitration field setting in the arbitration field, the identifier (std_id0 to std_id10, ext_id0 to ext_id17) of the message to be received is set. if all the bits in the set identifier do not match, the message is not stored in a mailbox. example: mailbox 1 010_1010_1010 (standard identifier) only one kind of message identifier can be received by mb1 identifier 1: 010_1010_1010 ? local acceptance filter mask (lafm) setting the local acceptance filter mask is provided for mailbox 0 (mb0) only, enabling a don?t care specification to be made for all bits in the received identifier. this allows various kinds of messages to be received. example: mailbox 0 010_1010_1010 (standard identifier) lafm 000_0000_0011 (0: care, 1: don?t care) a total of four kinds of message identifiers can be received by mb0 identifier 1: 010_1010_1000 identifier 2: 010_1010_1001 identifier 3: 010_1010_1010 identifier 4: 010_1010_1011
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 659 of 1484 rej09b0103-0600 message reception and interrupts: ? message reception crc check when a message is received, a crc check is performed automatically (by hardware). if the result of the crc check is normal, ack is transmitted in the ack field irrespective of whether or not the message can be received. ? data frame reception if the received message is confirmed to be error-free by the crc check, etc., the identifier in the mailbox (and also lafm in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. the message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. if a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (rxpr0 to rxpr15) is set in the receive complete register (rxpr). however, when a mailbox 0 lafm comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. it is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). if the corresponding bit (mbimr0 to mbimr15) in the mailbox interrupt mask register (mbimr) and the receive message interrupt mask (imr1) in the interrupt mask register (imr) are set to the interrupt enable value at this time, an interrupt can be sent to the cpu. ? remote frame reception two kinds of messages?data frames and remote frames?can be stored in mailboxes. a remote frame differs from a data frame in that the remote reception request bit (rtr) in the message control register (mc[x]5) and the data field are 0 bytes. the data length to be returned in a data frame must be stored in the data length code (dlc) in the control field. when a remote frame (rtr = recessive) is received, the corresponding bit is set in the remote request wait register (rfpr). if the corresponding bit (mbimr0 to mbimr15) in the mailbox interrupt mask register (mbimr) and the remote frame request interrupt mask (irr2) in the interrupt mask register (imr) are set to the interrupt enable value at this time, an interrupt can be sent to the cpu. ? unread message reception when a received message matches the identifier in a mailbox, the message is stored in the mailbox. if a message overwrite occurs before the cpu reads the message, the corresponding bit (umsr0 to umsr15) is set in the unread message register (umsr). in overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (rxpr) has been cleared, the unread message register (umsr) is set. if the
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 660 of 1484 rej09b0103-0600 unread interrupt flag (irr9) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu. figure 16-10 shows a flowchart of unread message overwriting. umsr = 1 irr9 = 1 unread message overwrite imr9 = 1? end yes interrupt to cpu clear irr9 message control/message data read no : settings by user : processing by hardware figure 16-10 unread message overwrite flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 661 of 1484 rej09b0103-0600 16.3.5 hcan sleep mode the hcan is provided with an hcan sleep mode that places the hcan module in the sleep state to reduce current dissipation. figure 16-11 shows a flowchart of the hcan sleep mode. mcr5 = 1 bus operation? irr12 = 1 initialize tec and rec imr12 = 1? sleep mode clearing method mcr7 = 0? mcr5 = 0 can bus communication possible cpu interrupt mb should not be accessed mcr5 = 0 clear sleep mode? yes yes no yes no yes (manual) no (automatic) no yes gsr3 = 1? no yes yes yes no : settings by user : processing by hardware 11 recessive bits? no gsr3 = 1? no bus idle? figure 16-11 hcan sleep mode flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 662 of 1484 rej09b0103-0600 hcan sleep mode is entered by setting the hcan sleep mode bit (mcr5) to 1 in the master control register (mcr). if the can bus is operating, the transition to hcan sleep mode is delayed until the bus becomes idle. either of the following methods of clearing hcan sleep mode can be selected by making a setting in the mcr7 bit. 1. clearing by software 2. clearing by can bus operation eleven recessive bits must be received after hcan sleep mode is cleared before can bus communication is enabled again. clearing by software: hcan sleep mode is cleared by writing a 0 to mcr5 from the cpu. clearing by can bus operation: clearing by can bus operation occurs automatically when the can bus performs an operation and this change is detected. in this case, the first message is not received in the mailbox, and normal reception starts from the next message. when a change is detected on the can bus in hcan sleep mode, the bus operation interrupt flag (irr12) is set in the interrupt register (irr). if the bus interrupt mask (imr12) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 663 of 1484 rej09b0103-0600 16.3.6 hcan halt mode the hcan halt mode is provided to enable mailbox settings to be changed without performing an hcan hardware or software reset. figure 16-12 shows a flowchart of the hcan halt mode. mcr1 = 1 bus idle? can bus communication possible no mbcr setting mcr1 = 0 yes : settings by user : processing by hardware figure 16-12 hcan halt mode flowchart hcan halt mode is entered by setting the halt request bit (mcr1) to 1 in the master control register (mcr). however, if the can bus is operating at the time of a transition, the transition to hcan alt mode is delayed until the bus becomes idle. hcan halt mode is cleared by clearing mcr1 to 0. 16.3.7 interrupt interface there are 12 hcan interrupt sources, to which five independent interrupt vectors are assigned. table 16-5 lists the hcan interrupt sources. with the exception of the reset processing vector (irr0), these sources can be masked. masking is implemented using the mailbox interrupt mask register (mbimr) and interrupt mask register (imr).
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 664 of 1484 rej09b0103-0600 table 16-5 hcan interrupt sources channel ipr bits vector vector number irr bit description hcan0 iprm (2 to 0) ers0 108 irr5 error passive interrupt (tec 128 or rec 128) irr6 bus off interrupt (tec 256) ovr0 108 irr0 hardware reset processing interrupt irr2 remote frame reception interrupt irr3 error warning interrupt (tec 96) irr4 error warning interrupt (rec 96) irr7 overload frame transmission interrupt irr9 unread message overwrite interrupt irr12 hcan sleep mode can bus operation interrupt rm0 109 irr1 mailbox 0 message reception interrupt rm1 108 irr1 mailbox 1 to 15 message reception interrupt sle0 108 irr8 message transmission/cancellation interrupt hcan1 iprm (6 to 4) ers0 106 irr5 error passive interrupt (tec 128 or rec 128) irr6 bus off interrupt (tec 256) ovr0 106 irr0 hardware reset processing interrupt irr2 remote frame reception interrupt irr3 error warning interrupt (tec 96) irr4 error warning interrupt (rec 96) irr7 overload frame transmission interrupt irr9 unread message overwrite interrupt irr12 hcan sleep mode can bus operation interrupt rm0 107 irr1 mailbox 0 message reception interrupt rm1 106 irr1 mailbox 1 to 15 message reception interrupt sle0 106 irr8 message transmission/cancellation interrupt
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 665 of 1484 rej09b0103-0600 16.3.8 dtc interface * note: * the dtc is not implemented in the h8s/2635 and h8s/2634. the dtc can be activated by reception of a message in the hcan?s mailbox 0. when dtc transfer ends after dtc activation has been set, the rxpr0 and rfpr0 flags are acknowledge signal automatically. an interrupt request due to a receive interrupt from the hcan cannot be sent to the cpu in this case. figure 16-13 shows a dtc transfer flowchart. dtc enable register setting dtc register information setting end of dtc transfer? end no dtc initialization message reception in hcan?s mailbox 0 dtc activation transfer counter = 0 or disel = 1? no interrupt to cpu yes yes : settings by user : processing by hardware rxpr and rfpr clearing figure 16-13 dtc transfer flowchart
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 666 of 1484 rej09b0103-0600 16.4 can bus interface a bus transceiver ic is necessary to connect the chip to a can bus. a ha13721 transceiver ic, or compatible device, is recommended. figure 16-14 shows a sample connection diagram. mode rxd txd nc vcc canh canl gnd hrxd port htxd nc note: nc: no connection chip can bus 120 ? 120 ? vcc ha13721 figure 16-14 high-speed interface using ha13721
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 667 of 1484 rej09b0103-0600 16.5 usage notes (1) reset the hcan is reset by a reset, and in hardware standby mode and software standby mode. all the registers are initialized in a reset, but mailboxes (message control (mcx[x])/message data (mdx[x]) are not. however, after powering on, mailboxes (message control (mcx[x])/message data (mdx[x]) are initialized, and their values are undefined. therefore, mailbox initialization must always be carried out after a reset or a transition to hardware standby mode or software standby mode. also, the reset interrupt flag (irr0) is always set after reset input or recovery from software standby mode. as this bit cannot be masked in the interrupt mask register (imr), if hcan interrupts are set as enabled by the interrupt controller without this flag having been cleared, an hcan interrupt will be initiated immediately. irr0 must therefore be cleared during initialization. (2) hcan sleep mode the bus operation interrupt flag (irr12) in the interrupt register (irr) is set by bus operation in hcan sleep mode. therefore, this flag is not used by the hcan to indicate sleep mode release. also note that the reset status bit (gsr3) in the general status register (gsr) is set in sleep mode. (3) interrupts when the mailbox interrupt mask register (mbimr) is set, the interrupt register (irr8,2,1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. (4) error counters in the case of error active and error passive, rec and tec normally count up and down. in the bus off state, 11-bit recessive sequences are counted (rec + 1) using rec. if rec reaches 96 during the count, irr4 and gsr1 are set. (5) register access byte or word access can be used on all hcan registers. longword access cannot be used. (6) hcan medium-speed mode hcan registers cannot be read or written to in medium-speed mode.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 668 of 1484 rej09b0103-0600 (7) register retention during standby all hcan registers are initialized in hardware standby mode and software standby mode. (8) usage of bit manipulation instructions the hcan status flags are cleared by writing 1, so do not use a bit manipulation instruction to clear a flag. when clearing a flag, use the mov instruction to write 1 to only the bit that is to be cleared. (9) operation of txcr in hcan 1. when the transmit wait cancel register (txcr) is used to cancel messages awaiting transmission from a mailbox waiting to transmit, the bits corresponding to txcr and the transmit wait register (txpr) are sometimes not cleared in spite of the fact that transmission was cancelled. this situation can arise when all of the following conditions are met. the hrxd pin is stuck at 1 because of a can bus error, etc. one or more mailboxes are waiting to transmit (or trans mitting). transmission of a message in a mailbox that is trans mitting is cancelled using txcr. when this situation occurs the message is not cancelled. however, since txpr and txcr continue to incorrectly display the status of the message as in the process of being cancelled, it is not possible to restart transmission even when the hrxd pin is no longer stuck at 1 and the can bus is restored to normal status. if there are two or more messages to be transmitted, those messages that are not in the process of being sent are cancelled and the messages in the process of being sent remain in that status. to avoid the situation described above, either of the following two countermeasures should be implemented. do not use txcr to cancel transmission of messages. this will ensure that txpr is cleared and hcan operates normally after transmission completes normally following recovery by the can bus. if it is necessary to cancel transmission of a message, write continuously to bit 1 corresponding to txcr until the bits corresponding to txcr become 0. this w ill ensure that txpr and txcr are cleared and that hcan is restored to normal operation. 2. if txpr is set, resulting in transmission wait status, when a transition to bus off status takes place, cancellation cannot be performed even if txcr is set during bus off status because the internal state machine does not operate. after recovery from bus off status, the message is cancelled after one message is either sent or generates a transmission error. the following countermeasure should be taken with regard to clearing messages following recovery from bus off status.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 669 of 1484 rej09b0103-0600 clear the messages awaiting transmission by resetting the hcan module during bus off status. to reset the hcan module, set and then clear the module stop bits (mstpc3 and mstpc2 in mstpcrc). note that this will reset all internal values in the hcan m odule, so it will be n ecessary to perform the initial settings once again. (10) hcan transmit procedure when transmission is set while the bus is in the idle state, if the next transmission is set or the set transmission is canceled under the following conditions within 50 s, the transmit message id of being set may be damaged. ? when the second transmission has the message whose priority is higher than the first one. ? when the message of the highest priority is canceled in the first transmission. make whichever setting shown below to avoid the message ids from being damaged. ? set transmission in one txpr. after transmission of all transmit messages is completed, set transmission again (mass transmission setting). the interval between transmission settings should be 50 s or longer. ? make the transmission setting according to the priority of transmit messages. ? set the interval to be 50 s or longer between txpr and another txpr or between txpr and txcr. table 16-6 interval limitation between txpr and txpr or between txpr and txcr baud rate (bps) set interval ( s) 1 m 50 500 k 50 250 k 50 (11) canceling hcan reset and hcan sleep before canceling the software reset or sleep mode for hcan (mcr0 = 0 or mcr5 = 0), confirm that the reset status bit (gsr3) is set to 1. (12) accessing mailbox in hcan sleep mode the mailboxes should not be accessed in hcan sleep mode. if mailboxes are accessed in hcan sleep mode, the cpu may stop. when registers are accessed in hcan sleep mode, the cpu does not stop. when mailboxes are accessed in modes other than sleep mode, the cpu does not stop.
section 16 controller area network (hcan) rev. 6.00 feb 22, 2005 page 670 of 1484 rej09b0103-0600
section 17 a/d converter rev. 6.00 feb 22, 2005 page 671 of 1484 rej09b0103-0600 section 17 a/d converter note: the h8s/2635 group is not equipped with a dtc. 17.1 overview the chip incorporates a successive approximation type 10-bit a/d converter that allows up to twelve analog input channels to be selected. 17.1.1 features a/d converter features are listed below. ? 10-bit resolution ? twelve input channels ? settable analog conversion voltage range ? conversion of analog voltages with the reference voltage pin (vref) as the analog reference voltage ? high-speed conversion ? minimum conversion time: 13.3 s per channel (at 20 mhz operation) ? choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three kinds of conversion start ? choice of software or timer conversion start trigger (tpu), or adtrg pin ? a/d conversion end interrupt generation ? a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion ? module stop mode can be set ? as the initial setting, a/d converter operation is halted. register access is enabled by exiting module stop mode.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 672 of 1484 rej09b0103-0600 17.1.2 block diagram figure 17-1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + ? sample-and- hold circuit /2 /4 /8 adi interrupt /16 bus interface addra addrb addrc addrd adcsr adcr a v cc v ref a v ss a n0 a n1 a n2 a n3 a n4 a n5 a n6 a n7 a n8 a n9 a n10 a n11 adtrg conversion start trigger from tpu successive approximations register multiplexer legend: adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d figure 17-1 block diagram of a/d converter
section 17 a/d converter rev. 6.00 feb 22, 2005 page 673 of 1484 rej09b0103-0600 17.1.3 pin configuration table 17-1 summarizes the input pins used by the a/d converter. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. the vref pin is the a/d conversion reference voltage pin. the 12 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (an0 to an7) comprising channel set 0, analog input pins 8 to 11 (an8 to an11) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (an0 to an3, an8 to an11) comprising group 0, and analog input pins 4 to 7 (an4 to an7) comprising group 1. table 17-1 a/d converter pins pin name symbol i/o function analog power supply pin avcc input analog block power supply analog ground pin avss i nput analog block ground and reference voltage reference voltage pin vref input a/d conversion reference voltage analog input pin 0 an0 input channel set 0 (ch3 = 0) group 0 analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input channel set 0 (ch3 = 0) group 1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog input pin 8 an8 input channel set 1 (ch3 = 1) group 0 analog inputs analog input pin 9 an9 input analog input pin 10 an10 input analog input pin 11 an11 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 17 a/d converter rev. 6.00 feb 22, 2005 page 674 of 1484 rej09b0103-0600 17.1.4 register configuration table 17-2 summarizes the registers of the a/d converter. table 17-2 a/d converter registers name abbreviation r/w initial value address * 1 a/d data register ah addrah r h'00 h 'ff90 a/d data register al addral r h'00 h 'ff91 a/d data register bh addrbh r h'00 h 'ff92 a/d data register bl addrbl r h'00 h 'ff93 a/d data register ch addrch r h'00 h 'ff94 a/d data register cl addrcl r h'00 h 'ff95 a/d data register dh addrdh r h'00 h 'ff96 a/d data register dl addrdl r h'00 h 'ff97 a/d control/status register adcsr r/(w) * 2 h'00 h'ff98 a/d control register adcr r/w h'33 h'ff99 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. bit 7 can only be written with 0 for flag clearing.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 675 of 1484 rej09b0103-0600 17.2 register descriptions 17.2.1 a/d data registers a to d (addra to addrd) 15 ad9 0 r bit initial value r/w : : : 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 17-3. addr can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 17.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode or module stop mode. table 17-3 analog input channels and corresponding addr registers analog input channel channel set 0 (ch3 = 0) channel set 1 (ch3 = 1) group 0 group 1 group 0 group 1 a/d data register an0 an4 an8 setting prohibited addra an1 an5 an9 setting prohibited addrb an2 an6 an10 setting prohibited addrc an3 an7 an11 setting prohibited addrd
section 17 a/d converter rev. 6.00 feb 22, 2005 page 676 of 1484 rej09b0103-0600 17.2.2 a/d control/status register (adcsr) 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value r/w : : : note: * only 0 can be written to bit 7, to clear this flag. adcsr is an 8-bit readable/writable register that controls a/d conversion operations. adcsr is initialized to h'00 by a reset, and in hardware standby mode or module stop mode. bit 7?a/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) ? when 0 is written to the adf flag after reading adf = 1 ? when the dtc is activated by an adi interrupt and addr is read 1 [setting conditions] ? single mode: when a/d conversion ends ? scan mode: when a/d conversion ends on all specified channels bit 6?a/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request disabled (initial value) 1 a/d conversion end interrupt (adi) request enabled
section 17 a/d converter rev. 6.00 feb 22, 2005 page 677 of 1484 rej09b0103-0600 bit 5?a/d start (adst): selects starting or stopping on a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ). bit 5 adst description 0 a/d conversion stopped (initial value) 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. bit 4?scan mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 17.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped (adst = 0). bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?channel select 3 (ch3): switches the analog input pins assigned to group 0 or group 1. setting ch3 to 1 enables an8 to an11 to be used instead of an0 to an7. bit 3 ch3 description 1 an8 to an11 are group 0 analog input pins 0 an0 to an3 are group 0 analog input pins, an4 to an7 are group 1 analog input pins (initial value)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 678 of 1484 rej09b0103-0600 bits 2 to 0?channel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channels. only set the input channel while conversion is stopped (adst = 0). channel selection description ch3 ch2 ch1 ch0 single mode (scan = 0) scan mode (scan = 1) 0000 an0 (initial value)an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 100 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 1000 an8 an8 1 an9 an8, an9 1 0 an10 an8 to an10 1 an11 an8 to an11 1 0 0 setting prohibited setting prohibited 1 setting prohibited setting prohibited 1 0 setting prohibited setting prohibited 1 setting prohibited setting prohibited
section 17 a/d converter rev. 6.00 feb 22, 2005 page 679 of 1484 rej09b0103-0600 17.2.3 a/d control register (adcr) 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 ? 4 ? 1 ? 3 cks1 0 r/w 0 ? 1 ? 2 cks0 0 r/w 1 ? 1 ? bit initial value r/w : : : adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations and sets the a/d conversion time. adcr is initialized to h'33 by a reset, and in standby mode or module stop mode. bits 7 and 6?timer trigger select 1 and 0 (trgs1, trgs0): select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped (adst = 0). bit 7 bit 6 trgs1 trgs0 description 0 0 a/d conversion start by software is enabled (initial value) 1 a/d conversion start by tpu conversion start trigger is enabled 1 0 setting prohibited 1 a/d conversion start by external trigger pin ( adtrg ) is enabled bits 5, 4, 1, and 0?reserved: these bits are reserved; they are always read as 1 and cannot be modified. bits 3 and 2?clock select 1 and 0 (cks1, cks0): these bits select the a/d conversion time. the conversion time should be changed only when adst = 0. set bits cks1 and cks0 to give a conversion time of at least 10 s. bit 3 bit 2 cks1 cks0 description 0 0 conversion time = 530 states (max.) (initial value) 1 conversion time = 266 states (max.) 1 0 conversion time = 134 states (max.) 1 conversion time = 68 states (max.)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 680 of 1484 rej09b0103-0600 17.2.4 module stop control register a (mstpcra) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w : : : mstpcr is an 8-bit readable/writable register that performs module stop mode control. when the mstpa1 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 23a.5, 23b.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a reset and in software standby mode. bit 1?module stop (mstpa1): specifies the a/d converter module stop mode. bit 1 mstpa1 description 0 a/d converter module stop mode cleared 1 a/d converter module stop mode set (initial value)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 681 of 1484 rej09b0103-0600 17.3 interface to bus master addra to addrd are 16-bit registers, and the data bus to the bus master is 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 17-2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 17-2 addr access operation (reading h'aa40)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 682 of 1484 rej09b0103-0600 17.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes: single mode and scan mode. 17.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1, according to the software or external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 17-3 shows a timing diagram for this example. [1] single mode is selected (scan = 0), input channel an1 is selected (ch3 = 0, ch2 = 0, ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). [2] when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. [3] since adf = 1 and adie = 1, an adi interrupt is requested. [4] the a/d interrupt handling routine starts. [5] the routine reads adcsr, then writes 0 to the adf flag. [6] the routine reads and processes the connection result (addrb). [7] execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps [2] to [7] are repeated.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 683 of 1484 rej09b0103-0600 adie adst adf state of channel 0 (an0) a/d conversion starts 2 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion set * figure 17-3 example of a/d converter operation (single mode, channel 1 selected)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 684 of 1484 rej09b0103-0600 17.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by a software, timer or external trigger input, a/d conversion starts on the first channel in the group (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again from the first channel (an0). the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an0 to an2) are selected in scan mode are described next. figure 17-4 shows a timing diagram for this example. [1] scan mode is selected (scan = 1), channel set 0 is selected (ch3 = 0), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) [2] when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. [3] conversion proceeds in the same way through the third channel (an2). [4] when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. [5] steps [2] to [4] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
section 17 a/d converter rev. 6.00 feb 22, 2005 page 685 of 1484 rej09b0103-0600 adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 17-4 example of a/d converter operation (scan mode, 3 channels an0 to an2 selected)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 686 of 1484 rej09b0103-0600 17.4.3 input sampling and a/d conversion time the a/d converter has an on-chip sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 17-5 shows the a/d conversion timing. table 17-4 indicates the a/d conversion time. as indicated in figure 17-5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 17-4. in scan mode, the values given in table 17-4 apply to the first conversion time. the values given in table 17-5 apply to the second and subsequent conversions. in both cases, set bits cks1 and cks0 in adcr to give a conversion time of at least 10 s. (1) (2) t d t spl t conv input sampling timing adf address write signal legend: (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 17-5 a/d conversion timing
section 17 a/d converter rev. 6.00 feb 22, 2005 page 687 of 1484 rej09b0103-0600 table 17-4 a/d conversion time (single mode) cks1 = 0 cks1 = 0 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min typ max min typ max min typ max min typ max a/d conversion start delay t d 18 ? 33 10 ? 17 6 ? 9 4 ? 5 input sampling time t spl ? 127 ? ? 63 ? ? 31 ? ? 15 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: values in the table are the number of states. table 17-5 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 0 512 (fixed) 1 256 (fixed) 1 0 128 (fixed) 1 64 (fixed) 17.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit has been set to 1 by software. figure 17-6 shows the timing.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 688 of 1484 rej09b0103-0600 adtrg internal trigger signal adst a/d conversion figure 17-6 external trigger input timing 17.5 interrupts the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. adi interrupt requests can be enabled or disabled by means of the adie bit in adcsr. the dtc can be activated by an adi interrupt. having the converted data read by the dtc in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. the a/d converter interrupt source is shown in table 17-6. table 17-6 a/d converter interrupt source interrupt source description dtc activation adi interrupt due to end of conversion possible
section 17 a/d converter rev. 6.00 feb 22, 2005 page 689 of 1484 rej09b0103-0600 17.6 usage notes the following points should be noted when using the a/d converter. setting range of analog power supply and other pins: (1) analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann vref. (2) relation between avcc, avss and vcc, vss as the relationship between avss and vss, set avss = vss. if the a/d converter is not used, set avcc = vcc, and do not leave the avcc and avss pins open or no account. (3) vref input range the analog reference voltage input at the vref pin set in the range vref avcc. if conditions (1), (2), and (3) above are not met, the reliab ility of the device may be adversely affected. notes on board design: in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity s hould be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an11), analog reference power supply (vref), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. notes on noise countermeasures: a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an11) and analog reference power supply (vref ) should be connected between avcc and avss as shown in figure 17-7. also, the bypass capacitors connected to avcc and vref and the filter capacitor connected to an0 to an11 must be connected to avss. if a filter capacitor is connected as shown in figure 17-7, the input currents at the analog input pins (an0 to an11) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the
section 17 a/d converter rev. 6.00 feb 22, 2005 page 690 of 1484 rej09b0103-0600 sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog i nput pin voltage. careful consideration is therefore required when deciding the circuit constants. avcc * 1 * 1 vref an0 to an11 avss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 m f 0.01 m f 10 m f figure 17-7 example of analog input protection circuit table 17-7 analog pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 5 k ?
section 17 a/d converter rev. 6.00 feb 22, 2005 page 691 of 1484 rej09b0103-0600 20 pf to a/d converter an0 to an11 10 k w note: values are reference values. figure 17-8 analog input pin equivalent circuit a/d conversion precision definitions: the chip?s a/d conversion precision definitions are given below. ? resolution the number of a/d converter digital output codes ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'00) to b'0000000001 (h'01) (see figure 17-10). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3e) to b'1111111111 (h'3f) (see figure 17-10). ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 17-9). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. ? absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 692 of 1484 rej09b0103-0600 111 110 101 100 011 010 001 000 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 1 1024 2 1024 1022 1024 1023 1024 figure 17-9 a/d conversion precision definitions (1)
section 17 a/d converter rev. 6.00 feb 22, 2005 page 693 of 1484 rej09b0103-0600 fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 17-10 a/d conversion precision definitions (2) permissible signal source impedance: the chip's analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k ? or less. this specification is provided to enable the a/d converter?s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load w ill essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/s or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted.
section 17 a/d converter rev. 6.00 feb 22, 2005 page 694 of 1484 rej09b0103-0600 influences on absolute precision: adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. figure 17-11 shows an example of analog input circuit. a/d converter equivalent circuit chip 20 pf c in = 15 pf 10 k w to 5 k w low-pass filter c to 0.1 m f sensor output impedance sensor input figure 17-11 example of analog input circuit
section 18 d/a converter rev. 6.00 feb 22, 2005 page 695 of 1484 rej09b0103-0600 section 18 d/a converter note: the h8s/2635 group is not equipped with a d/a converter. 18.1 overview the chip has an on-chip d/a converter module with two channels. 18.1.1 features features of the d/a converter module are listed below. ? eight-bit resolution ? two-channel output ? maximum conversion time: 10 s (with 20-pf load capacitance) ? output voltage: 0 v to vref ? d/a output retention in software standby mode ? possible to set module stop mode operation of d/a converter is disenabled by initial values. it is possible to access the register by canceling module stop mode.
section 18 d/a converter rev. 6.00 feb 22, 2005 page 696 of 1484 rej09b0103-0600 18.1.2 block diagram figure 18-1 shows a block diagram of the d/a converter. bus interface module data bus internal data bus 8-bit d/a dadr0 dadr1 dacr control circuit legend: dadr: dadr0, dadr1: d/a control register d/a data register 0, 1 vref avcc da1 da0 avss figure 18-1 block diagram of d/a converter
section 18 d/a converter rev. 6.00 feb 22, 2005 page 697 of 1484 rej09b0103-0600 18.1.3 input and output pins table 18-1 lists the input and output pins used by the d/a converter module. table 18-1 input and output pins of d/a converter module name abbreviation i/o function analog supply voltage avcc input power supply for analog circuits analog ground avss i nput ground and reference voltage for analog circuits analog output 0 da0 output analog output channel 0 analog output 1 da1 output analog output channel 1 reference voltage vref input reference voltage of analog section 18.1.4 register configuration table 18-2 lists the registers of the d/a converter module. table 18-2 d/a converter registers channel name abbreviation r/w initial value address * 0, 1 d/a data register 0 dadr0 r/w h'00 h'ffa4 d/a data register 1 dadr1 r/w h'00 h'ffa5 d/a control register 01 dacr01 r/w h'1f h'ffa6 all module stop control register a mstpcra r/w h'3f h'fdf8 note: * lower 16 bits of the address.
section 18 d/a converter rev. 6.00 feb 22, 2005 page 698 of 1484 rej09b0103-0600 18.2 register descriptions 18.2.1 d/a data registers 0, 1 (dadr0, dadr1) bit 76543210 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d/a data registers 0, 1 (dadr0, dadr1) are 8-bit readable/writable registers that store data to be converted. when analog output is enabled, the value in the d/a data register is converted and output continuously at the analog output pin. the d/a data registers are initialized to h'00 by a reset and in hardware standby mode. 18.2.2 d/a control register 01 (dacr01) bit 76543210 daoe1 daoe0 dae ? ? ? ? ? initial value 0 0 0 1 1 1 1 1 read/write r/w r/w r/w ? ? ? ? ? dacr01 is an 8-bit readable/writable register that controls the operation of the d/a converter module. dacr01 is initialized to h'1f by a reset and in hardware standby mode. bit 7?d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0 analog output da1 is disabled (initial value) 1 d/a conversion is enabled on channel 1. analog output da1 is enabled
section 18 d/a converter rev. 6.00 feb 22, 2005 page 699 of 1484 rej09b0103-0600 bit 6?d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 analog output da0 is disabled (initial value) 1 d/a conversion is enabled on channel 0. analog output da0 is enabled bit 5?d/a enable (dae): controls d/a conversion, in combination with bits daoe0 and daoe1. d/a conversion is controlled independently on channels 0 and 1 when dae = 0. channels 0 and 1 are controlled together when dae = 1. output of the converted results is always controlled independently by daoe0 and daoe1. bit 7 daoe1 bit 6 daoe0 bit 5 dae d/a conversion 00 * disabled on channels 0 and 1 10 enabled on channel 0 disabled on channel 1 1 enabled on channels 0 and 1 100disabled on channel 0 enabled on channel 1 1 enabled on channels 0 and 1 1 * enabled on channels 0 and 1 * : don?t care if the chip enters software standby mode while d/a conversion is enabled, the d/a output is retained and the analog power supply current is the same as during d/a conversion. if it is necessary to reduce the analog power supply current in software standby mode, disable d/a output by clearing both the daoe0 and daoe1 bits to 0. bits 4 to 0?reserved: these bits cannot be modified and are always read as 1.
section 18 d/a converter rev. 6.00 feb 22, 2005 page 700 of 1484 rej09b0103-0600 18.2.3 module stop control register a (mstpcra) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w : : : mstpcra mstpcra is an 8-bit readable/writable registers that performs module stop mode control. when the mstpa2 is set to 1, the d/a converter halts and enters module stop mode at the end of the bus cycle. register read/write is disenabled in module stop mode. see section 23a.5, 23b.5, module stop mode, for details. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 2?module stop (mstpa2): specifies d/a converter (channels 0 and 1) module stop mode. bit 2 mstpa2 description 0 d/a converter (channels 0 and 1) module stop mode is cleared 1 d/a converter (channels 0 and 1) module stop mode is set (initial value)
section 18 d/a converter rev. 6.00 feb 22, 2005 page 701 of 1484 rej09b0103-0600 18.3 operation the d/a converter module has one on-chip d/a converter circuits that can operate independently. d/a conversion is performed continuously whenever enabled by the d/a control register (dacr). when a new value is written in dadr0 or dadr1, conversion of the new value begins immediately. the converted result is output by setting the daoe0 or daoe1 bit to 1. an example of conversion on channel 0 is given next. figure 18-2 shows the timing. ? software writes the data to be converted in dadr0. ? d/a conversion begins when the daoe0 bit in dacr is set to 1. after the elapse of the conversion time, analog output appears at the da0 pin. contents of dadr / 256 vref this output continues until a new value is written in dadr0 or the daoe0 bit is cleared to 0. ? if a new value is written in dadr0, conversion begins immediately. output of the converted result begins after the conversion time. ? when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle a ddress dadr0 daoe0 da0 conversion data (1) conversion data (2) high-impedance state conversion result (1) conversion result (2) t dconv t dconv legend: t dconv : d/a conversion time figure 18-2 d/a conversion (example)
section 18 d/a converter rev. 6.00 feb 22, 2005 page 702 of 1484 rej09b0103-0600
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 703 of 1484 rej09b0103-0600 section 19 motor control pwm timer note: the h8s/2635 group is not equipped with a dtc. 19.1 overview the chip has an on-chip motor control pwm (pulse width modulator) with a maximum capab ility of 16 pulse outputs. 19.1.1 features features of the motor control pwm are given below. ? maximum of 16 pulse outputs ? two 10-bit pwm channels, each with eight outputs. ? each channel is provided with a 10-bit counter (pwcnt) and cycle register (pwcyr). ? duty and output polarity can be set for each output. ? buffered duty registers ? duty registers (pwdtr) are provided with buffer registers (pwbfr), with data transferred automatically every cycle. ? channel 1 has four duty registers and four buffer registers. ? channel 2 has eight duty registers and four buffer registers. ? 0% to 100% duty ? a duty cycle of 0% to 100% can be set by means of a duty register setting. ? five operating clocks ? there is a choice of five operating clocks ( , /2, /4, /8, /16). ? high-speed access via internal 16-bit-bus ? high-speed access is possible via a 16-bit bus interface. ? two interrupt sources ? an interrupt can be requested independently for each channel by a cycle register compare match. ? automatic transfer of register data ? block transfer and one-word data transfer are possible by activating the data transfer controller (dtc). ? module stop mode ? as the initial setting, pwm operation is halted. register access is enabled by clearing module stop mode.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 704 of 1484 rej09b0103-0600 19.1.2 block diagram figure 19-1 shows a block diagram of pwm channel 1. pwcnt1 pwcyr1 pwdtr1a 12 9 0 pwpr1 p/n p/n pwm1a pwm1b pwbfr1a 12 9 0 pwdtr1c p/n p/n pwm1c pwm1d pwbfr1c pwdtr1e p/n p/n pwm1e pwm1f pwbfr1e pwdtr1g p/n p/n pwm1g pwm1h pwbfr1g pwcr1 pwocr1 compare match interrupt request internal data bus bus interface port control legend: pwcr1: pwm control register 1 pwocr1: pwm output control register 1 pwpr1: pwm polarity register 1 pwcnt1: pwm counter 1 pwcyr1: pwm cycle register 1 pwdtr1a, 1c, 1e, 1g: pwm duty registers 1a, 1c, 1e, 1g pwbfr1a, 1c, 1e, 1g: pwm buffer registers 1a, 1c, 1e, 1g , /2, /4, /8, /16 figure 19-1 block diagram of pwm channel 1
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 705 of 1484 rej09b0103-0600 figure 19-2 shows a block diagram of pwm channel 2. pwbfr2a 12 9 0 pwbfr2b pwbfr2c pwbfr2d pwcnt2 pwcyr2 pwocr2 pwpr2 pwdtr2a pwdtr2b pwdtr2c pwdtr2d pwdtr2e pwdtr2f pwdtr2g pwdtr2h p/n pwcr2 p/n p/n p/n p/n p/n p/n p/n pwm2a pwm2b pwm2c pwm2d pwm2e pwm2f pwm2g pwm2h 90 compare match , /2, /4, /8, /16 legend: pwcr2: pwm control register 2 pwocr2: pwm output control register 2 pwpr2: pwm polarity register 2 pwcnt2: pwm counter 2 pwcyr2: pwm cycle register 2 pwdtr2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h: pwm duty registers 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h pwbfr2a, 2b, 2c, 2d: pwm buffer registers 2a, 2b, 2c, 2d internal data bus interrupt request bus interface port control figure 19-2 block diagram of pwm channel 2
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 706 of 1484 rej09b0103-0600 19.1.3 pin configuration table 19-1 shows the pwm pin configuration. table 19-1 pwm pin configuration name abbrev. i/o function pwm output pin 1a pwm1a output channel 1a pwm output pwm output pin 1b pwm1b output channel 1b pwm output pwm output pin 1c pwm1c output channel 1c pwm output pwm output pin 1d pwm1d output channel 1d pwm output pwm output pin 1e pwm1e output channel 1e pwm output pwm output pin 1f pwm1f output channel 1f pwm output pwm output pin 1g pwm1g output channel 1g pwm output pwm output pin 1h pwm1h output channel 1h pwm output pwm output pin 2a pwm2a output channel 2a pwm output pwm output pin 2b pwm2b output channel 2b pwm output pwm output pin 2c pwm2c output channel 2c pwm output pwm output pin 2d pwm2d output channel 2d pwm output pwm output pin 2e pwm2e output channel 2e pwm output pwm output pin 2f pwm2f output channel 2f pwm output pwm output pin 2g pwm2g output channel 2g pwm output pwm output pin 2h pwm2h output channel 2h pwm output
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 707 of 1484 rej09b0103-0600 19.1.4 register configuration table 19-2 shows the register configuration of the pwm. table 19-2 pwm registers channel name abbrev. r/w initial value address * 1 1 pwm control register 1 pwcr1 r/w h'c0 h'fc00 pwm output control register 1 pwocr1 r/w h'00 h'fc02 pwm polarity register 1 pwpr1 r/w h'00 h'fc04 pwm cycle register 1 pwcyr1 r/w h'ffff h'fc06 pwm buffer register 1a pwbfr1a r/w h'ec00 h'fc08 pwm buffer register 1c pwbfr1c r/w h'ec00 h'fc0a pwm buffer register 1e pwbfr1e r/w h'ec00 h'fc0c pwm buffer register 1g pwbfr1g r/w h'ec00 h'fc0e 2 pwm control register 2 pwcr2 r/w h'c0 h'fc10 pwm output control register 2 pwocr2 r/w h'00 h'fc12 pwm polarity register 2 pwpr2 r/w h'00 h'fc14 pwm cycle register 2 pwcyr2 r/w h'ffff h'fc16 pwm buffer register 2a pwbfr2a r/w h'ec00 h'fc18 pwm buffer register 2b pwbfr2b r/w h'ec00 h'fc1a pwm buffer register 2c pwbfr2c r/w h'ec00 h'fc1c pwm buffer register 2d pwbfr2d r/w h'ec00 h'fc1e all module stop control register d mstpcrd r/w b'11 ****** h'fc60 note: 1. lower 16 bits of the address.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 708 of 1484 rej09b0103-0600 19.2 register descriptions 19.2.1 pwm control registers 1 and 2 (pwcr1, pwcr2) bit 76543210 ? ? ie cmf cst cks2 cks1 cks0 initial value 1 1 0 0 0 0 0 0 read/write ? ? r/w r/w * r/w r/w r/w r/w note: * only 0 can be written, to clear the flag. pwcr is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and counter (pwcnt) clock selection. it also contains a flag that indicates a compare match with the cycle register (pwcyr). pwcr1 is the channel 1 register, and pwcr2 is the channel 2 register. pwcr is initialized to h'c0 upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. bits 7 and 6?reserved: they are always read as 1 and cannot be modified. bit 5?interrupt enable (ie): bit 5 selects enabling or disabling of an interrupt in the event of a compare match with the pwcyr register for the corresponding channel. bit 5: ie description 0 interrupt disabled (initial value) 1 interrupt enabled
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 709 of 1484 rej09b0103-0600 bit 4?compare match flag (cmf): bit 4 indicates the occurrence of a compare match with the pwcyr register for the corresponding channel. bit 4: cmf description 0 [clearing conditions] (initial value) ? when 0 is written to cmf after reading cmf = 1 ? when the dtc is activated by a compare match interrupt, and the disel bit in the dtc?s mrb register is 0 1 [setting condition] ? when pwcnt = pwcyr bit 3?counter start (cst): bit 3 selects starting or stopping of the pwcnt counter for the corresponding channel. bit 3: cst description 0 pwcnt is stopped (initial value) 1 pwcnt is started bits 2 to 0?clock select (cks): bits 2 to 0 select the clock for the pwcnt counter in the corresponding channel. bit 2: cks2 bit 1: cks1 bit 0: cks0 description 000internal clock: c ounts on /1 (initial value) 1 internal clock: counts on /2 1 0 internal clock: counts on /4 1 internal clock: counts on /8 1 ** internal clock: counts on /16 * : don?t care
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 710 of 1484 rej09b0103-0600 19.2.2 pwm output control registers 1 and 2 (pwocr1, pwocr2) pwocr1 bit 76543210 oe1h oe1g oe1f oe1e oe1d oe1c oe1b oe1a initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwocr2 bit 76543210 oe2h oe2g oe2f oe2e oe2d oe2c oe2b oe2a initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwocr is an 8-bit read/write register that enables or disables pwm output. pwocr1 controls outputs pwm1h to pwm1a, and pwocr2 controls outputs pwm2h to pwm2a. pwocr is initialized to h'00 upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bits 7 to 0?output enable (oe): each of these bits enables or disables the corresponding pwm output. bits 7 to 0: oe description 0 pwm output is disabled (initial value) 1 pwm output is enabled
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 711 of 1484 rej09b0103-0600 19.2.3 pwm polarity registers 1 and 2 (pwpr1, pwpr2) pwpr1 bit 76543210 ops1h ops1g ops1f ops1e ops1d ops1c ops1b ops1a initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwpr2 bit 76543210 ops2h ops2g ops2f ops2e ops2d ops2c ops2b ops2a initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwpr is an 8-bit read/write register that selects the pwm output polarity. pwpr1 controls outputs pwm1h to pwm1a, and pwpr2 controls outputs pwm2h to pwm2a. pwpr is initialized to h'00 upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bits 7 to 0?output polarity select (ops): each of these bits selects the polarity of the corresponding pwm output. bits 7 to 0: ops description 0 pwm direct output (initial value) 1 pwm inverse output
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 712 of 1484 rej09b0103-0600 19.2.4 pwm counters 1 and 2 (pwcnt1, pwcnt2) bit 1514131211109876543210 ?????? initial value1111110000000000 read/write ???????????????? pwcnt is a 10-bit up-counter incremented by the input clock. the input clock is selected by clock select bits 2 to 0 (cks2 to cks0) in pwcr. pwcnt1 is used as the channel 1 time base, and pwcnt2 as the channel 2 time base. pwcnt is initialized to h'fc00 when the counter start bit (cst) in pwcr is cleared to 0, and also upon reset and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 713 of 1484 rej09b0103-0600 19.2.5 pwm cycle registers 1 and 2 (pwcyr1, pwcyr2) bit 1514131211109876543210 ?????? initial value1111111111111111 read/write ??????r/wr/wr/wr/wr/wr/wr/wr/wr/wr/w pwcyr is a 16-bit read/write register that sets the pwm conversion cycle. when a pwcyr compare match occurs, pwcnt is cleared and data is transferred from the buffer register (pwbfr) to the duty register (pwdtr). pwcyr1 is used for the channel 1 conversion cycle setting, and pwcyr2 for the channel 2 conversion cycle setting. pwcyr should be written to only while pwcnt is stopped. a value of h'fc00 must not be set. pwcyr is initialized to h'ffff upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. 01 01 n n ? 1 pwcnt (lower 10 bits) pwcyr (lower 10 bits) n ? 2 compare match compare match figure 19-3 cycle register compare match
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 714 of 1484 rej09b0103-0600 19.2.6 pwm duty registers 1a, 1c, 1e, 1g (pwdtr1a, 1c, 1e, 1g) bit 1514131211109876543210 ? ? ? ots ? ? dt9 dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 initial value1110110000000000 read/write ???????????????? there are four pwdtr1x registers (pwdtr1a, 1c, 1e, 1g). pwdtr1a is used for outputs pwm1a and pwm1b, pwdtr1c for outputs pwm1c and pwm1d, pwdtr1e for outputs pwm1e and pwm1f, and pwdtr1g for outputs pwm1g and pwm1h. pwdtr1 cannot be read or written to directly. when a pwcyr1 compare match occurs, data is transferred from buffer register 1 (pwbfr1) to pwdtr1. pwdtr1x is initialized to h'ec00 when the counter start bit (cst) in pwcr1 is cleared to 0, and also upon reset and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bits 15 to 13?reserved: these bits cannot be read from or written to.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 715 of 1484 rej09b0103-0600 bit 12?output terminal select (ots): bit 12 selects the pin used for pwm output according to the value in bit 12 in the buffer register that is transferred by a pwcyr1 compare match. unselected pins output a low level (or a high level when the corresponding bit in pwpr1 is set to 1). register bit 12: ots description pwdtr1a 0 pwm1a output selected (initial value) 1 pwm1b output selected pwdtr1c 0 pwm1c output selected (initial value) 1 pwm1d output selected pwdtr1e 0 pwm1e output selected (initial value) 1 pwm1f output selected pwdtr1g 0 pwm1g output selected (initial value) 1 pwm1h output selected bits 11 and 10?reserved: these bits cannot be read from or written to. bits 9 to 0?duty (dt): bits 9 to 0 set the pwm output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a pwcyr1 compare match. a high level (or a low level when the corresponding bit in pwpr1 is set to 1) is output from the time pwcnt1 is cleared by a pwcyr1 compare match until a pwdtr1 compare match occurs. when all the bits are 0, there is no high-level output period (no low-level output period when the corresponding bit in pwpr1 is set to 1). pwcnt1 (lower 10 bits) pwcyr1 (lower 10 bits) pwdtr1 (lower 10 bits) pwm output on selected pin pwm output on unselected pin compare match 01 n m m ? 2m ? 1m n ? 10 figure 19-4 duty register compare match (ops = 0 in pwpr1)
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 716 of 1484 rej09b0103-0600 01 n ? 10 n m n ? 2 pwcnt1 (lower 10 bits) pwcyr1 (lower 10 bits) pwdtr1 (lower 10 bits) pwm output (m = 0) pwm output (0 < m < n) pwm output (n m) figure 19-5 differences in pwm output according to duty register set value (ops = 0 in pwpr1) 19.2.7 pwm buffer registers 1a, 1c, 1e, 1g (pwbfr1a, 1c, 1e, 1g) bit 1514131211109876543210 ? ? ? ots ? ? dt9 dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 initial value1110110000000000 read/write ? ? ? r/w ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w there are four 16-bit read/write pwbfr1 registers (pwbfr1a, 1c, 1e, 1g). when a pwcyr1 compare match occurs, data is transferred from pwbfr1a to pwdtr1a, from pwbfr1c to pwdtr1c, from pwbfr1e to pwdtr1e, and from pwbfr1g to pwdtr1g. pwbfr1 is initialized to h'ec00 upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 717 of 1484 rej09b0103-0600 bits 15 to 13?reserved: they are always read as 1 and cannot be modified. bit 12?output terminal select (ots): bit 12 is the data transferred to bit 12 of pwdtr1. bits 11 and 10?reserved: they are always read as 1 and cannot be modified. bits 9 to 0?duty (dt): bits 9 to 0 comprise the data transferred to bits 9 to 0 in pwdtr1. 19.2.8 pwm duty registers 2a to 2h (pwdtr2a to pwdtr2h) bit 1514131211109876543210 ??????dt9dt8dt7dt6dt5dt4dt3dt2dt1dt0 initial value1110110000000000 read/write ???????????????? there are eight pwdtr2 registers (pwdtr2a to pwdtr2h). pwdtr2a is used for output pwm2a, pwdtr2b for output pwm2b, pwdtr2c for output pwm2c, pwdtr2d for output pwm2d, pwdtr2e for output pwm2e, pwdtr2f for output pwm2f, pwdtr2g for output pwm2g, and pwdtr2h for output pwm2h. pwdtr2 cannot be read or written to directly. when a pwcyr2 compare match occurs, data is transferred from buffer register 2 (pwbfr2) to pwdtr2. pwdtr2 is initialized to h'ec00 when the counter start bit (cst) in pwcr2 is cleared to 0, and also upon reset and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bits 15 to 10?reserved: these bits cannot be read from or written to.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 718 of 1484 rej09b0103-0600 bits 9 to 0?duty (dt): bits 9 to 0 set the pwm output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a pwcyr2 compare match. a high level (or a low level when the corresponding bit in pwpr2 is set to 1) is output from the time pwcnt2 is cleared by a pwcyr2 compare match until a pwdtr2 compare match occurs. when all the bits are 0, there is no high-level output period (no low-level output period when the corresponding bit in pwpr2 is set to 1). pwcnt2 (lower 10 bits) pwcyr2 (lower 10 bits) pwdtr2 (lower 10 bits) pwm output compare match 01 n m m ? 2m ? 1m n ? 10 figure 19-6 duty register compare match (ops = 0 in pwpr2) 01 n ? 10 n m n ? 2 pwcnt2 (lower 10 bits) pwcyr2 (lower 10 bits) pwdtr2 (lower 10 bits) pwm output (m = 0) pwm output (0 < m < n) pwm output (n m) figure 19-7 differences in pwm output according to duty register set value (ops = 0 in pwpr2)
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 719 of 1484 rej09b0103-0600 19.2.9 pwm buffer registers 2a to 2d (pwbfr2a to pwbfr2d) bit 1514131211109876543210 ? ? ? tds ? ? dt9 dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 initial value1110110000000000 read/write ? ? ? r/w ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w there are four 16-bit read/write pwbfr2 registers (pwbfr2a to pwbfr2d). when a pwcyr2 compare match occurs, data is transferred from pwbfr2a to pwdtr2a or pwdtr2e, from pwbfr2b to pwdtr2b or pwdtr2f, from pwbfr2c to pwdtr2c or pwdtr2g, and from pwbfr2d to pwdtr2d or pwdtr2h. the transfer destination is determined by the value of the tds bit. pwbfr2 is initialized to h'ec00 upon reset, and in standby mode, watch mode * , subactive mode * , subsleep mode * , and module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. bits 15 to 13?reserved: they are always read as 1 and cannot be modified. bit 12?transfer destination select (tds): bit 12 selects the pwdtr2 register to which data is to be transferred. register bit 12: tds description pwbfr2a 0 pwdtr2a selected (initial value) 1 pwdtr2e selected pwbfr2b 0 pwdtr2b selected (initial value) 1 pwdtr2f selected pwbfr2c 0 pwdtr2c selected (initial value) 1 pwdtr2g selected pwbfr2d 0 pwdtr2d selected (initial value) 1 pwdtr2h selected bits 11 and 10?reserved: they are always read as 1 and cannot be modified. bits 9 to 0?duty (dt): bits 9 to 0 comprise the data transferred to bits 9 to 0 in pwdtr2.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 720 of 1484 rej09b0103-0600 19.2.10 module stop control register d (mstpcrd) bit 76543210 mstpd7 mstpd6 mstpd5 mstpd4 mstpd3 mstpd2 mstpd1 mstpd0 initial value 1 1 undefined undefined undefined undefined undefined undefined read/write r/w r/w ? ? ? ? ? ? mstpcrd is an 8-bit read/write register that performs module stop mode control. when the mstpd7 bit is set to 1, pwm timer operation is stopped at the end of the bus cycle, and module stop mode is entered. for details, see section 23a.5, 23b.5, module stop mode. mstpcrd is initialized by a reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?module stop (mstpd7): bit 7 specifies the pwm module stop mode. bit 7: mstpd7 description 0 pwm module stop mode is cleared 1 pwm module stop mode is set (initial value)
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 721 of 1484 rej09b0103-0600 19.3 bus master interface 19.3.1 16-bit data registers pwcyr1/2, pwbfr1a/c/e/g, and pwbfr2a/b/c/d are 16-bit registers. these registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. they cannot be read by 8-bit access; 16-bit access must always be used. h l pwcyr1 bus master internal data bus bus interface module data bus figure 19-8 16-bit register access operation (bus master ? ? ? ? pwcyr1 (16 bits)) 19.3.2 8-bit data registers pwcr1/2, pwocr1/2, and pwpr1/2 are 8-bit registers that can be read and written to in 8-bit units. these registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16-bit access; in this case, the lower 8 bits w ill always be read as h'ff. h l pwcr1 bus master internal data bus bus interface module data bus figure 19-9 8-bit register access operation (bus master ? ? ? ? pwcr1 (upper 8 bits))
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 722 of 1484 rej09b0103-0600 19.4 operation 19.4.1 pwm channel 1 operation pwm waveforms are output from pins pwm1a to pwm1h as shown in figure 19-10. initial settings: set the pwm output polarity in pwpr1; enable the pins for pwm output with pwocr1; select the clock to be input to pwcnt1 with bits cks2 to cks0 in pwcr1; set the pwm conversion cycle in pwcyr1; and set the first frame of data in pwbfr1a, pwbfr1c, pwbfr1e, and pwbfr1g. activation: when the cst bit in pwcr1 is set to 1, a compare match between pwcnt1 and pwcyr1 is generated. data is transferred from pwbfr1a to pwdtr1a, from pwbfr1c to pwdtr1c, from pwbfr1e to pwdtr1e, and from pwbfr1g to pwdtr1g. pwcnt1 starts counting up. at the same time the cmf bit in pwcr1 is set, so that, if the ie bit in pwcr1 has been set, an interrupt can be requested or the dtc can be activated. waveform output: the pwm outputs selected by the ots bits in pwdtr1a/c/e/g go high when a compare match occurs between pwcnt1 and pwcyr1. the pwm outputs not selected by the ots bits are low. when a compare match occurs between pwcnt1 and pwdtr1a/c/e/g, the corresponding pwm output goes low. if the corresponding bit in pwpr1 is set to 1, the output is inverted. pwbfr1a pwcyr1 pwm1a pwdtr1a pwm1b ots (pwdtr1a) = 1 ots (pwdtr1a) = 0 ots (pwdtr1a) = 1 ots (pwdtr1a) = 0 figure 19-10 pwm channel 1 operation
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 723 of 1484 rej09b0103-0600 next frame: when a compare match occurs between pwcnt1 and pwcyr1, data is transferred from pwbfr1a to pwdtr1a, from pwbfr1c to pwdtr1c, from pwbfr1e to pwdtr1e, and from pwbfr1g to pwdtr1g. pwcnt1 is reset and starts counting up from h'000. the cmf bit in pwcr1 is set, and if the ie bit in pwcr1 has been set, an interrupt can be requested or the dtc can be activated. stopping: when the cst bit in pwcr1 is cleared to 0, pwcnt1 is reset and stops. all pwm outputs go low (or high if the corresponding bit in pwpr1 is set to 1). 19.4.2 pwm channel 2 operation pwm waveforms are output from pins pwm2a to pwm2h as shown in figure 19-11. initial settings: set the pwm output polarity in pwpr2; enable the pins for pwm output with pwocr2; select the clock to be input to pwcnt2 with bits cks2 to cks0 in pwcr2; set the pwm conversion cycle in pwcyr2; and set the first frame of data in pwbfr2a, pwbfr2b, pwbfr2c, and pwbfr2d. activation: when the cst bit in pwcr2 is set to 1, a compare match between pwcnt2 and pwcyr2 is generated. data is transferred from pwbfr2a to pwdtr2a or pwdtr2e, from pwbfr2b to pwdtr2b or pwdtr2f, from pwbfr2c to pwdtr2c or pwdtr2g, and from pwbfr2d to pwdtr2d or pwdtr2h, according to the value of the tds bit. pwcnt2 starts counting up. at the same time the cmf bit in pwcr2 is set, so that, if the ie bit in pwcr2 has been set, an interrupt can be requested or the dtc can be activated. waveform output: the pwm outputs go high when a compare match occurs between pwcnt2 and pwcyr2. when a compare match occurs between pwcnt2 and pwdtr2a to pwdtr2h, the corresponding pwm output goes low. if the corresponding bit in pwpr2 is set to 1, the output is inverted.
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 724 of 1484 rej09b0103-0600 tds (pwbfr2a) = 0 tds (pwbfr2a) = 1 tds (pwbfr2a) = 0 pwbfr2a pwcyr2 pwm2a pwdtr2a pwm2b pwdtr2e figure 19-11 pwm channel 2 operation next frame: when a compare match occurs between pwcnt2 and pwcyr2, data is transferred from pwbfr2a to pwdtr2a or pwdtr2e, from pwbfr2b to pwdtr2b or pwdtr2f, from pwbfr2c to pwdtr2c or pwdtr2g, and from pwbfr2d to pwdtr2d or pwdtr2h, according to the value of the tds bit. pwcnt2 is reset and starts counting up from h'000. the cmf bit in pwcr2 is set, and if the ie bit in pwcr2 has been set, an interrupt can be requested or the dtc can be activated. stopping: when the cst bit in pwcr2 is cleared to 0, pwcnt2 is reset and stops. pwdtr2a to pwdtr2h are reset. all pwm outputs go low (or high if the corresponding bit in pwpr2 is set to 1).
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 725 of 1484 rej09b0103-0600 19.5 usage note contention between buffer register write and compare match if a pwbfr write is performed in the state immediately after a cycle register compare match, the pwm output does not change, but as the duty register is also rewritten at the same time as the buffer register, normal pwm output will not be achieved. if a pwbfr write is performed in the state immediately after a cycle register compare match, the buffer register and duty register are overwritten. pwm output changed by the cycle register compare match is not changed in the overwrite of the duty register due to contention. this may result in unanticipated duty output. in the case of channel 2, the duty register used as the transfer destination is selected by the tds bit of the buffer register when an overwrite of the duty register occurs due to contention. this can also result in an unintended overwrite of the duty register. buffer register rewriting must be completed before automatic transfer by the dtc * (data transfer controller), exception handling due to a compare match interrupt, or the occurrence of a cycle register compare match on detection of the rise of cmf (compare match flag) in pwcr. note: * the dtc is not implemented in the h8s/2635 and h8s/2634. t 1 t w t w t 2 a ddress write signal pwcnt (lower 10 bits) pwbfr pwdtr pwm output cmf buffer register address compare match 0 m n m n figure 19-12 pwm channel 1 operation
section 19 motor control pwm timer rev. 6.00 feb 22, 2005 page 726 of 1484 rej09b0103-0600
section 20 ram rev. 6.00 feb 22, 2005 page 727 of 1484 rej09b0103-0600 section 20 ram note: the h8s/2635 group is not equipped with a dtc. 20.1 overview the h8s/2636 has 4 kbytes, and h8s/2638, h8s/2639, and h8s/2630 have 16 kbytes of on-chip high-speed static ram. the h8s/2635 has 6 kbytes of on-chip ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 20.1.1 block diagram figure 20-1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffe000 h'ffe002 h'ffe004 h'ffffc0 h'ffe001 h'ffe003 h'ffe005 h'ffffc1 h'fffffe h'ffffff h'ffefbe h'ffefbf figure 20-1 (a) block diagram of ram (h8s/2636)
section 20 ram rev. 6.00 feb 22, 2005 page 728 of 1484 rej09b0103-0600 internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffb000 h'ffb002 h'ffb004 h'ffffc0 h'ffb001 h'ffb003 h'ffb005 h'ffffc1 h'fffffe h'ffffff h'ffbfbe h'ffbfbf figure 20-1 (b) block diagram of ram (h8s/2638, h8s/2639, and h8s/2630)
section 20 ram rev. 6.00 feb 22, 2005 page 729 of 1484 rej09b0103-0600 internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffd800 h'ffd802 h'ffd804 h'ffffc0 h'ffd801 h'ffd803 h'ffd805 h'ffffc1 h'fffffe h'ffffff h'ffbfbe h'ffbfbf figure 20-1 (c) block diagram of ram (h8s/2635 group) 20.1.2 register configuration the on-chip ram is controlled by syscr. table 20-1 shows the address and initial value of syscr. table 20-1 ram register name abbreviation r/w initial value address * system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address.
section 20 ram rev. 6.00 feb 22, 2005 page 730 of 1484 rej09b0103-0600 20.2 register descriptions 20.2.1 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 ? 0 r/w 1 ? 0 ? bit initial value r/w : : : the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 20.3 operation when the rame bit is set to 1, accesses to addresses h'ffe000 to h'ffefbf (for the h8s/2636), h'ffb000 to h'ffefbf (for the h8s/2638, h8s/2639, and h8s/2630), h'ffd800 to h'ffefbf (for the h8s/2635 group), or h'ffffc0 to h'ffffff in the chip are directed to the on-chip ram. when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written to and read in byte or word units. each type of access can be performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address.
section 20 ram rev. 6.00 feb 22, 2005 page 731 of 1484 rej09b0103-0600 20.4 usage notes when using the dtc: dtc register information can be located in addresses h'ffebc0 to h'ffefbf. when the dtc is used, the rame bit must not be cleared to 0. reserved areas: addresses h'ffb000 to h'ffdfff in the h8s/2636 and h'ffb000 to h'ffd7ff in the h8s/2635 group are reserved areas that cannot be read or written to. when the rame bit is cleared to 0, the off-chip address space is accessed.
section 20 ram rev. 6.00 feb 22, 2005 page 732 of 1484 rej09b0103-0600
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 733 of 1484 rej09b0103-0600 section 21a rom (h8s/2636 group) 21a.1 overview the h8s/2636 has 128 kbytes of on-chip flash memory, or 128 kbytes of on-chip mask rom. the rom is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the on-chip rom is enabled and disabled by setting the mode pins (md2 to md0). the flash memory version can be erased and programmed on-board, as well as with a special- purpose prom programmer. 21a.1.1 block diagram figure 21a-1 shows a block diagram of 128-kbyte rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff figure 21a-1 block diagram of rom (128 kbytes) 21a.1.2 register configuration the h8s/2636 operating mode is controlled by the mode pins and the mdcr register. the register configuration is shown in table 21a-1.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 734 of 1484 rej09b0103-0600 table 21a-1 register configuration register name abbreviation r/w initial value address * mode control register mdcr r/w undefined h'fde7 note: * lower 16 bits of the address. 21a.2 register descriptions 21a.2.1 mode control register (mdcr) bit:76543210 ?????mds2mds1mds0 initial value:10000? * ? * ? * r/w:r/w???? r r r note: * determined by pins md2 to md0. mdcr is an 8-bit register used to monitor the current h8s/2636 group operating mode. bit 7?reserved: only 1 should be written to these bits. bits 6 to 3?reserved: these bits are always read as 0 and cannot be modified. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be modified. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. 21a.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the on-chip rom is enabled and disabled by setting the mode pins (md2, md1, and md0). these settings are shown in table 21a-2.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 735 of 1484 rej09b0103-0600 table 21a-2 operating modes and rom (f-ztat version) mode pins operating mode fwe md2 md1 md0 on-chip rom mode 0 ? 0 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (128 kbytes) mode 7 advanced single-chip mode 1 enabled (128 kbytes) mode 8 ? 1 0 0 0 ? mode 9 1 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (128 kbytes) mode 11 boot mode (advanced single-chip mode) * 2 1 enabled (128 kbytes) mode 12 ? 1 0 0 ? mode 13 1 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (128 kbytes) mode 15 user program mode (advanced single- chip mode) * 2 1 enabled (128 kbytes) notes: 1. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip rom enabled. 2. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 736 of 1484 rej09b0103-0600 table 21a-3 operating modes and rom (mask rom version) mode pins operating mode md2 md1 md0 on-chip rom mode 0 ? 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 100disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (128 kbytes) mode 7 advanced single-chip mode 1 enabled (128 kbytes)
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 737 of 1484 rej09b0103-0600 21a.4 flash memory overview 21a.4.1 features the h8s/2636 has 128 kbytes of on-chip flash memory, or 128 kbytes of on-chip mask rom. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. to erase the entire flash memory, each block must be erased in turn. blocks of 1 kbyte, 8 kbytes, 16 kbytes, 28 kbytes, and 32 kbytes can be erased as required. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte progra mming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the lsi?s bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 738 of 1484 rej09b0103-0600 ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. 21a.4.2 block diagram module bus bus interface/controller flash memory (128 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flpwcr flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register flash memory power control register legend: flmcr1: flmcr2: ebr1: ebr2: ramer: flpwcr: figure 21a-2 block diagram of flash memory
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 739 of 1484 rej09b0103-0600 21a.4.3 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21a-3. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode res = 0 fwe = 1fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md0 = 0, md1 = 0, md2 = 0, p14 = 0, p16 = 0, pf0 = 1 res = 0 md2 = 0, md1 = 1, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 21a-3 flash memory state transitions
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 740 of 1484 rej09b0103-0600 21a.4.4 on-board programming modes boot mode flash memory chip ram host programming control program sci application program (old version) new application program flash memory chip ram host sci application program (old version) boot program area new application program flash memory chip ram host sci flash memory preprogramming erase boot program new application program flash memory chip program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 741 of 1484 rej09b0103-0600 user program mode flash memory chip ram host programming/ erase control program sci boot program new application program flash memory chip ram host sci new application program flash memory chip ram host sci flash memory erase boot program new application program flash memory chip program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 742 of 1484 rej09b0103-0600 21a.4.5 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 21a-4 reading overlap ram data in user mode or user program mode when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 743 of 1484 rej09b0103-0600 application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 21a-5 writing overlap ram data in user program mode 21a.4.6 differences between boot mode and user program mode table 21a-4 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 744 of 1484 rej09b0103-0600 21a.4.7 block configuration the flash memory is divided into two 32 kbytes blocks, one 28 kbytes block, one 16 kbytes block, two 8 kbytes blocks, and four 1 kbyte blocks. address h'00000 a ddress h'1ffff 128 kbytes 28 kbytes 32 kbytes 32 kbytes 16 kbytes 8 kbytes 8 kbytes 1 kbyte 4 figure 21a-6 block configuration
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 745 of 1484 rej09b0103-0600 21a.5 pin configuration the flash memory is controlled by means of the pins shown in table 21a-5. table 21a-5 pin configuration pin name abbreviation i/o function reset res input reset flash write enable fwe input flash program/erase protection by hardware mode 2 md2 input sets lsi operating mode mode 1 md1 input sets lsi operating mode mode 0 md0 input sets lsi operating mode port f0 pf0 input sets lsi operating mode when md2 = md1 = md0 = 0 port 16 p16 input sets lsi operating mode when md2 = md1 = md0 = 0 port 14 p14 input sets lsi operating mode when md2 = md1 = md0 = 0 transmit data txd1 output serial transmit data output receive data rxd1 input serial receive data input
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 746 of 1484 rej09b0103-0600 21a.6 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 21a-6. table 21a-6 register configuration register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 4 r/w h'00 * 2 h'ffa8 flash memory control register 2 flmcr2 * 4 r h'00 h'ffa9 erase block register 1 ebr1 * 4 r/w h'00 * 3 h'ffaa erase block register 2 ebr2 * 4 r/w h'00 * 3 h'ffab ram emulation register ramer * 4 r/w h'00 h'fedb flash memory power control register flpwcr * 4 r/w h'00 * 3 h'ffac notes: 1. lower 16 bits of the address. 2. when a high level is input to the fwe pin, the initial value is h'80. 3. when a low level is input to the fwe pin, or if a high level is input and the swe1 bit in flmcr1 is not set, these registers are initialized to h'00. 4. flmcr1, flmcr2, ebr1, and ebr2, ramer, and flpwcr are 8-bit registers. use byte access on these registers.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 747 of 1484 rej09b0103-0600 21a.7 register descriptions 21a.7.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the pv or ev bit. program mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode for on- chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read w ill return h'00, and writes are invalid. writes are enabled only in the following cases: writes to bit swe of flmcr1 enabled when fwe = 1, to bits esu, psu, ev, and pv when fwe = 1 and swe = 1, to bit e when fwe = 1, swe = 1 and esu = 1, and to bit p when fwe = 1, swe = 1, and psu = 1. bit:76543210 fwe swe esu psu ev pv e p initial value: ? * 0000000 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. bit 7?flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7: fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 748 of 1484 rej09b0103-0600 bit 6?software write enable bit (swe): enables or disables flash memory programming and erasing. set this bit when setting bits 5 to 0, bits 7 to 0 of ebr1, and bits 1 and 0 of ebr2. bit 6: swe description 0 writes disabled (initial value ) 1 writes enabled [setting condition] ? when fwe = 1 bit 5?erase setup bit (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit in flmcr1 to 1. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5: esu description 0 erase setup cleared (initial value ) 1 erase setup [setting condition] ? when fwe = 1 and swe = 1 bit 4?program setup bit (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit in flmcr1 to 1. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4: psu description 0 program setup cleared (initial value ) 1 program setup [setting condition] ? when fwe = 1 and swe = 1 bit 3?erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3: ev description 0 erase-verify mode cleared (initial value ) 1 transition to erase-verify mode [setting condition] ? when fwe = 1 and swe = 1
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 749 of 1484 rej09b0103-0600 bit 2?program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2: pv description 0 program-verify mode cleared (initial value ) 1 transition to program-verify mode [setting condition] ? when fwe = 1 and swe = 1 bit 1?erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1: e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] ? when fwe = 1, swe = 1, and esu = 1 bit 0?program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time. bit 0: p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] ? when fwe = 1, swe = 1, and psu = 1
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 750 of 1484 rej09b0103-0600 21a.7.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00. bit:76543210 fler??????? initial value:00000000 r/w:r ??????? note: flmcr2 is a read-only register, and should not be written to. bit 7?flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7: fler description 0 flash memory is operating normally (initial value ) flash memory program/erase protection (error protection) is disabled [clearing condition] ? reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] ? see section 21a.10.3, error protection bits 6 to 0?reserved: these bits always read 0.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 751 of 1484 rej09b0103-0600 21a.7.3 erase block register 1 (ebr1) ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid. the flash memory block configuration is shown in table 21a-6. bit:76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 21a.7.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin. bit 0 w ill be initialized to 0 if bit swe of flmcr1 is not set, even though a high level is input to pin fwe. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. bits 7 to 2 are reserved and must only be written with 0. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid. the flash memory block configuration is shown in table 21a-7. bit:76543210 ??????eb9eb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 752 of 1484 rej09b0103-0600 table 21a-7 flash memory erase blocks (h8s/2636) block (size) addresses eb0 (1 kbyte) h'000000 to h'0003ff eb1 (1 kbyte) h'000400 to h'0007ff eb2 (1 kbyte) h'000800 to h'000bff eb3 (1 kbyte) h'000c00 to h'000fff eb4 (28 kbytes) h'001000 to h'007fff eb5 (16 kbytes) h'008000 to h'00bfff eb6 (8 kbytes) h'00c000 to h'00dfff eb7 (8 kbytes) h'00e000 to h'00ffff eb8 (32 kbytes) h'010000 to h'017fff eb9 (32 kbytes) h'018000 to h'01ffff 21a.7.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer initialized to h'00 by a reset and in hardware standby mode. it is not initialized by software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 21a-8. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit:76543210 ????ramsram2ram1ram0 initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w bits 7 and 6?reserved: these bits always read 0. bits 5 and 4?reserved: only 0 may be written to these bits.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 753 of 1484 rej09b0103-0600 bit 3?ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 3: rams description 0 emulation not selected (initial value ) program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2, 1 and 0?flash memory area selection: these bits are used together with bit 3 to select the flash memory area to be overlapped with ram (see table 21a-7). table 21a-8 flash memory area divisions (h8s/2636) addresses block name rams ram2 ram1 ram0 h'ffe000 to h'ffe3ff ram area 1 kbyte 0 *** h'000000 to h'0003ff eb0 (1 kbyte) 1 0 0 * h'000400 to h'0007ff eb1 (1 kbyte) 1 0 1 * h'000800 to h'000bff eb2 (1 kbyte) 1 1 0 * h'000c00 to h'000fff eb3 (1 kbyte) 1 1 1 * * : don't care 21a.7.6 flash memory power control register (flpwcr) bit:76543210 pdwnd??????? initial value:00000000 r/w:r/wrrrrrrr flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode * . note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask version only. these functions cannot be used with the other versions.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 754 of 1484 rej09b0103-0600 bit 7?power-down disable (pdwnd): enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. for details, see section 21a.14, flash memory and power-down states. the subactive mode can be used in the u-mask version only. when writing to this bit in other versions, be sure to write 0. bit 7: pdwnd description 0 transition to flash memory power-down mode enabled (initial value) 1 transition to flash memory power-down mode disabled bits 6 to 0?reserved: these bits always read 0. 21a.8 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 21a-9. for a diagram of the transitions to the various flash memory modes, see figure 21a-3. table 21a-9 setting on-board programming modes mode fwe md2 md1 md0 boot mode expanded mode 1 0 1 0 single-chip mode 0 1 1 user program mode expanded mode 1 1 1 0 single-chip mode 1 1 1
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 755 of 1484 rej09b0103-0600 21a.8.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset-start is executed after the lsi?s pins have been set to boot mode, the boot program built into the lsi is started and the programming control program prepared in the host is serially transmitted to the lsi via the sci. in the lsi, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 21a-7, and the boot mode execution procedure in figure 21a-8. rxd1 txd1 sci1 lsi flash memory write data reception verify data transmission host on-chip ram figure 21a-7 system configuration in boot mode
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 756 of 1484 rej09b0103-0600 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate chip measures low period of h'00 data transmitted by host chip calculates bit rate and sets value in bit rate register after bit rate adjustment, chip transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, lsi transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte chip transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units chip transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, chip transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 21a-8 boot mode execution procedure
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 757 of 1484 rej09b0103-0600 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h00 data) high period (1 or more bits) when boot mode is initiated, the lsi measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/r eceive format should be set as follows: 8-bit data, 1 stop bit, no parity. the lsi calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the lsi. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host?s transmission bit rate and the lsi?s system clock frequency, there will be a discrepancy between the bit rates of the host and the lsi. set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the sci properly. table 21a-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the lsi bit rate is possible. the boot program should be executed within this system clock range. table 21a-10 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency for which automatic adjustment of lsi bit rate is possible 4,800 bps 4 to 20 mhz 9,600 bps 8 to 20 hhz 19,200 bps 16 to 20 mhz note: the system clock frequency used in boot mode is generated by an external crystal oscillator element. pll frequency multiplication is not used.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 758 of 1484 rej09b0103-0600 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 21a-9. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffefbf h'ffe000 h'ffe7ff h'ffe800 programming control program area (1.9 kbytes) boot program area (2 kbytes) note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. figure 21a-9 ram areas in boot mode notes on use of boot mode: ? when the chip comes out of reset in boot mode, it measures the low-level period of the input at the sci?s rxd1 pin. the reset should end with rxd1 high. after the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the rxd1 pin. ? in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. ? interrupts cannot be used while the flash memory is being programmed or erased. ? the rxd1 and txd1 pins should be pulled up on the board.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 759 of 1484 rej09b0103-0600 ? before branching to the programming control program (ram area h'ffe 800), the chip terminates transmit and receive operations by the on-chip sci (channel 1) (by clearing the re and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, txd1, goes to the high-level output state (p33ddr = 1, p33dr = 1). the contents of the cpu?s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. ? boot mode can be entered by making the pin settings shown in table 21a-9 and executing a reset-start. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release * 1 . boot mode can also be cleared by a wdt overflow reset. do not change the mode pin input levels in boot mode, and do not drive the fwe pin low * 3 while the boot program is being executed or while flash memory is being programmed or erased. ? if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( as , rd , hwr ) will change according to the change in the microcomputer?s operating mode * 2 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: 1. mode pin and fwe pin input must satisfy the mode progra mming setup time (t mds = 4 states) with respect to the reset release timing. 2. see appendix d, pin states. 3. for precautions on applying and disconnecting fwe, see section 21a.15, flash memory programming and erasing precautions. 21a.8.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 760 of 1484 rej09b0103-0600 to select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. the flash memory itself cannot be read while the swe bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing s hould be run in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. figure 21a-10 shows the procedure for executing the program/erase control program when transferred to on-chip ram. clear fwe fwe = high * branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md2, md1, md0 = 110, 111 reset-start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand notes: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * for precautions on applying and disconnecting fwe, see section 21a.15, flash memory programming and erasing precautions. figure 21a-10 user program mode execution procedure
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 761 of 1484 rej09b0103-0600 21a.9 flash memory programming/erasing a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes for on-chip flash memory are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. also ensure that the dtc is not activated before or after execution of the flash memory write instruction. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 24.1.7, flash memory characteristics. notes: 1. operation is not guaranteed if setting/resetting of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 762 of 1484 rej09b0103-0600 normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe = 1 swe = 0 fwe = 1 fwe = 0 e = 1 e = 0 p = 1 p = 0 software programming enable state * 1 * 2 * 3 * 4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. 1. : normal mode : on-board programming mode 2. do not make a state transition by setting or clearing multiple bits simultaneously. 3. after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu = 0 esu = 1 psu = 1 psu = 0 pv = 1 pv = 0 ev = 0 ev = 1 figure 21a-11 flmcr1 bit settings and state transitions
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 763 of 1484 rej09b0103-0600 21a.9.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21a-12 should be followed. performing progra mming operations according to this flowchart will enable data or programs to be written to flash memory wit hout subjecting the device to voltage stress or sacrificing program data reliability. programming s hould be carried out 128 bytes at a time. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n) are shown in table 24-10 in section 24.1.7, flash memory characteristics. following the elapse of (t sswe ) s or more after the swe bit is set to 1 in flmcr1, 128-byte data is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 and h'80, 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer (wdt) is set to prevent overprogra mming due to program runaway, etc. set a value greater than (t spsu + t sp + t cp + t cpsu ) s as the wdt overflow period. preparation for entering program mode (program setup) is performed next by setting the psu bit in flmcr1. the operating mode is then switched to program mode by setting the p bit in flmcr1 after the elapse of at least (t spsu ) s. the time during which the p bit is set is the flash memory programming time. make a program setting so that the time for one programming operation is within the range of (t sp ) s. the wait time after p bit setting must be changed according to the degree of progress through the programming operati on. for details see ?notes on program/program-verify procedure.?
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 764 of 1484 rej09b0103-0600 21a.9.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p bit in flmcr1, then wait for at least (t cp ) s before clearing the psu bit to exit program mode. after exiting program mode, the watchdog timer setting is also cleared. the operating mode is then switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t spv ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t spvr ) s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21a-12) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (t cpv ) s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (n). leave a wait time of at least (t cswe ) s after clearing swe. notes on program/program-verify procedure 1. in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. 2. when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. 3. verify data is read in word units. 4. the write pulse is applied and a flash memory write executed while the p bit in flmcr1 is set. in the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming c ount (n).
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 765 of 1484 rej09b0103-0600 b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. the following processing is necessary for programmed bits. when programming is completed at an early stage in the program/program-verify procedure: if programming is completed in the 1st to 6th reprogramming processing l oop, additional programming s hould be performed on the relevant bits. additional progra mming s hould only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. when programming is completed at a late stage in the program/program-verify procedure: if programming is completed in the 7th or later reprogramming processing l oop, additional programming is not necessary for the relevant bits. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which progra mming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. the period for which the p bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 24.1.7, flash memory characteristics. item symbol item symbol t sp when reprogramming loop count (n) is 1 to 6 t sp30 wait time after p bit setting when reprogramming loop count (n) is 7 or more t sp200 in case of additional programming processing * t sp10 note: * additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. the program/program-verify flowchart for the h8s/2636 is shown in figure 21a-12. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 766 of 1484 rej09b0103-0600 reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 0 0 1 programming completed: reprogramming processing not to be executed 01 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend: (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend: (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop 7. it is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. however, once 128-byte-unit progra mming is finished, additional programming s hould not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 767 of 1484 rej09b0103-0600 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s sub-routine write pulse end sub set psu bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note: 6 write pulse width write time (tsp) sec 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n = 1 m = 0 no no no no yes yes yes wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming end of programming * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note 6 for pulse width m = 0 ? increment address programming failure yes clear swe bit in flmcr1 wait (t cswe ) s no yes 6 n? no yes 6 n ? wait (t cswe ) s n (n)? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to t he extra addresses. 2. verify data is read in 16-bit (word) units. 3. reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program d ata area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing addit ional data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. 7. the wait times and value of n are shown in section 24.1.7, flash memory characteristics. figure 21a-12 program/program-verify flowchart
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 768 of 1484 rej09b0103-0600 21a.9.3 erase mode when erasing flash memory, the single-block erase flowchart shown in figure 21a-13 should be followed. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of erase operations (n) are shown in table 24-10 in section 24.1.7, flash memory characteristics. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (ebr1, ebr2) at least (t sswe ) s after setting the swe bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (t se ) ms + (t sesu + t ce + t cesu ) s as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu bit in flmcr1. the operating mode is then switched to erase mode by setting the e bit in flmcr1 after the elapse of at least (t sesu ) s. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (t se ) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 769 of 1484 rej09b0103-0600 21a.9.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e bit in flmcr1, then wait for at least (t ce ) s before clearing the esu bit to exit erase mode. after exiting erase mode, the watchdog timer setting is also cleared. the operating mode is then switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t sev ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t sevr ) s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (n). when verification is completed, exit erase-verify mode, and wait for at least (t cev ) s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1, and leave a wait time of at least (t cswe ) s. if erasing multiple blocks, set a single bit in ebr1/ebr2 for the next block to be erased, and repeat the erase/erase-verify sequence as before.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 770 of 1484 rej09b0103-0600 end of erasing start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait (t sswe ) s wait (t sesu ) s n = 1 set ebr1 or ebr2 enable wdt * 3 * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 wait (t se ) ms wait (t ce ) s wait (t cesu ) s wait (t sev ) s set block start address as verify address wait (t sevr ) s * 2 wait (t cev) s start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait (t cev ) s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1s? last address of block? erase failure clear swe bit in flmcr1 n (n)? no no no yes yes yes n n + 1 increment address wait (t cswe ) s wait (t cswe ) s notes: 1. prewriting (setting erase block data to all 0s) is not necessary. 2. verify data is read in 16-bit (word) units. 3. make only a single-bit specification in the erase block registers (ebr1 and ebr2). two or more bits must not be set simulta neously. 4. erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. 5. the wait times and the value of n are shown in section 24.1.7, flash memory characteristics. perform erasing in block units. figure 21a-13 erase/erase-verify flowchart
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 771 of 1484 rej09b0103-0600 21a.10 protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21a.10.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, flmcr2, ebr1, and ebr2 settings are retained in the error-protected state (see table 21a-11). table 21a-11 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2, (except bit fler) ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a reset (including a wdt reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 772 of 1484 rej09b0103-0600 21a.10.2 software protection software protection can be implemented by setting the swe bit in flmcr1, erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1), does not cause a transition to program mode or erase mode (see table 21a-12). table 21a-12 software protection functions item description program erase swe bit protection ? setting bit swe1 in flmcr1 to 0 will place area on-chip flash memory in the program/ erase-protected state (execute the program in the on-chip ram, external memory). yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. ?yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes 21a.10.3 error protection in error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the chip malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 773 of 1484 rej09b0103-0600 fler bit setting conditions are as follows: 1. when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. immediately after exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the cpu releases the bus to the dtc error protection is released only by a reset and in hardware standby mode. figure 21a-14 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence res = 0 or hstby = 0 res = 0 or hstby = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2, (except bit fler) ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend: res = 0 or hstby = 0 error occurrence (software standby) figure 21a-14 flash memory state transitions
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 774 of 1484 rej09b0103-0600 21a.11 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 21a-15 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 21a-15 flowchart for flash memory emulation in ram
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 775 of 1484 rej09b0103-0600 h'000000 h'000400 h'000800 h'000c00 h'001000 h'01ffff flash memory eb4 to eb9 eb0 eb1 eb2 eb3 h'ffe000 h'ffe3ff h'ffefbf on-chip ram this area can be accessed from both the ram area and flash memory area figure 21a-16 example of ram overlap operation example in which flash memory block area eb0 is overlapped 1. set bits rams, ram2 to ram0 in ramer to 1, 0, 0, 0, to overlap part of ram onto the area (eb0) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1), will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 776 of 1484 rej09b0103-0600 21a.12 interrupt handling when programming/erasing flash memory all interrupts, including nmi interrupt is disabled when flash memory is being programmed or erased (when the p or e bit is set in flmcr1), and while the boot program is executing in boot mode * 1 , to give priority to the program or erase operation. there are three reasons for this: 1. interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly * 2 , possibly resulting in mcu runaway. 3. if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operati on. all requests, including nmi interrupt, must therefore be restricted inside and outside the mcu when programming or erasing flash memory. nmi interrupt is also disabled in the error-protection state while the p or e bit remains set in flmcr1. notes: 1. interrupt requests must be disabled inside and outside the mcu until the programming control program has completed programming. 2. the vector may not be read correctly in this case for the following two reasons: ? if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 777 of 1484 rej09b0103-0600 21a.13 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to programmer mode (see table 21a-13) and input a 12 mhz input clock. table 21a-13 shows the pin settings for programmer mode. table 21a-13 programmer mode pin settings pin names settings mode pins: md2, md1, md0 low level input to md2, md1, and md0. mode setting pins: pf0, p16, p14 high level input to pf0, low level input to p16 and p14 fwe pin high level input (in auto-program and auto-erase modes) res pin reset circuit xtal, extal, pllcap, pllvss pins oscillator circuit vcl internal voltage step-down circuit 21a.13.1 socket adapter and memory map in programmer mode in which the prom writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. at this time, a dedicated conversion socket adapter must be attached to a general-purpose prom writer. table 21a-14 shows the types of the socket adapters. for programmer mode on this lsi, one of the socket adapters listed in table 21a-14 should be used. table 21a-14 type of socket adapter product name package type socket adapter type manufacturer hd64f2636uf 128 pin qfp me2636eshf1h minato electronics inc. hd64f2636f (fp-128b) hf2636q128d4001 data i/o japan corporation
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 778 of 1484 rej09b0103-0600 the memory map of on-chip rom is shown in figure 21a-17 h'000000 a ddresses in mcu mode addresses in programmer mode h'01ffff h'00000 h'1ffff on-chip rom space (128 kbytes) figure 21a-17 on-chip rom memory map 21a.13.2 programmer mode operation table 21a-15 shows how the different operating modes are set when using programmer mode, and table 21a-16 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports progra mming of 128 bytes at a time. status po lling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status po lling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 779 of 1484 rej09b0103-0600 table 21a-15 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o7 to i/o0 a18 to a0 read h or l l l h data output ain * 2 output disable h or l l h h hi-z x command write h or l * 3 l h l data input ain * 2 chip disable * 1 h or lhxxhi-zx notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. table 21a-16 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 21a.13.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 780 of 1484 rej09b0103-0600 table 21a-17 ac characteristics in transition to memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce oe ce a18 to a0 oe we i/o7 to i/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 21a-18 timing waveforms for memory read after memory write
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 781 of 1484 rej09b0103-0600 table 21a-18 ac characteristics in transition from memory read mode to another mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 21a-19 timing waveforms in transition from memory read mode to another mode
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 782 of 1484 rej09b0103-0600 table 21a-19 ac characteristics in memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit access time t acc ?20s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5?ns ce a18 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 21a-20 ce and oe enable state read timing waveforms ce a18 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 21a-21 ce and oe clock system read timing waveforms
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 783 of 1484 rej09b0103-0600 21a.13.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when progra mming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 21a-22). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe .
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 784 of 1484 rej09b0103-0600 table 21a-20 ac characteristics in auto-program mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1?ms status polling access time t spa ? 150 ns address setup time t as 0?ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms write setup time t pns 100 ? ns write end setup time t pnh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 21a-22 auto-program mode timing waveforms
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 785 of 1484 rej09b0103-0600 21a.13.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 21a-21 ac characteristics in auto-erase mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1?ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ? ns erase end setup time t enh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 786 of 1484 rej09b0103-0600 ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase end decision signal erase normal end decision signal figure 21a-23 auto-erase mode timing waveforms
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 787 of 1484 rej09b0103-0600 21a.13.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 21a-22 ac characteristics in status read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit read time after command write t std 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ? 30 ns we fall time t f ? 30 ns ce a18 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 21a-24 status read mode timing waveforms
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 788 of 1484 rej09b0103-0600 table 21a-23 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end decision command error program- ming error erase error ?? program- ming or erase count exceeded effective address error initial value00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 ??count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined. 21a.13.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 21a-24 status polling output truth table pin name during internal operation abnormal end ? normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o0 to i/o5 0 0 0 0 21a.13.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 21a-25 stipulated transition times to command wait state item symbol min. max. unit standby release (oscillation stabilization time) t osc1 30 ? ms programmer mode setup time t bmv 10 ? ms vcc hold time t dwn 0?ms
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 789 of 1484 rej09b0103-0600 t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal end decision note:when using other than the automatic write mode and automatic erase mode, drive the fwe input pin low. figure 21a-25 oscillation stabilization time, boot program transfer time, and power-down sequence 21a.13.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming s hould be performed once only on the same address block. additional programming ca nnot be performed on previously programmed address blocks.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 790 of 1484 rej09b0103-0600 21a.14 flash memory and power-down states in addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. there are three flash memory operating states: (1) normal operating mode: the flash memory can be read and written to. (2) power-down mode: part of the power supply circuitry is halted, and the flash memory can be read when the lsi is operating on the subclock * . (3) standby mode: all flash memory circuits are halted, and the flash memory cannot be read or written to. states (2) and (3) are flash memory power-down states. table 21a-26 shows the correspondence between the operating states of the lsi and the flash memory. table 21a-26 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal mode (read/write) subactive mode * subsleep mode * when pdwnd = 0: power-down mode (read-only) when pdwnd = 1: normal mode (read-only) watch mode * software standby mode hardware standby mode standby mode note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask version only. these functions cannot be used with the other versions. 21a.14.1 notes on power-down states 1. when the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. therefore, a power supply circuit stabilization period must be provided when returning to normal operation. when the flash memory returns to its normal operating state from a power-down state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 791 of 1484 rej09b0103-0600 2. in a power-down state, flmcr1, flmcr2, ebr1, ebr2, ramer, and flpwcr cannot be read from or written to. 21a.15 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and programmer mode are summarized below. 1. use the specified voltages and timing for programming and erasing. applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the renesas technology microcomputer device type with 128-kbyte on-chip flash memory. only use the specified socket adapter. failure to observe these points may result in damage to the device. 2. powering on and off (see figures 21a-26 to 21a-28) do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements s hould also be satisfied in the event of a power failure and subsequent recovery. 3. fwe application/disconnection (see figures 21a-26 to 21a-28) fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the v cc voltage has stabilized within its rated voltage range. apply fwe when oscillation has stabilized (after the elapse of the oscillation settling time). in boot mode, apply and disconnect fwe during a reset. in user program mode, fwe can be switched between high and low level regardless of a reset state. fwe input can also be switched during execution of a program in flash memory. do not apply fwe if program runaway has occurred.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 792 of 1484 rej09b0103-0600 disconnect fwe only when the swe, esu, psu, ev, pv, p, and e bits in flmcr1 are cleared. make sure that the swe, esu, psu, ev, pv, p, and e bits are not set by mistake when applying or disconnecting fwe. 4. do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. use the recommended algorithm when programming and erasing flash memory. the recommended algorithm enables programming and erasing to be carried out wit hout subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 6. do not set or clear the swe bit during execution of a program in flash memory. do not set or clear the swe bit during execution of a program in flash memory. wait for at least 100 s after clearing the swe bit before executing a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but when swe = 1, flash memory can only be read in program-verify or erase-verify mode. access flash memory only for verify operations (verification during programming/erasing). do not clear the swe bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a high level is being i nput to the fwe pin, the swe bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. 7. do not use interrupts while flash memory is being programmed or erased. all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations. 8. do not perform additional programming. erase the memory before reprogramming. in on-board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, also, perform only one programming operation on a 128-byte programming unit block. further programming must only be executed after this programming unit block has been erased.
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 793 of 1484 rej09b0103-0600 9. before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. 10. do not touch the socket adapter or chip during programming. touching either of these can cause contact faults and write errors. period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds * 3 t mds * 3 md2 to md0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: 100 s min. 0 s notes: 1. except when switching modes, the level of the mode pins (md2?md0) must be fixed until power- off by pulling the pins up or down. 2. see section 24.1.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 21a-26 power-on/off timing (boot mode)
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 794 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s md2 to md0 * 1 res swe bit swe set swe cleared program- ming/ erasing possible wait time: x wait time: 100 s t mds * 3 notes: 1. except when switching modes, the level of the mode pins (md2 ? md0) must be fixed until power- off by pulling the pins up or down. 2. see section 24.1.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 21a-27 power-on/off timing (user program mode)
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 795 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds t mds * 2 t mds t resw md2 to md0 res swe bit mode change * 1 user mode boot mode user program mode swe set swe cleared programming/ erasing possible wait time: x wait time: 100 s programming/ erasing possible wait time: x wait time: 100 s programming/ erasing possible wait time: x programming/ erasing possible wait time: x wait time: 100 s wait time: 100 s mode change * 1 user mode user program mode notes: 1. when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. 2. when making a transition from boot mode to another mode, a mode programming setup time, t mds (min.), of 200 ns is necessary with respect to the res clearance timing. 3. see section 24.1.7, flash memory characteristics. figure 21a-28 mode transition timing (example: boot mode user mode ? ? ? ? user program mode)
section 21a rom (h8s/2636 group) rev. 6.00 feb 22, 2005 page 796 of 1484 rej09b0103-0600 21a.16 note on switching from f-ztat version to mask rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 21a-27 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 21a-27 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 21a-27 have no effect. table 21a-27 registers present in f-ztat version but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 797 of 1484 rej09b0103-0600 section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) 21b.1 overview the h8s/2638 and h8s/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes or 384 kbytes of on-chip mask rom. the h8s/2630 has 384 kbytes of on-chip flash memory, or 384 kbytes of on-chip mask rom. the rom is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the on-chip rom is enabled and disabled by setting the mode pins (md2 to md0). the flash memory version can be erased and programmed on-board, as well as with a special- purpose prom programmer. 21b.1.1 block diagram figure 21b-1 shows a block diagram of 256-kbyte and 384-kbyte rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'000001 h'000003 h'03fffe (h'05fffe) * h'03ffff (h'05ffff) * note: * rom addresses for the h8s/2638 and h8s/2639 extend from h'000000 to h'03ffff (256 kbytes), and for the h8s/2630 from h'000000 to h'05ffff (384 kbytes). figure 21b-1 block diagram of rom 256 kbytes (384 kbytes) *
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 798 of 1484 rej09b0103-0600 21b.1.2 register configuration the h8s/2638 and h8s/2639 operating mode is controlled by the mode pins and the mdcr register. the register configuration is shown in table 21b-1. table 21b-1 register configuration register name abbreviation r/w initial value address * mode control register mdcr r/w undefined h'fde7 note: * lower 16 bits of the address. 21b.2 register descriptions 21b.2.1 mode control register (mdcr) bit:76543210 ?????mds2mds1mds0 initial value:10000? * ? * ? * r/w:r/w???? r r r note: * determined by pins md2 to md0. mdcr is an 8-bit register used to monitor the current h8s/2638 group, h8s/2639 group, and h8s/2630 group operating mode. bit 7?reserved: only 1 should be written to these bits. bits 6 to 3?reserved: these bits are always read as 0 and cannot be modified. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be modified. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. 21b.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 799 of 1484 rej09b0103-0600 the on-chip rom is enabled and disabled by setting the mode pins (md2, md1, and md0). these settings are shown in table 21b-2. table 21b-2 operating modes and rom (f-ztat version) mode pins operating mode fwe md2 md1 md0 on-chip rom mode 0 ? 0 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (256 kbytes/ 384 kbytes) * 3 mode 7 advanced single-chip mode 1 enabled (256 kbytes/ 384 kbytes) * 3 mode 8 ? 1 0 0 0 ? mode 9 1 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (256 kbytes/ 384 kbytes) * 3 mode 11 boot mode (advanced single-chip mode) * 2 1 enabled (256 kbytes/ 384 kbytes) * 3 mode 12 ? 1 0 0 ? mode 13 1 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (256 kbytes/ 384 kbytes) * 3 mode 15 user program mode (advanced single- chip mode) * 2 1 enabled (256 kbytes/ 384 kbytes) * 3 notes: 1. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip rom enabled. 2. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 800 of 1484 rej09b0103-0600 3. the h8s/2638 and h8s/2639 have 256 kbytes of on-chip rom. the h8s/2630 has 384 kbytes of on-chip rom. table 21b-3 operating modes and rom (mask rom version) mode pins operating mode md2 md1 md0 on-chip rom mode 0 ? 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 100disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 10 enabled (256 kbytes/ 384 kbytes) * mode 7 advanced single-chip mode 1 enabled (256 kbytes/ 384 kbytes) * note: * the h8s/2638 and h8s/2639 have 256 kbytes of on-chip rom. the h8s/2630 has 384 kbytes of on-chip rom.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 801 of 1484 rej09b0103-0600 21b.4 flash memory overview 21b.4.1 features the h8s/2638 and h8s/2639 have 256 kbytes of on-chip flash memory, or 256 kbytes of on-chip mask rom. the h8s/2630 has 384 kbytes of on-chip flash memory, or 384 kbytes of on-chip mask rom. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. to erase the entire flash memory, each block must be erased in turn. block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte progra mming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the lsi?s bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 802 of 1484 rej09b0103-0600 ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. 21b.4.2 block diagram module bus bus interface/controller flash memory (256 kbytes/ 384 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flpwcr flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register flash memory power control register legend: flmcr1: flmcr2: ebr1: ebr2: ramer: flpwcr: figure 21b-2 block diagram of flash memory
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 803 of 1484 rej09b0103-0600 21b.4.3 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21b-3. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode res = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md0 = 0, md1 = 0, md2 = 0, p14 = 0, p16 = 0, pf0 = 1 res = 0 md2 = 0, md1 = 1, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 21b-3 flash memory state transitions
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 804 of 1484 rej09b0103-0600 21b.4.4 on-board programming modes boot mode flash memory chip ram host programming control program sci application program (old version) new application program flash memory chip ram host sci application program (old version) boot program area new application program flash memory chip ram host sci flash memory preprogramming erase boot program new application program flash memory chip program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 805 of 1484 rej09b0103-0600 user program mode flash memory chip ram host programming/ erase control program sci boot program new application program flash memory chip ram host sci new application program flash memory chip ram host sci flash memory erase boot program new application program flash memory chip program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 806 of 1484 rej09b0103-0600 21b.4.5 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 21b-4 reading overlap ram data in user mode or user program mode when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 807 of 1484 rej09b0103-0600 application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 21b-5 writing overlap ram data in user program mode 21b.4.6 differences between boot mode and user program mode table 21b-4 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify emulation note: * to be provided by the user, in accordance with the recommended algorithm.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 808 of 1484 rej09b0103-0600 21b.4.7 block configuration the h8s/2638 and h8s/2639 have 256 kbytes of flash memory, which is divided into three 64- kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. the h8s/2630 has 384 kbytes of flash memory, which is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. address h00000 address h3ffff address h5ffff 32 kbytes 64 kbytes 64 kbytes 64 kbytes 256 kbytes 4 kbytes 8 h8s/2638, h8s/2639 64 kbytes 32 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 384 kbytes 4 kbytes 8 h8s/2630 figure 21b-6 flash memory block configuration
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 809 of 1484 rej09b0103-0600 21b.5 pin configuration the flash memory is controlled by means of the pins shown in table 21b-5. table 21b-5 pin configuration pin name abbreviation i/o function reset res input reset flash write enable fwe input flash memory program/erase protection by hardware mode 2 md2 input sets mcu operating mode mode 1 md1 input sets mcu operating mode mode 0 md0 input sets mcu operating mode port f0 pf0 input sets mcu operating mode in programmer mode port 16 p16 input sets mcu operating mode in programmer mode port 14 p14 input sets mcu operating mode in programmer mode transmit data txd1 output serial transmit data output receive data rxd1 input serial receive data input
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 810 of 1484 rej09b0103-0600 21b.6 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 21b-6. table 21b-6 register configuration register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 4 r/w h'00 * 2 h'ffa8 flash memory control register 2 flmcr2 * 4 r h'00 h'ffa9 erase block register 1 ebr1 * 4 r/w h'00 * 3 h'ffaa erase block register 2 ebr2 * 4 r/w h'00 * 3 h'ffab ram emulation register ramer * 4 r/w h'00 h'fedb flash memory power control register flpwcr * 4 r/w h'00 * 3 h'ffac notes: 1. lower 16 bits of the address. 2. when a high level is input to the fwe pin, the initial value is h'80. 3. when a low level is input to the fwe pin, or if a high level is input and the swe1 bit in flmcr1 is not set, these registers are initialized to h'00. 4. flmcr1, flmcr2, ebr1, and ebr2, ramer, and flpwcr are 8-bit registers. use byte access on these registers.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 811 of 1484 rej09b0103-0600 21b.7 register descriptions 21b.7.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the pv or ev bit. program mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode for on- chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read w ill return h'00, and writes are invalid. writes are enabled only in the following cases: writes to bit swe of flmcr1 enabled when fwe = 1, to bits esu, psu, ev, and pv when fwe = 1 and swe = 1, to bit e when fwe = 1, swe = 1 and esu = 1, and to bit p when fwe = 1, swe = 1, and psu = 1. bit:76543210 fwe swe esu psu ev pv e p initial value: ? * 0000000 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. bit 7?flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 812 of 1484 rej09b0103-0600 bit 6?software write enable bit (swe): this bit selects write and erase valid/invalid of the flash memory. set it when setting bits 5 to 0, bits 7 to 0 of ebr1, and bits 5 to 0 * of ebr2. bit 6 swe description 0 writes disabled (initial value ) 1 writes enabled [setting condition] ? when fwe = 1 note: * bits 3 to 0 of ebr2 for the h8s/2638 and h8s/2639. bit 5?erase setup bit (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit in flmcr1 to 1. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5 esu description 0 erase setup cleared (initial value ) 1 erase setup [setting condition] ? when fwe = 1 and swe = 1 bit 4?program setup bit (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit in flmcr1 to 1. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4 psu description 0 program setup cleared (initial value ) 1 program setup [setting condition] ? when fwe = 1 and swe = 1
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 813 of 1484 rej09b0103-0600 bit 3?erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3 ev description 0 erase-verify mode cleared (initial value ) 1 transition to erase-verify mode [setting condition] ? when fwe = 1 and swe = 1 bit 2?program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2 pv description 0 program-verify mode cleared (initial value ) 1 transition to program-verify mode [setting condition] ? when fwe = 1 and swe = 1 bit 1?erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1 e description 0 erase mode cleared (initial value ) 1 transition to erase mode [setting condition] ? when fwe = 1, swe = 1, and esu = 1 bit 0?program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 814 of 1484 rej09b0103-0600 bit 0 p description 0 program mode cleared (initial value ) 1 transition to program mode [setting condition] ? when fwe = 1, swe = 1, and psu = 1 21b.7.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00. bit:76543210 fler??????? initial value:00000000 r/w:r ??????? note: flmcr2 is a read-only register, and should not be written to. bit 7?flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally (initial value ) flash memory program/erase protection (error protection) is disabled [clearing condition] ? reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] ? see section 21b.10.3, error protection bits 6 to 0?reserved: these bits always read 0.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 815 of 1484 rej09b0103-0600 21b.7.3 erase block register 1 (ebr1) ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid. the flash memory erase block configuration is shown in table 21b-7. bit:76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 21b.7.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin. bit 0 w ill be initialized to 0 if bit swe of flmcr1 is not set, even though a high level is input to pin fwe. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. on the h8s/2638 and h8s/2639 bits 7 to 4 are reserved, and on the h8s/2630 bits 7 and 6 are reserved. only 0 may be written to these reserved bits. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory erase block configuration is shown in table 21b-7. bit:76543210 ? ? eb13 * eb12 * eb11 eb10 eb9 eb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * valid on the h8s/2630. on the h8s/2638 and h8s/2639 these bits are reserved and only 0 may be written to them.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 816 of 1484 rej09b0103-0600 table 21b-7 flash memory erase blocks block (size) addresses eb0 (4 kbytes) h'000000 to h'000fff eb1 (4 kbytes) h'001000 to h'001fff eb2 (4 kbytes) h'002000 to h'002fff eb3 (4 kbytes) h'003000 to h'003fff eb4 (4 kbytes) h'004000 to h'004fff eb5 (4 kbytes) h'005000 to h'005fff eb6 (4 kbytes) h'006000 to h'006fff eb7 (4 kbytes) h'007000 to h'007fff eb8 (32 kbytes) h'008000 to h'00ffff eb9 (64 kbytes) h'010000 to h'01ffff eb10 (64 kbytes) h'020000 to h'02ffff eb11 (64 kbytes) h'030000 to h'03ffff eb12 (64 kbytes) * h'040000 to h'04ffff eb13 (64 kbytes)) * h'050000 to h'05ffff note: * this function is not available in the h8s/2638 and h8s/2639. 21b.7.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 21b-8. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit:76543210 ????ramsram2ram1ram0 initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 817 of 1484 rej09b0103-0600 bits 7 and 6?reserved: these bits always read 0. bits 5 and 4?reserved: only 0 may be written to these bits. bit 3?ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 3 rams description 0 emulation not selected (initial value ) program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2 to 0?flash memory area selection: these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 21b-8.) table 21b-8 flash memory area divisions addresses block name rams ram1 ram1 ram0 h'ffd000 to h'ffdfff ram area 4 kbytes 0 *** h'000000 to h'000fff eb0 (4 kbytes) 1 0 0 0 h'001000 to h'001fff eb1 (4 kbytes) 1 0 0 1 h'002000 to h'002fff eb2 (4 kbytes) 1 0 1 0 h'003000 to h'003fff eb3 (4 kbytes) 1 0 1 1 h'004000 to h'004fff eb4 (4 kbytes) 1 1 0 0 h'005000 to h'005fff eb5 (4 kbytes) 1 1 0 1 h'006000 to h'006fff eb6 (4 kbytes) 1 1 1 0 h'007000 to h'007fff eb7 (4 kbytes) 1 1 1 1 * : don't care
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 818 of 1484 rej09b0103-0600 21b.7.6 flash memory power control register (flpwcr) bit:76543210 pdwnd??????? initial value:00000000 r/w:r/wrrrrrrr flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode * . note: * subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the u-mask and w-mask versions. bit 7?power-down disable (pdwnd): the subactive mode is not available in versions other than the u-mask and w-mask versions. only 0 should be written to this bit in the case of versions other than the u-mask and w-mask versions. see section 21.b.14, flash memory and power-down states, for more information. bit 7 pdwnd description 0 transition to flash memory power-down mode enabled (initial value) 1 transition to flash memory power-down mode disabled bits 6 to 0?reserved: these bits always read 0.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 819 of 1484 rej09b0103-0600 21b.8 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 21b-9. for a diagram of the transitions to the various flash memory modes, see figure 21b-3. table 21b-9 setting on-board programming modes mode fwe md2 md1 md0 boot mode expanded mode 1 0 1 0 single-chip mode 0 1 1 user program mode expanded mode 1 1 1 0 single-chip mode 1 1 1
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 820 of 1484 rej09b0103-0600 21b.8.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset-start is executed after the h8s/2638?, h8s/2639?, and h8s/2630? pins have been set to boot mode, the boot program built into the h8s/2638, h8s/2639, and h8s/2630 are started and the programming control program prepared in the host is serially transmitted to the h8s/2 638, h8s/2639, and h8s/2630 via the sci. in the h8s/2638, h8s/2639, and h8s/2630, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 21b-7, and the boot mode execution procedure in figure 21b-8. rxd1 txd1 sci1 lsi flash memory write data reception verify data transmission host on-chip ram figure 21b-7 system configuration in boot mode
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 821 of 1484 rej09b0103-0600 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate chip measures low period of h'00 data transmitted by host chip calculates bit rate and sets value in bit rate register after bit rate adjustment, chip transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, lsi transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte chip transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units chip transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, chip transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 21b-8 boot mode execution procedure
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 822 of 1484 rej09b0103-0600 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h00 data) high period (1 or more bits) when boot mode is initiated, the lsi measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/r eceive format should be set as follows: 8-bit data, 1 stop bit, no parity. the lsi calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the lsi. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host?s transmission bit rate and the lsi?s system clock frequency, there will be a discrepancy between the bit rates of the host and the lsi. set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the sci properly. table 21b-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the lsi bit rate is possible. the boot program should be executed within this system clock range. table 21b-10 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency for which automatic adjustment of lsi bit rate is possible 4,800 bps 4 to 20 mhz 9,600 bps 8 to 20 mhz 19,200 bps 16 to 20 mhz note: the system clock frequency used in boot mode is generated by an external crystal oscillator element. pll frequency multiplication is not used.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 823 of 1484 rej09b0103-0600 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 21b-9. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffc000 h'ffdfff h'ffe000 h'ffefbf boot program area (4 kbytes) programming control program area (8 kbytes) note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. figure 21b-9 ram areas in boot mode notes on use of boot mode: ? when the chip comes out of reset in boot mode, it measures the low-level period of the input at the sci?s rxd1 pin. the reset should end with rxd1 high. after the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the rxd1 pin. ? in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. ? interrupts cannot be used while the flash memory is being programmed or erased. ? the rxd1 and txd1 pins should be pulled up on the board. ? before branching to the programming control program (ram area h'ffc 000), the chip terminates transmit and receive operations by the on-chip sci (channel 1) (by clearing the re
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 824 of 1484 rej09b0103-0600 and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, txd1, goes to the high-level output state (p33ddr = 1, p33dr = 1). the contents of the cpu?s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. ? boot mode can be entered by making the pin settings shown in table 21b-9 and executing a reset-start. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release * 1 . boot mode can also be cleared by a wdt overflow reset. do not change the mode pin input levels in boot mode, and do not drive the fwe pin low while the boot program is being executed or while flash memory is being programmed or erased * 2 . ? if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( as , rd , hwr ) will change according to the change in the microcomputer?s operating mode * 3 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: 1. mode pin and fwe pin input must satisfy the mode progra mming setup time (t mds = 4 states) with respect to the reset release timing. 2. for precautions on applying and disconnecting fwe, see section 21b.15, flash memory programming and erasing precautions. 3. see appendix d, pin states. 21b.8.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 825 of 1484 rej09b0103-0600 to select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. the flash memory itself cannot be read while the swe bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing s hould be run in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. figure 21b-10 shows the procedure for executing the program/erase control program when transferred to on-chip ram. clear fwe * fwe = high * branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md2, md1, md0 = 110, 111 reset-start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand notes: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * for further information on fwe application and disconnection, see section 21b.15, flash memory programming and erasing precautions. figure 21b-10 user program mode execution procedure
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 826 of 1484 rej09b0103-0600 21b.9 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1 for on-chip flash memory. the flash memory cannot be read while it is being written or erased. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing s hould be located and executed in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. also ensure that the dtc is not activated before or after execution of the flash memory write instruction. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 24.2.7 and 24.3.7, flash memory characteristics. notes: 1. operation is not guaranteed if bits swe, esu, psu, ev, pv, e, and p of flmcr1 are set/reset by a program in flash memory in the corresponding address areas. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming s hould be performed in the erased state. do not perform additional programming on previously programmed addresses.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 827 of 1484 rej09b0103-0600 normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe = 1 swe = 0 fwe = 1 fwe = 0 e = 1 e = 0 p = 1 p = 0 software programming enable state * 1 * 2 * 3 * 4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. 1. : normal mode : on-board programming mode 2. do not make a state transition by setting or clearing multiple bits simultaneously. 3. after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu = 0 esu = 1 psu = 1 psu = 0 pv = 1 pv = 0 ev = 0 ev = 1 figure 21b-11 flmcr1 bit settings and state transitions
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 828 of 1484 rej09b0103-0600 21b.9.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21b-12 should be followed. performing progra mming operations according to this flowchart will enable data or programs to be written to flash memory wit hout subjecting the device to voltage stress or sacrificing program data reliability. programming s hould be carried out 128 bytes at a time. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n) are shown in table 24-22 in section 24.2.7, and in table 24-34 in section 24.3.7, and in table 24-46 in section 24.4.7, flash memory characteristics. following the elapse of (t sswe ) s or more after the swe bit is set to 1 in flmcr1, 128-byte data is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 and h'80, 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer (wdt) is set to prevent overprogra mming due to program runaway, etc. set a value greater than (t spsu + t sp + t cp + t cpsu ) s as the wdt overflow period. preparation for entering program mode (program setup) is performed next by setting the psu bit in flmcr1. the operating mode is then switched to program mode by setting the p bit in flmcr1 after the elapse of at least (t spsu ) s. the time during which the p bit is set is the flash memory programming time. make a program setting so that the time for one programming operation is within the range of (t sp ) s. the wait time after p bit setting must be changed according to the degree of progress through the programming operati on. for details see ?notes on program/program-verify procedure.?
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 829 of 1484 rej09b0103-0600 21b.9.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p bit in flmcr1, then wait for at least (t cp ) s before clearing the psu bit to exit program mode. after exiting program mode, the watchdog timer setting is also cleared. the operating mode is then switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t spv ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t spvr ) s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21b-12) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (t cpv ) s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (n). leave a wait time of at least (t cswe ) s after clearing swe. notes on program/program-verify procedure 1. in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. 2. when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. 3. verify data is read in word units. 4. the write pulse is applied and a flash memory write executed while the p bit in flmcr1 is set. in the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming c ount (n).
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 830 of 1484 rej09b0103-0600 b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. the following processing is necessary for programmed bits. when programming is completed at an early stage in the program/program-verify procedure: if programming is completed in the 1st to 6th reprogramming processing l oop, additional programming s hould be performed on the relevant bits. additional progra mming s hould only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. when programming is completed at a late stage in the program/program-verify procedure: if programming is completed in the 7th or later reprogramming processing l oop, additional programming is not necessary for the relevant bits. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which progra mming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. the period for which the p bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. item symbol item symbol t sp when reprogramming loop count (n) is 1 to 6 t sp30 wait time after p bit setting when reprogramming loop count (n) is 7 or more t sp200 in case of additional programming processing * t sp10 note: * additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. the program/program-verify flowchart for the h8s/2638, h8s/2639, and h8s/2630 are shown in figure 21b-12. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 831 of 1484 rej09b0103-0600 reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 0 0 1 programming completed: reprogramming processing not to be executed 01 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend: (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend: (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop 7. it is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. however, once 128-byte-unit progra mming is finished, additional programming s hould not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 832 of 1484 rej09b0103-0600 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s sub-routine write pulse end sub set psu bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note: 6 write pulse width write time (tsp) sec 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n = 1 m = 0 no no no no yes yes yes wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming end of programming * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note 6 for pulse width m = 0 ? increment address programming failure yes clear swe bit in flmcr1 wait (t cswe ) s no yes 6 n? no yes 6 n ? wait (t cswe ) s n (n)? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to t he extra addresses. 2. verify data is read in 16-bit (word) units. 3. reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program d ata area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing addit ional data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. 7. the wait times and value of n are shown in section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. figure 21b-12 program/program-verify flowchart
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 833 of 1484 rej09b0103-0600 21b.9.3 erase mode when erasing flash memory, the single-block erase flowchart shown in figure 21b-13 should be followed. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of erase operations (n) are shown in table 24-10 in section 24.2.7 and 24.3.7, flash memory characteristics. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (ebr1, ebr2) at least (t sswe ) s after setting the swe bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (t se ) ms + (t sesu + t ce + t cesu ) s as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu bit in flmcr1. the operating mode is then switched to erase mode by setting the e bit in flmcr1 after the elapse of at least (t sesu ) s. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (t se ) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 21b.9.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e bit in flmcr1, then wait for at least (t ce ) s before clearing the esu bit to exit erase mode. after exiting erase mode, the watchdog timer setting is also cleared. the operating mode is then switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t sev ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t sevr ) s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (n). when verification is completed, exit erase-verify mode, and wait for at least (t cev ) s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1, and leave a wait time of at least (t cswe ) s.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 834 of 1484 rej09b0103-0600 if erasing multiple blocks, set a single bit in ebr1/ebr2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. end of erasing start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait (t sswe ) s wait (t sesu ) s n = 1 set ebr1 or ebr2 enable wdt * 3 * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 wait (t se ) ms wait (t ce ) s wait (t cesu ) s wait (t sev ) s set block start address as verify address wait (t sevr ) s * 2 wait (t cev) s start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait (t cev ) s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1s? last address of block? erase failure clear swe bit in flmcr1 n (n)? no no no yes yes yes n n + 1 increment address wait (t cswe ) s wait (t cswe ) s notes: 1. prewriting (setting erase block data to all 0s) is not necessary. 2. verify data is read in 16-bit (word) units. 3. make only a single-bit specification in the erase block registers (ebr1 and ebr2). two or more bits must not be set simulta neously. 4. erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. 5. the wait times and the value of n are shown in section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. perform erasing in block units. figure 21b-13 erase/erase-verify flowchart
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 835 of 1484 rej09b0103-0600 21b.10 protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21b.10.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, flmcr2, ebr1, and ebr2 settings are retained in the error-protected state (see table 21b-11). table 21b-11 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2, (except bit fler) ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a reset (including a wdt reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 836 of 1484 rej09b0103-0600 21b.10.2 software protection software protection can be implemented by setting the swe bit in flmcr1, erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1), does not cause a transition to program mode or erase mode (see table 21b-12). table 21b-12 software protection functions item description program erase swe bit protection ? setting bit swe in flmcr1 to 0 will place area on-chip flash memory in the program/ erase-protected state (execute the program in the on-chip ram, external memory). yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. ?yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 837 of 1484 rej09b0103-0600 21b.10.3 error protection in error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the chip malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. immediately after exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the cpu releases the bus to the dtc error protection is released only by a reset and in hardware standby mode.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 838 of 1484 rej09b0103-0600 figure 21b-14 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence res = 0 or hstby = 0 res = 0 or hstby = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2, (except bit fler) ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend: res = 0 or hstby = 0 error occurrence (software standby) figure 21b-14 flash memory state transitions
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 839 of 1484 rej09b0103-0600 21b.11 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 21b-15 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 21b-15 flowchart for flash memory emulation in ram
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 840 of 1484 rej09b0103-0600 h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'3ffff flash memory eb8 to eb11 h8s/2638, h8s/2639 eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ffd000 h'ffdfff h'ffefbf on-chip ram this area can be accessed from both the ram area and flash memory area h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'5ffff flash memory eb8 to eb13 h8s/2630 eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ffd000 h'ffdfff h'ffefbf on-chip ram this area can be accessed from both the ram area and flash memory area figure 21b-16 example of ram overlap operation example in which flash memory block area eb0 is overlapped 1. set bits rams, ram2 to ram0 in ramer to 1, 0, 0, 0, to overlap part of ram onto the area (eb0) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1), will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 841 of 1484 rej09b0103-0600 21b.12 interrupt handling when programming/erasing flash memory all interrupts, including nmi interrupt is disabled when flash memory is being programmed or erased (when the p or e bit is set in flmcr1), and while the boot program is executing in boot mode * 1 , to give priority to the program or erase operation. there are three reasons for this: 1. interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly * 2 , possibly resulting in mcu runaway. 3. if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operati on. all requests, including nmi interrupt, must therefore be restricted inside and outside the mcu when programming or erasing flash memory. nmi interrupt is also disabled in the error-protection state while the p or e bit remains set in flmcr1. notes: 1. interrupt requests must be disabled inside and outside the mcu until the programming control program has completed programming. 2. the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 21b.13 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to programmer mode (see table 21b-13) and input a 12 mhz input clock.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 842 of 1484 rej09b0103-0600 table 21b-13 shows the pin settings for programmer mode. table 21b-13 programmer mode pin settings pin names settings mode pins: md2, md1, md0 low level input to md2, md1, and md0. mode setting pins: pf0, p16, p14 high level input to pf0, low level input to p16 and p14 fwe pin high level input (in auto-program and auto-erase modes) res pin reset circuit xtal, extal, pllcap, pllvss pins oscillator circuit vcl internal voltage step-down circuit 21b.13.1 socket adapter and memory map in programmer mode in which the prom writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. at this time, a dedicated conversion socket adapter must be attached to a general-purpose prom writer. table 21b-14 shows the types of the socket adapters. for programmer mode on this lsi, one of the socket adapters listed in table 21b-14 should be used. table 21b-14 type of socket adapter product name package type socket adapter type manufacturer me2636eshf1h minato electronics inc. hd64f2638f hd64f2638uf hd64f2638wf hd64f2639uf hd64f2639wf hd64f2630f * hd64f2630uf * hd64f2630wf * 128 pin qfp (fp-128b) hf2636q128d4001 data i/o japan corporation note: * under development
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 843 of 1484 rej09b0103-0600 h'000000 addresses in mcu mode addresses in programmer mode h'03ffff h'00000 h'3ffff on-chip rom space 256 kbytes (h8s/2638, h8s/2639) h'000000 addresses in mcu mode addresses in programmer mode h'05ffff h'00000 h'5ffff on-chip rom space 384 kbytes (h8s/2630) figure 21b-17 on-chip rom memory map 21b.13.2 programmer mode operation table 21b-15 shows how the different operating modes are set when using programmer mode, and table 21b-16 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports progra mming of 128 bytes at a time. status po lling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status po lling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 844 of 1484 rej09b0103-0600 table 21b-15 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o7 to i/o0 a18 to a0 read h or l l l h data output ain * 2 output disable h or l l h h hi-z x command write h or l * 3 l h l data input ain * 2 chip disable * 1 h or lhxxhi-zx notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. table 21b-16 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 21b.13.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 845 of 1484 rej09b0103-0600 table 21b-17 ac characteristics in transition to memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce oe ce a18 to a0 oe we i/o7 to i/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 21b-18 timing waveforms for memory read after memory write
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 846 of 1484 rej09b0103-0600 table 21b-18 ac characteristics in transition from memory read mode to another mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 21b-19 timing waveforms in transition from memory read mode to another mode
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 847 of 1484 rej09b0103-0600 table 21b-19 ac characteristics in memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit access time t acc ?20s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5?ns ce a18 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 21b-20 ce and oe enable state read timing waveforms ce a18 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 21b-21 ce and oe clock system read timing waveforms
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 848 of 1484 rej09b0103-0600 21b.13.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when progra mming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 21b-22). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe .
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 849 of 1484 rej09b0103-0600 table 21b-20 ac characteristics in auto-program mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1?ms status polling access time t spa ? 150 ns address setup time t as 0?ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms write setup time t pns 100 ? ns write end setup time t pnh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 21b-22 auto-program mode timing waveforms
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 850 of 1484 rej09b0103-0600 21b.13.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 21b-21 ac characteristics in auto-erase mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1?ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ? ns erase end setup time t enh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 851 of 1484 rej09b0103-0600 ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase end decision signal erase normal end decision signal figure 21b-23 auto-erase mode timing waveforms
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 852 of 1484 rej09b0103-0600 21b.13.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 21b-22 ac characteristics in status read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit read time after command write t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 21b-24 status read mode timing waveforms
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 853 of 1484 rej09b0103-0600 table 21b-23 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end decision command error program- ming error erase error ?? program- ming or erase count exceeded effective address error initial value00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 ??count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined. 21b.13.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 21b-24 status polling output truth table pin name during internal operation abnormal end ? normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o0 to i/o5 0 0 0 0 21b.13.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 21b-25 stipulated transition times to command wait state item symbol min. max. unit standby release (oscillation stabilization time) t osc1 30 ? ms programmer mode setup time t bmv 10 ? ms v cc hold time t dwn 0?ms
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 854 of 1484 rej09b0103-0600 t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal end decision note: when using other than the automatic write mode and automatic erase mode, drive the fwe input pin low. figure 21b-25 oscillation stabilization time, boot program transfer time, and power-down sequence 21b.13.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming s hould be performed once only on the same address block. additional programming ca nnot be performed on previously programmed address blocks.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 855 of 1484 rej09b0103-0600 21b.14 flash memory and power-down states in addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. there are three flash memory operating states: (1) normal operating mode: the flash memory can be read and written to. (2) power-down mode: part of the power supply circuitry is halted, and the flash memory can be read when the lsi is operating on the subclock. (3) standby mode: all flash memory circuits are halted, and the flash memory cannot be read or written to. states (2) and (3) are flash memory power-down states. table 21b-26 shows the correspondence between the operating states of the lsi and the flash memory. table 21b-26 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal mode (read/write) subactive mode * subsleep mode * when pdwnd = 0: power-down mode (read-only) when pdwnd = 1: normal mode (read-only) watch mode * software standby mode hardware standby mode standby mode note: * subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the u-mask and w-mask versions.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 856 of 1484 rej09b0103-0600 21b.14.1 notes on power-down states 1. when the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. therefore, a power supply circuit stabilization period must be provided when returning to normal operation. when the flash memory returns to its normal operating state from a power-down state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 2. in a power-down state, flmcr1, flmcr2, ebr1, ebr2, ramer, and flpwcr cannot be read from or written to. 21b.15 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and programmer mode are summarized below. use the specified voltages and timing for programming and erasing: applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the renesas microcomputer device type * with 256-kbyte and 512-kbyte on-chip flash memory. only use the specified socket adapter. failure to observe these points may result in damage to the device. note: * the h8s/2638 and h8s/2639 are renesas technology microcomputer devices with 256 kbytes of on-chip flash memory. the h8s/2630 is a renesas microcomputer device with 512 kbytes of on-chip flash memory (the h8s/2630 has 384 kbytes of prom. the area from h'60000 to h'7ffff should be programmed as h'ff). powering on and off (see figures 21b-26 to 21b-28): do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements s hould also be satisfied in the event of a power failure and subsequent recovery.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 857 of 1484 rej09b0103-0600 fwe application/disconnection (see figures 21b-26 to 21b-28): fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the v cc voltage has stabilized within its rated voltage range. apply fwe when oscillation has stabilized (after the elapse of the oscillation stabilization time). ? in boot mode, apply and disconnect fwe during a reset. ? in user program mode, fwe can be switched between high and low level regardless of the reset state. fwe input can also be switched during execution of a program in flash memory. ? do not apply fwe if program runaway has occurred. ? disconnect fwe only when the swe, esu, psu, ev, pv, p, and e bits in flmcr1 are cleared. make sure that the swe, esu, psu, ev, pv, p, and e bits are not set by mistake when applying or disconnecting fwe. do not apply a constant high level to the fwe pin: apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogra mming or overerasing due to program runaway, etc. use the recommended algorithm when programming and erasing flash memory: the recommended algorithm enables programming and erasing to be carried out wit hout subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. do not set or clear the swe bit during execution of a program in flash memory: wait for at least 100 s after clearing the swe bit before executing a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but when swe = 1, flash memory can only be read in program-verify or erase-verify mode. access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a high level is being i nput to the fwe pin, the swe bit must be cleared before executing a program or reading data in flash memory.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 858 of 1484 rej09b0103-0600 however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. do not use interrupts while flash memory is being programmed or erased: all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming: in on- board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perform only one progra mming operation on a 128-byte programming unit block. programming s hould be carried out with the entire progra mming unit block erased. before programming, check that the chip is correctly mounted in the prom programmer: overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. do not touch the socket adapter or chip during programming: touching either of these can cause contact faults and write errors.
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 859 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds * 3 t mds * 3 md2 to md0 * 1 res swe bit swe set swe cleared programming/ erasing possible wait time: x wait time: 100 s notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns min. 0 s figure 21b-26 power-on/off timing (boot mode)
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 860 of 1484 rej09b0103-0600 swe set swe cleared v cc fwe t osc1 min. 0 s md2 to md0 * 1 res swe bit programming/ erasing possible wait time: x wait time: 100 s t mds * 3 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 21b-27 power-on/off timing (user program mode)
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 861 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds t mds t mds * 2 t resw md2 to md0 res swe bit mode change * 1 mode change * 1 boot mode user mode user program mode swe set swe cleared programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s user mode user program mode notes: 1. when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. 2. when making a transition from boot mode to another mode, a mode programming setup time t mds (min.) of 200 ns is necessary with respect to res clearance timing. 3. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. figure 21b-28 mode transition timing (example: boot mode user mode ? ? ? ? user program mode)
section 21b rom (h8s/2638 group, h8s/2639 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 862 of 1484 rej09b0103-0600 21b.16 note on switching from f-ztat version to mask rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 21b-24 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 21b-24 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 21b-27 have no effect. table 21b-27 registers present in f-ztat version but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 863 of 1484 rej09b0103-0600 section 21c rom (h8s/2635 group) 21c.1 overview the h8s/2635 group has 192 kbytes of on-chip flash memory, or 192 kbytes or 128 kbytes of on- chip mask rom. the rom is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the on-chip rom is enabled and disabled by setting the mode pins (md2 to md0). the flash memory version can be erased and programmed on-board, as well as with a special- purpose prom programmer. 21c.1.1 block diagram figure 21c-1 shows a block diagram of 192-kbyte and 128-kbyte rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'000001 h'000003 h'02fffe (h'01fffe) * h'02ffff (h'01ffff) * note: * rom addresses for the h8s/2635 extend from h'000000 to h'02ffff (192 kbytes), and for the h8s/2634 from h'000000 to h'01ffff (128 kbytes). figure 21c-1 block diagram of rom 192 kbytes (128 kbytes) *
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 864 of 1484 rej09b0103-0600 21c.1.2 register configuration the h8s/2638 and h8s/2639 operating mode is controlled by the mode pins and the mdcr register. the register configuration is shown in table 21c-1. table 21c-1 register configuration register name abbreviation r/w initial value address * mode control register mdcr r/w undefined h'fde7 note: * lower 16 bits of the address. 21c.2 register descriptions 21c.2.1 mode control register (mdcr) bit:76543210 ?????mds2mds1mds0 initial value:10000? * ? * ? * r/w:r/w???? r r r note: * determined by pins md2 to md0. mdcr is an 8-bit register used to monitor the current h8s/2638 group, h8s/2639 group, and h8s/2630 group operating mode. bit 7?reserved: only 1 should be written to these bits. bits 6 to 3?reserved: these bits are always read as 0 and cannot be modified. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be modified. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. 21c.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 865 of 1484 rej09b0103-0600 the on-chip rom is enabled and disabled by setting the mode pins (md2, md1, and md0). these settings are shown in table 21c-2. table 21c-2 operating modes and rom (f-ztat version) mode pins operating mode fwe md2 md1 md0 on-chip rom mode 0 ? 0 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (192 kbytes/ 128 kbytes) * 3 mode 7 advanced single-chip mode 1 enabled (192 kbytes/ 128 kbytes) * 3 mode 8 ? 1 0 0 0 ? mode 9 1 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (192 kbytes/ 128 kbytes) * 3 mode 11 boot mode (advanced single-chip mode) * 2 1 enabled (192 kbytes/ 128 kbytes) * 3 mode 12 ? 1 0 0 ? mode 13 1 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (192 kbytes/ 128 kbytes) * 3 mode 15 user program mode (advanced single- chip mode) * 2 1 enabled (192 kbytes/ 128 kbytes) * 3 notes: 1. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip rom enabled. 2. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 866 of 1484 rej09b0103-0600 3. the h8s/2635 has 192 kbytes of on-chip rom. the h8s/2634 has 128 kbytes of on- chip rom. table 21c-3 operating modes and rom (mask rom version) mode pins operating mode md2 md1 md0 on-chip rom mode 0 ? 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 100disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 10 enabled (192 kbytes/ 128 kbytes) * mode 7 advanced single-chip mode 1 enabled (192 kbytes/ 128 kbytes) * note: * the h8s/2635 has 192 kbytes of on-chip rom. the h8s/2634 has 128 kbytes of on-chip rom.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 867 of 1484 rej09b0103-0600 21c.4 flash memory overview 21c.4.1 features the h8s/2635 has 192 kbytes of on-chip flash memory, or 192 kbytes or 128 kbytes of on-chip mask rom. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. to erase the entire flash memory, each block must be erased in turn. block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte progra mming, equivalent to 80 s (typ.) per byte, and the erase time is 100 ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the lsi?s bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 868 of 1484 rej09b0103-0600 ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. 21c.4.2 block diagram module bus bus interface/controller flash memory (192 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flpwcr flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register flash memory power control register legend: flmcr1: flmcr2: ebr1: ebr2: ramer: flpwcr: figure 21c-2 block diagram of flash memory
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 869 of 1484 rej09b0103-0600 21c.4.3 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 21c-3. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode res = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md0 = 0, md1 = 0, md2 = 0, p14 = 0, p16 = 0, pf0 = 1 res = 0 md2 = 0, md1 = 1, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 21c-3 flash memory state transitions
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 870 of 1484 rej09b0103-0600 21c.4.4 on-board programming modes boot mode flash memory chip ram host programming control program sci application program (old version) new application program flash memory chip ram host sci application program (old version) boot program area new application program flash memory chip ram host sci flash memory preprogramming erase boot program new application program flash memory chip program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 871 of 1484 rej09b0103-0600 user program mode flash memory chip ram host programming/ erase control program sci boot program new application program flash memory chip ram host sci new application program flash memory chip ram host sci flash memory erase boot program new application program flash memory chip program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 872 of 1484 rej09b0103-0600 21c.4.5 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 21c-4 reading overlap ram data in user mode or user program mode when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 873 of 1484 rej09b0103-0600 application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 21c-5 writing overlap ram data in user program mode 21c.4.6 differences between boot mode and user program mode table 21c-4 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify emulation note: * to be provided by the user, in accordance with the recommended algorithm.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 874 of 1484 rej09b0103-0600 21c.4.7 block configuration the h8s/2635 has 192 kbytes of flash memory, which is divided into two 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. address h'00000 a ddress h'2ffff 32 kbytes 64 kbytes 64 kbytes 192 kbytes 4 kbytes 8 h8s/2635 figure 21c-6 flash memory block configuration
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 875 of 1484 rej09b0103-0600 21c.5 pin configuration the flash memory is controlled by means of the pins shown in table 21c-5. table 21c-5 pin configuration pin name abbreviation i/o function reset res input reset flash write enable fwe input flash memory program/erase protection by hardware mode 2 md2 input sets mcu operating mode mode 1 md1 input sets mcu operating mode mode 0 md0 input sets mcu operating mode port f0 pf0 input sets mcu operating mode in programmer mode port 16 p16 input sets mcu operating mode in programmer mode port 14 p14 input sets mcu operating mode in programmer mode transmit data txd1 output serial transmit data output receive data rxd1 input serial receive data input
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 876 of 1484 rej09b0103-0600 21c.6 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 21c-6. table 21c-6 register configuration register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 4 r/w h'00 * 2 h'ffa8 flash memory control register 2 flmcr2 * 4 r h'00 h'ffa9 erase block register 1 ebr1 * 4 r/w h'00 * 3 h'ffaa erase block register 2 ebr2 * 4 r/w h'00 * 3 h'ffab ram emulation register ramer * 4 r/w h'00 h'fedb flash memory power control register flpwcr * 4 r/w h'00 * 3 h'ffac notes: 1. lower 16 bits of the address. 2. when a high level is input to the fwe pin, the initial value is h'80. 3. when a low level is input to the fwe pin, or if a high level is input and the swe1 bit in flmcr1 is not set, these registers are initialized to h'00. 4. flmcr1, flmcr2, ebr1, and ebr2, ramer, and flpwcr are 8-bit registers. use byte access on these registers.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 877 of 1484 rej09b0103-0600 21c.7 register descriptions 21c.7.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the pv or ev bit. program mode for on-chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode for on- chip flash memory is entered by setting swe bit to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read w ill return h'00, and writes are invalid. writes are enabled only in the following cases: writes to bit swe of flmcr1 enabled when fwe = 1, to bits esu, psu, ev, and pv when fwe = 1 and swe = 1, to bit e when fwe = 1, swe = 1 and esu = 1, and to bit p when fwe = 1, swe = 1, and psu = 1. bit:76543210 fwe swe esu psu ev pv e p initial value: ? * 0000000 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. bit 7?flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 878 of 1484 rej09b0103-0600 bit 6?software write enable bit (swe): this bit selects write and erase valid/invalid of the flash memory. set it when setting bits 5 to 0, bits 7 to 0 of ebr1, and bits 2 to 0 of ebr2. bit 6 swe description 0 writes disabled (initial value ) 1 writes enabled [setting condition] ? when fwe = 1 bit 5?erase setup bit (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit in flmcr1 to 1. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5 esu description 0 erase setup cleared (initial value ) 1 erase setup [setting condition] ? when fwe = 1 and swe = 1 bit 4?program setup bit (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit in flmcr1 to 1. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4 psu description 0 program setup cleared (initial value ) 1 program setup [setting condition] ? when fwe = 1 and swe = 1
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 879 of 1484 rej09b0103-0600 bit 3?erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3 ev description 0 erase-verify mode cleared (initial value ) 1 transition to erase-verify mode [setting condition] ? when fwe = 1 and swe = 1 bit 2?program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2 pv description 0 program-verify mode cleared (initial value ) 1 transition to program-verify mode [setting condition] ? when fwe = 1 and swe = 1 bit 1?erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1 e description 0 erase mode cleared (initial value ) 1 transition to erase mode [setting condition] ? when fwe = 1, swe = 1, and esu = 1 bit 0?program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 880 of 1484 rej09b0103-0600 bit 0 p description 0 program mode cleared (initial value ) 1 transition to program mode [setting condition] ? when fwe = 1, swe = 1, and psu = 1 21c.7.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00. bit:76543210 fler??????? initial value:00000000 r/w:r ??????? note: flmcr2 is a read-only register, and should not be written to. bit 7?flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally (initial value ) flash memory program/erase protection (error protection) is disabled [clearing condition] ? reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] ? see section 21c.10.3, error protection bits 6 to 0?reserved: these bits always read 0.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 881 of 1484 rej09b0103-0600 21c.7.3 erase block register 1 (ebr1) ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid. the flash memory erase block configuration is shown in table 21c-7. bit:76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 21c.7.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin. bit 0 w ill be initialized to 0 if bit swe of flmcr1 is not set, even though a high level is input to pin fwe. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. on the h8s/2635 bits 7 to 3 are reserved. only 0 may be written to these reserved bits. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory erase block configuration is shown in table 21c-7. bit:76543210 ?????eb10eb9eb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: bits 7 to 3 are reserved and only 0 may be written to them.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 882 of 1484 rej09b0103-0600 table 21c-7 flash memory erase blocks block (size) addresses eb0 (4 kbytes) h'000000 to h'000fff eb1 (4 kbytes) h'001000 to h'001fff eb2 (4 kbytes) h'002000 to h'002fff eb3 (4 kbytes) h'003000 to h'003fff eb4 (4 kbytes) h'004000 to h'004fff eb5 (4 kbytes) h'005000 to h'005fff eb6 (4 kbytes) h'006000 to h'006fff eb7 (4 kbytes) h'007000 to h'007fff eb8 (32 kbytes) h'008000 to h'00ffff eb9 (64 kbytes) h'010000 to h'01ffff eb10 (64 kbytes) h'020000 to h'02ffff 21c.7.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 21c-8. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit:76543210 ????ramsram2ram1ram0 initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 883 of 1484 rej09b0103-0600 bits 7 and 6?reserved: these bits always read 0. bits 5 and 4?reserved: only 0 may be written to these bits. bit 3?ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 3 rams description 0 emulation not selected (initial value ) program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2 to 0?flash memory area selection: these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 21c-8.) table 21c-8 flash memory area divisions addresses block name rams ram1 ram1 ram0 h'ffd800 to h'ffe7ff ram area 4 kbytes 0 *** h'000000 to h'000fff eb0 (4 kbytes) 1 0 0 0 h'001000 to h'001fff eb1 (4 kbytes) 1 0 0 1 h'002000 to h'002fff eb2 (4 kbytes) 1 0 1 0 h'003000 to h'003fff eb3 (4 kbytes) 1 0 1 1 h'004000 to h'004fff eb4 (4 kbytes) 1 1 0 0 h'005000 to h'005fff eb5 (4 kbytes) 1 1 0 1 h'006000 to h'006fff eb6 (4 kbytes) 1 1 1 0 h'007000 to h'007fff eb7 (4 kbytes) 1 1 1 1 * : don't care
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 884 of 1484 rej09b0103-0600 21c.7.6 flash memory power control register (flpwcr) bit:76543210 pdwnd??????? initial value:00000000 r/w:r/wrrrrrrr flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. bit 7?power-down disable (pdwnd): the subactive mode is not available in versions other than the u-mask and w-mask versions. only 0 should be written to this bit in the case of versions other than the u-mask and w-mask versions. see section 21.b.14, flash memory and power-down states, for more information. bit 7 pdwnd description 0 transition to flash memory power-down mode enabled (initial value) 1 transition to flash memory power-down mode disabled bits 6 to 0?reserved: these bits always read 0.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 885 of 1484 rej09b0103-0600 21c.8 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 21c-9. for a diagram of the transitions to the various flash memory modes, see figure 21c-3. table 21c-9 setting on-board programming modes mode fwe md2 md1 md0 boot mode expanded mode 1 0 1 0 single-chip mode 0 1 1 user program mode expanded mode 1 1 1 0 single-chip mode 1 1 1
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 886 of 1484 rej09b0103-0600 21c.8.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset-start is executed after the h8s/2635 group?s pins have been set to boot mode, the boot program built into the h8s/2635 group are started and the progra mming control program prepared in the host is serially transmitted to the h8s/ 2635 group via the sci. in the h8s/2635 group, the progra mming control program r eceived via the sci is written into the progra mming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 21c-7, and the boot mode execution procedure in figure 21c-8. rxd1 txd1 sci1 lsi flash memory write data reception verify data transmission host on-chip ram figure 21c-7 system configuration in boot mode
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 887 of 1484 rej09b0103-0600 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate chip measures low period of h'00 data transmitted by host chip calculates bit rate and sets value in bit rate register after bit rate adjustment, chip transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, lsi transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte chip transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units chip transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, chip transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 21c-8 boot mode execution procedure
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 888 of 1484 rej09b0103-0600 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) when boot mode is initiated, the lsi measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/r eceive format should be set as follows: 8-bit data, 1 stop bit, no parity. the lsi calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the lsi. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host?s transmission bit rate and the lsi?s system clock frequency, there will be a discrepancy between the bit rates of the host and the lsi. set the host transfer bit rate at 4,800, 9,600 or 19,200 bps to operate the sci properly. table 21c-10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the lsi bit rate is possible. the boot program should be executed within this system clock range. table 21c-10 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency for which automatic adjustment of lsi bit rate is possible 4,800 bps 4 to 20 mhz 9,600 bps 8 to 20 mhz 19,200 bps 16 to 20 mhz note: the system clock frequency used in boot mode is generated by an external crystal oscillator element. pll frequency multiplication is not used.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 889 of 1484 rej09b0103-0600 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 21c-9. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffe000 h'ffe7ff h'ffe800 h'ffefbf boot program area (1.9 kbytes) programming control program area (2 kbytes) note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. figure 21c-9 ram areas in boot mode notes on use of boot mode: ? when the chip comes out of reset in boot mode, it measures the low-level period of the input at the sci?s rxd1 pin. the reset should end with rxd1 high. after the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the rxd1 pin. ? in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. ? interrupts cannot be used while the flash memory is being programmed or erased. ? the rxd1 and txd1 pins should be pulled up on the board.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 890 of 1484 rej09b0103-0600 ? before branching to the programming control program (ram area h'ffe 000), the chip terminates transmit and receive operations by the on-chip sci (channel 1) (by clearing the re and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, txd1, goes to the high-level output state (p33ddr = 1, p33dr = 1). the contents of the cpu?s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. ? boot mode can be entered by making the pin settings shown in table 21c-9 and executing a reset-start. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release * 1 . boot mode can also be cleared by a wdt overflow reset. do not change the mode pin input levels in boot mode, and do not drive the fwe pin low while the boot program is being executed or while flash memory is being programmed or erased * 2 . ? if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( as , rd , hwr ) will change according to the change in the microcomputer?s operating mode * 3 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: 1. mode pin and fwe pin input must satisfy the mode progra mming setup time (t mds = 4 states) with respect to the reset release timing. 2. for precautions on applying and disconnecting fwe, see section 21c.15, flash memory programming and erasing precautions. 3. see appendix d, pin states. 21c.8.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 891 of 1484 rej09b0103-0600 to select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. the flash memory itself cannot be read while the swe bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing s hould be run in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. figure 21c-10 shows the procedure for executing the program/erase control program when transferred to on-chip ram. clear fwe * fwe = high * branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md2, md1, md0 = 110, 111 reset-start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand notes: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * for further information on fwe application and disconnection, see section 21b.15, flash memory programming and erasing precautions. figure 21c-10 user program mode execution procedure
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 892 of 1484 rej09b0103-0600 21c.9 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1 for on-chip flash memory. the flash memory cannot be read while it is being written or erased. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing s hould be located and executed in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. also ensure that the dtc is not activated before or after execution of the flash memory write instruction. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 24.2.7 and 24.3.7, flash memory characteristics. notes: 1. operation is not guaranteed if bits swe, esu, psu, ev, pv, e, and p of flmcr1 are set/reset by a program in flash memory in the corresponding address areas. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming s hould be performed in the erased state. do not perform additional programming on previously programmed addresses.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 893 of 1484 rej09b0103-0600 normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe = 1 swe = 0 fwe = 1 fwe = 0 e = 1 e = 0 p = 1 p = 0 software programming enable state * 1 * 2 * 3 * 4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. 1. : normal mode : on-board programming mode 2. do not make a state transition by setting or clearing multiple bits simultaneously. 3. after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu = 0 esu = 1 psu = 1 psu = 0 pv = 1 pv = 0 ev = 0 ev = 1 figure 21c-11 flmcr1 bit settings and state transitions
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 894 of 1484 rej09b0103-0600 21c.9.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 21c-12 should be followed. performing progra mming operations according to this flowchart will enable data or programs to be written to flash memory wit hout subjecting the device to voltage stress or sacrificing program data reliability. programming s hould be carried out 128 bytes at a time. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n) are shown in table 24-22 in section 24.2.7, and in table 24-34 in section 24.3.7, and in table 24-46 in section 24.4.7, flash memory characteristics. following the elapse of (t sswe ) s or more after the swe bit is set to 1 in flmcr1, 128-byte data is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 and h'80, 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer (wdt) is set to prevent overprogra mming due to program runaway, etc. set a value greater than (t spsu + t sp + t cp + t cpsu ) s as the wdt overflow period. preparation for entering program mode (program setup) is performed next by setting the psu bit in flmcr1. the operating mode is then switched to program mode by setting the p bit in flmcr1 after the elapse of at least (t spsu ) s. the time during which the p bit is set is the flash memory programming time. make a program setting so that the time for one programming operation is within the range of (t sp ) s. the wait time after p bit setting must be changed according to the degree of progress through the programming operati on. for details see ?notes on program/program-verify procedure.?
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 895 of 1484 rej09b0103-0600 21c.9.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p bit in flmcr1, then wait for at least (t cp ) s before clearing the psu bit to exit program mode. after exiting program mode, the watchdog timer setting is also cleared. the operating mode is then switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t spv ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t spvr ) s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 21c-12) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (t cpv ) s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (n). leave a wait time of at least (t cswe ) s after clearing swe. notes on program/program-verify procedure 1. in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. 2. when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. 3. verify data is read in word units. 4. the write pulse is applied and a flash memory write executed while the p bit in flmcr1 is set. in the chip, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the chip, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming c ount (n).
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 896 of 1484 rej09b0103-0600 b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. the following processing is necessary for programmed bits. when programming is completed at an early stage in the program/program-verify procedure: if programming is completed in the 1st to 6th reprogramming processing l oop, additional programming s hould be performed on the relevant bits. additional progra mming s hould only be performed on bits which first return 0 in a verify-read in certain reprogramming processing. when programming is completed at a late stage in the program/program-verify procedure: if programming is completed in the 7th or later reprogramming processing l oop, additional programming is not necessary for the relevant bits. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which progra mming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. the period for which the p bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. item symbol item symbol t sp when reprogramming loop count (n) is 1 to 6 t sp30 wait time after p bit setting when reprogramming loop count (n) is 7 or more t sp200 in case of additional programming processing * t sp10 note: * additional programming processing is necessary only when the reprogramming loop count (n) is 1 to 6. 6. the program/program-verify flowchart for the h8s/2638, h8s/2639, and h8s/2630 are shown in figure 21c-12. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 897 of 1484 rej09b0103-0600 reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 0 0 1 programming completed: reprogramming processing not to be executed 01 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend: (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend: (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop 7. it is necessary to execute additional programming processing during the course of the chip program/program-verify procedure. however, once 128-byte-unit progra mming is finished, additional programming s hould not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 898 of 1484 rej09b0103-0600 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s sub-routine write pulse end sub set psu bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note: 6 write pulse width write time (tsp) sec 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p bit in flmcr1 wait (t sp ) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s n = 1 m = 0 no no no no yes yes yes wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming end of programming * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s write pulse sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note 6 for pulse width m = 0 ? increment address programming failure yes clear swe bit in flmcr1 wait (t cswe ) s no yes 6 n? no yes 6 n ? wait (t cswe ) s n (n)? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to t he extra addresses. 2. verify data is read in 16-bit (word) units. 3. reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program d ata area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing addit ional data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. 7. the wait times and value of n are shown in section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. figure 21c-12 program/program-verify flowchart
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 899 of 1484 rej09b0103-0600 21c.9.3 erase mode when erasing flash memory, the single-block erase flowchart shown in figure 21c-13 should be followed. the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of erase operations (n) are shown in table 24-10 in section 24.2.7 and 24.3.7, flash memory characteristics. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (ebr1, ebr2) at least (t sswe ) s after setting the swe bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (t se ) ms + (t sesu + t ce + t cesu ) s as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu bit in flmcr1. the operating mode is then switched to erase mode by setting the e bit in flmcr1 after the elapse of at least (t sesu ) s. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (t se ) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 21c.9.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e bit in flmcr1, then wait for at least (t ce ) s before clearing the esu bit to exit erase mode. after exiting erase mode, the watchdog timer setting is also cleared. the operating mode is then switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of (t sev ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least (t sevr ) s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is indicated by the maximum erase count (n). when verification is completed, exit erase-verify mode, and wait for at least (t cev ) s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1, and leave a wait time of at least (t cswe ) s.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 900 of 1484 rej09b0103-0600 if erasing multiple blocks, set a single bit in ebr1/ebr2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. end of erasing start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait (t sswe ) s wait (t sesu ) s n = 1 set ebr1 or ebr2 enable wdt * 3 * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 wait (t se ) ms wait (t ce ) s wait (t cesu ) s wait (t sev ) s set block start address as verify address wait (t sevr ) s * 2 wait (t cev) s start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait (t cev ) s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1s? last address of block? erase failure clear swe bit in flmcr1 n (n)? no no no yes yes yes n n + 1 increment address wait (t cswe ) s wait (t cswe ) s notes: 1. prewriting (setting erase block data to all 0s) is not necessary. 2. verify data is read in 16-bit (word) units. 3. make only a single-bit specification in the erase block registers (ebr1 and ebr2). two or more bits must not be set simulta neously. 4. erasing is performed in block units. to erase multiple blocks, each block must be erased in turn. 5. the wait times and the value of n are shown in section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. perform erasing in block units. figure 21c-13 erase/erase-verify flowchart
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 901 of 1484 rej09b0103-0600 21c.10 protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 21c.10.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, flmcr2, ebr1, and ebr2 settings are retained in the error-protected state (see table 21c-11). table 21c-11 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2, (except bit fler) ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a reset (including a wdt reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 902 of 1484 rej09b0103-0600 21c.10.2 software protection software protection can be implemented by setting the swe bit in flmcr1, erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1), does not cause a transition to program mode or erase mode (see table 21c-12). table 21c-12 software protection functions item description program erase swe bit protection ? setting bit swe in flmcr1 to 0 will place area on-chip flash memory in the program/ erase-protected state (execute the program in the on-chip ram, external memory). yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. ?yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 903 of 1484 rej09b0103-0600 21c.10.3 error protection in error protection, an error is detected when chip runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the chip malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. immediately after exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing error protection is released only by a reset and in hardware standby mode.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 904 of 1484 rej09b0103-0600 figure 21c-14 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence res = 0 or hstby = 0 res = 0 or hstby = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2, (except bit fler) ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend: res = 0 or hstby = 0 error occurrence (software standby) figure 21c-14 flash memory state transitions
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 905 of 1484 rej09b0103-0600 21c.11 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 21c-15 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 21c-15 flowchart for flash memory emulation in ram
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 906 of 1484 rej09b0103-0600 h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'2ffff flash memory eb8 to eb10 h8s/2635 eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ffd800 h'ffe7ff h'ffefbf on-chip ram this area can be accessed from both the ram area and flash memory area figure 21c-16 example of ram overlap operation example in which flash memory block area eb0 is overlapped 1. set bits rams, ram2 to ram0 in ramer to 1, 0, 0, 0, to overlap part of ram onto the area (eb0) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1), will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 907 of 1484 rej09b0103-0600 21c.12 interrupt handling when programming/erasing flash memory all interrupts, including nmi interrupt is disabled when flash memory is being programmed or erased (when the p or e bit is set in flmcr1), and while the boot program is executing in boot mode * 1 , to give priority to the program or erase operation. there are three reasons for this: 1. interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly * 2 , possibly resulting in mcu runaway. 3. if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operati on. all requests, including nmi interrupt, must therefore be restricted inside and outside the mcu when programming or erasing flash memory. nmi interrupt is also disabled in the error-protection state while the p or e bit remains set in flmcr1. notes: 1. interrupt requests must be disabled inside and outside the mcu until the programming control program has completed programming. 2. the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 21c.13 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to programmer mode (see table 21c-13) and input a 12 mhz input clock.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 908 of 1484 rej09b0103-0600 table 21c-13 shows the pin settings for programmer mode. table 21c-13 programmer mode pin settings pin names settings mode pins: md2, md1, md0 low level input to md2, md1, and md0. mode setting pins: pf0, p16, p14 high level input to pf0, low level input to p16 and p14 fwe pin high level input (in auto-program and auto-erase modes) res pin reset circuit xtal, extal, pllcap, pllvss pins oscillator circuit vcl internal voltage step-down circuit 21c.13.1 socket adapter and memory map in programmer mode in which the prom writer is used, reading from memory (verification), writing, and initializing the flash memory (erasing all of its contents) are enabled. at this time, a dedicated conversion socket adapter must be attached to a general-purpose prom writer. table 21c-14 shows the types of the socket adapters. for programmer mode on this lsi, one of the socket adapters listed in table 21c-14 should be used. table 21c-14 type of socket adapter product name package type socket adapter type manufacturer me2636eshf1h minato electronics inc. hd64f2635f 128 pin qfp (fp-128b) hf2636q128d4001 data i/o japan corporation
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 909 of 1484 rej09b0103-0600 h'000000 a ddresses in mcu mode addresses in programmer mode h'02ffff h'00000 h'2ffff on-chip rom space 192 kbytes (h8s/2635) figure 21c-17 on-chip rom memory map 21c.13.2 programmer mode operation table 21c-15 shows how the different operating modes are set when using programmer mode, and table 21c-16 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports progra mming of 128 bytes at a time. status po lling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status po lling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 910 of 1484 rej09b0103-0600 table 21c-15 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o7 to i/o0 a18 to a0 read h or l l l h data output ain * 2 output disable h or l l h h hi-z x command write h or l * 3 l h l data input ain * 2 chip disable * 1 h or lhxxhi-zx notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. table 21c-16 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 21c.13.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 911 of 1484 rej09b0103-0600 table 21c-17 ac characteristics in transition to memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce oe ce a18 to a0 oe we i/o7 to i/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 21c-18 timing waveforms for memory read after memory write
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 912 of 1484 rej09b0103-0600 table 21c-18 ac characteristics in transition from memory read mode to another mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 21c-19 timing waveforms in transition from memory read mode to another mode
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 913 of 1484 rej09b0103-0600 table 21c-19 ac characteristics in memory read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit access time t acc ?20s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5?ns ce a18 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 21c-20 ce and oe enable state read timing waveforms ce a18 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 21c-21 ce and oe clock system read timing waveforms
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 914 of 1484 rej09b0103-0600 21c.13.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when progra mming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 21c-22). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe .
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 915 of 1484 rej09b0103-0600 table 21c-20 ac characteristics in auto-program mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1?ms status polling access time t spa ? 150 ns address setup time t as 0?ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms write setup time t pns 100 ? ns write end setup time t pnh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 21c-22 auto-program mode timing waveforms
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 916 of 1484 rej09b0103-0600 21c.13.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 21c-21 ac characteristics in auto-erase mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1?ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ? ns erase end setup time t enh 100 ? ns we rise time t r ?30ns we fall time t f ?30ns
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 917 of 1484 rej09b0103-0600 ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase end decision signal erase normal end decision signal figure 21c-23 auto-erase mode timing waveforms
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 918 of 1484 rej09b0103-0600 21c.13.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 21c-22 ac characteristics in status read mode conditions: v cc = 5.0 v 0.5 v, v ss = 0 v, t a = 25c 5c item symbol min. max. unit read time after command write t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ?30ns we fall time t f ?30ns ce a18 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 21c-24 status read mode timing waveforms
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 919 of 1484 rej09b0103-0600 table 21c-23 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end decision command error program- ming error erase error ?? program- ming or erase count exceeded effective address error initial value00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 ??count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined. 21c.13.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 21c-24 status polling output truth table pin name during internal operation abnormal end ? normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o0 to i/o5 0 0 0 0 21c.13.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 21c-25 stipulated transition times to command wait state item symbol min. max. unit standby release (oscillation stabilization time) t osc1 30 ? ms programmer mode setup time t bmv 10 ? ms v cc hold time t dwn 0?ms
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 920 of 1484 rej09b0103-0600 t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal end decision note: when using other than the automatic write mode and automatic erase mode, drive the fwe input pin low. figure 21c-25 oscillation stabilization time, boot program transfer time, and power-down sequence 21c.13.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming s hould be performed once only on the same address block. additional programming ca nnot be performed on previously programmed address blocks.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 921 of 1484 rej09b0103-0600 21c.14 flash memory and power-down states in addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. there are three flash memory operating states: (1) normal operating mode: the flash memory can be read and written to. (2) power-down mode: part of the power supply circuitry is halted, and the flash memory can be read when the lsi is operating on the subclock. (3) standby mode: all flash memory circuits are halted, and the flash memory cannot be read or written to. states (2) and (3) are flash memory power-down states. table 21c-26 shows the correspondence between the operating states of the lsi and the flash memory. table 21c-26 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal mode (read/write) subactive mode subsleep mode when pdwnd = 0: power-down mode (read-only) when pdwnd = 1: normal mode (read-only) watch mode software standby mode hardware standby mode standby mode
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 922 of 1484 rej09b0103-0600 21c.14.1 notes on power-down states 1. when the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. therefore, a power supply circuit stabilization period must be provided when returning to normal operation. when the flash memory returns to its normal operating state from a power-down state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 2. in a power-down state, flmcr1, flmcr2, ebr1, ebr2, ramer, and flpwcr cannot be read from or written to. 21c.15 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and programmer mode are summarized below. use the specified voltages and timing for programming and erasing: applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the renesas microcomputer device type * with 256-kbyte on-chip flash memory. only use the specified socket adapter. failure to observe these points may result in damage to the device. note: * the h8s/2635 is renesas technology microcomputer devices with 256 kbytes of on-chip flash memory. (the h8s/2635 has 192 kbytes of prom. the area from h'30000 to h'3ffff should be programmed as h'ff.) powering on and off (see figures 21c-26 to 21c-28): do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements s hould also be satisfied in the event of a power failure and subsequent recovery.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 923 of 1484 rej09b0103-0600 fwe application/disconnection (see figures 21c-26 to 21c-28): fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the v cc voltage has stabilized within its rated voltage range. apply fwe when oscillation has stabilized (after the elapse of the oscillation stabilization time). ? in boot mode, apply and disconnect fwe during a reset. ? in user program mode, fwe can be switched between high and low level regardless of the reset state. fwe input can also be switched during execution of a program in flash memory. ? do not apply fwe if program runaway has occurred. ? disconnect fwe only when the swe, esu, psu, ev, pv, p, and e bits in flmcr1 are cleared. make sure that the swe, esu, psu, ev, pv, p, and e bits are not set by mistake when applying or disconnecting fwe. do not apply a constant high level to the fwe pin: apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogra mming or overerasing due to program runaway, etc. use the recommended algorithm when programming and erasing flash memory: the recommended algorithm enables programming and erasing to be carried out wit hout subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. do not set or clear the swe bit during execution of a program in flash memory: wait for at least 100 s after clearing the swe bit before executing a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but when swe = 1, flash memory can only be read in program-verify or erase-verify mode. access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a high level is being i nput to the fwe pin, the swe bit must be cleared before executing a program or reading data in flash memory.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 924 of 1484 rej09b0103-0600 however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. do not use interrupts while flash memory is being programmed or erased: all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming: in on- board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perform only one progra mming operation on a 128-byte programming unit block. programming s hould be carried out with the entire progra mming unit block erased. before programming, check that the chip is correctly mounted in the prom programmer: overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. do not touch the socket adapter or chip during programming: touching either of these can cause contact faults and write errors.
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 925 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds * 3 t mds * 3 md2 to md0 * 1 res swe bit swe set swe cleared programming/ erasing possible wait time: x wait time: 100 s notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns min. 0 s figure 21c-26 power-on/off timing (boot mode)
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 926 of 1484 rej09b0103-0600 swe set swe cleared v cc fwe t osc1 min. 0 s md2 to md0 * 1 res swe bit programming/ erasing possible wait time: x wait time: 100 s t mds * 3 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 21c-27 power-on/off timing (user program mode)
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 927 of 1484 rej09b0103-0600 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min. 0 s t mds t mds t mds * 2 t resw md2 to md0 res swe bit mode change * 1 mode change * 1 boot mode user mode user program mode swe set swe cleared programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s user mode user program mode notes: 1. when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. 2. when making a transition from boot mode to another mode, a mode programming setup time t mds (min.) of 200 ns is necessary with respect to res clearance timing. 3. see section 24.2.7, 24.3.7, and 24.4.7, flash memory characteristics. figure 21c-28 mode transition timing (example: boot mode user mode ? ? ? ? user program mode)
section 21c rom (h8s/2635 group) rev. 6.00 feb 22, 2005 page 928 of 1484 rej09b0103-0600 21c.16 note on switching from f-ztat version to mask rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 21c-24 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 21c-24 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 21c-27 have no effect. table 21c-27 registers present in f-ztat version but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 929 of 1484 rej09b0103-0600 section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) 22a.1 overview the chip has a built-in clock pulse generator (cpg) that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator, pll (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. the frequency can be changed by means of the pll circuit in the cpg. frequency changes are performed by software by means of settings in the system clock control register (sckcr) and low-power control register (lpwrcr). 22a.1.1 block diagram figure 22a-1 shows a block diagram of the clock pulse generator. legend: lpwrcr: sckcr: note: * low-power control register system clock control register subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. extal xtal pll circuit ( 1, 2, 4) medium- speed clock divider system clock oscillator clock selection circuit sub wdt1 count clock system clock to pin internal clock to supporting modules bus master clock to cpu and dtc /2 to /32 sck2 to sck0 sckcr stc1, stc0 osc1 osc2 waveform generation circuit subclock oscillator lpwrcr bus master clock selection circuit * * figure 22a-1 block diagram of clock pulse generator
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 930 of 1484 rej09b0103-0600 22a.1.2 register configuration the clock pulse generator is controlled by sckcr and lpwrcr. table 22a-1 shows the register configuration. table 22a-1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec note: * lower 16 bits of the address. 22a.2 register descriptions 22a.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control and medium- speed mode control, selection of operation when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): in combination with the ddr of the applicable port, this bit controls output. see section 23a.8, 23b.12, clock output disable function for details. description bit 7 pstop normal operating state sleep mode software standby mode hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 to 4?reserved: these bits are always read as 0 and cannot be modified.
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 931 of 1484 rej09b0103-0600 bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode, watch mode * , and subactive mode * (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. bits 2 to 0?system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1?? 22a.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit initial value read/write lpwrcr is an 8-bit readable/writable register that performs power-down mode control. the following pertains to bits 1 and 0. for details of the other bits, see section 23a.2.3, 23b.2.3, low power control register (lpwrcr). lpwrcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode.
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 932 of 1484 rej09b0103-0600 bits 1 and 0?frequency multiplication factor (stc1, stc0): the stc bits specify the frequency multiplication factor of the pll circuit. bit 1 bit 0 stc1 stc0 description 00 1 (initial value) 1 2 10 4 1 setting prohibited note: the multiplication factor should be set so that the clock frequency following multiplication does not exceed the maximum operating frequency of the lsi. it is possible to reduce power consumption and noise by using a setting of pll 4 for this function and lowering the external clock frequency. 22a.3 oscillator clock pulses may be supplied either by connecting a crystal osc illator or inputting an external clock. in the latter case, the input clock frequency should be between 4 mhz and 20 mhz. 22a.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 22a-2. select the damping resistance r d according to table 22a-2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22pf figure 22a-2 connection of crystal resonator (example) table 22a-2 damping resistance value frequency (mhz) 4 8 12 16 20 r d ( ? ) 500 200 0 0 0
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 933 of 1484 rej09b0103-0600 crystal resonator: figure 22a-3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 22a-3. the crystal resonator frequency should not exceed 20 mhz. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 22a-3 crystal resonator equivalent circuit table 22a-3 crystal resonator parameters frequency (mhz) 4 8 12 16 20 r s max ( ? ) 120 80 60 50 40 c 0 max (pf) 77777 note on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the osc illator circuit to prevent i nduction from interfering with correct oscillati on. see figure 22a-4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 chip xtal extal avoid figure 22a-4 example of incorrect board design
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 934 of 1484 rej09b0103-0600 external circuitry such as that shown below is recommended around the pll. pllcap pllvss vcc vss r1: 3 k w c1: 470 pf cb: 0.1 m f * note: * cb is laminated ceramic capacitors. (values are preliminary recommended values.) figure 22a-5 points for attention when using pll oscillation circuit place oscillation stabilization capacitor c1 and resistor r1 close to the pllcap pin, and ensure that no other signal lines cross this line. supply the c1 ground from pllvss. separate pllvss from the other vcc and vss lines at the board power supply source, and be sure to insert bypass capacitors cb close to the pins.
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 935 of 1484 rej09b0103-0600 22a.3.2 external clock input circuit configuration an external clock signal can be input as shown in the examples in figure 22a-6. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode. in this case, the input clock frequency should be between 4 mhz and 20 mhz. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) complementary clock input at xtal pin figure 22a-6 external clock input (examples)
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 936 of 1484 rej09b0103-0600 external clock table 22a-4 and figure 22a-7 show the input conditions for the external clock. table 22a-4 external clock input conditions v cc = 5.0 v 10% item symbol min. max. unit test conditions external clock input low pulse width t exl 15 ? ns figure 22a-7 external clock input high pulse width t exh 15 ? ns external clock rise time t exr ?5 ns external clock fall time t exf ?5 ns t exh t exl t exr t exf v cc 0.5 extal figure 22a-7 external clock input timing
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 937 of 1484 rej09b0103-0600 22a.4 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. the multiplication factor is set with the stc bits in sckcr. the phase of the rising edge of the internal clock is controlled so as to match that at the extal pin. when the multiplication factor of the pll circuit is changed, the operation varies according to the setting of the stcs bit in sckcr. when stcs = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode * , or subactive mode * . the transition time count is performed in accordance with the setting of bits sts2 to sts0 in sbycr. [1] the initial pll circuit multiplication factor is 1. [2] a value is set in bits sts2 to sts0 to give the specified transition time. [3] the target value is set in stc1 and stc0, and a transition is made to software standby mode, watch mode * , or subactive mode * . [4] the clock pulse generator stops and the value set in stc1 and stc0 becomes valid. [5] software standby mode, watch mode * , or subactive mode * is cleared, and a transition time is secured in accordance with the setting in sts2 to sts0. [6] after the set transition time has elapsed, the lsi resumes operation using the target multiplication factor. if a pc break is set for the sleep instruction that causes a transition to software standby mode in [1], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. in this case, the instruction following the sleep instruction is executed after execution of the rte instruction. when stcs = 1, the lsi operates on the changed multiplication factor immediately after bits stc1 and stc0 are rewritten. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions.
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 938 of 1484 rej09b0103-0600 22a.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 22a.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock ( ) or one of the medium-speed clocks ( /2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr. 22a.7 subclock oscillator connecting 32.768khz quartz oscillator (u mask, w mask): to supply a clock to the subclock divider, connect a 32.768khz quartz osc illator, as shown in figure 22a-8. see section 22a.3.1, ?notes on board design? for notes on connecting quartz osc illators. osc1 osc2 c 1 c 2 c 1 =c 2 =15pf (typ) figure 22a-8 example connection of 32.768khz quartz oscillator figure 22a-9 shows the equivalence circuit for a 32.768khz osc illator. osc1 osc2 c s c s r s f w = 1.5 pf (typ.) = 14 k w (typ.) = 32.768 khz l s r s c o figure 22a-9 equivalence circuit for 32.768khz oscillator
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 939 of 1484 rej09b0103-0600 handling pins when subclock not required: if no subclock is required, connect the osc1 pin to vss and leave osc2 open, as shown in figure 22a-10. osc1 osc2 open figure 22a-10 pin handling when subclock not required 22a.8 subclock waveform generation circuit to eliminate noise from the subclock input to osci, the subclock is sampled using the dividing clock . the sampling frequency is set using the nesel bit of lpwrcr. for details, see section 23a.2.3, 23b.2.3, low power control register (lpwrcr). no sampling is performed in subactive mode * , subsleep mode * , or watch mode * . note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. 22a.9 note on crystal resonator since various characteristics related to the crystal resonator are closely linked to the user?s board design, thorough evaluation is necessary on the user?s part, for both the mask versions and f-ztat versions, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.
section 22a clock pulse generator (h8s/2636 group, h8s/2638 group, h8s/2630 group) rev. 6.00 feb 22, 2005 page 940 of 1484 rej09b0103-0600
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 941 of 1484 rej09b0103-0600 section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) 22b.1 overview the chip has a built-in clock pulse generator (cpg) that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator, pll (phase-locked loop) circuit, system clock selection circuit, medium-speed clock divider, bus master clock selection circuit, and subclock divider. the frequency can be changed by means of the pll circuit in the cpg. frequency changes are performed by software by means of settings in the system clock control register (sckcr) and low-power control register (lpwrcr). 22b.1.1 block diagram figure 22b-1 shows a block diagram of the clock pulse generator. legend: lpwrcr: sckcr: low-power control register system clock control register extal xtal pll circuit ( 1, 2, 4) medium- speed clock divider clock oscillator system clock selection circuit sub wdt1 count clock system clock to pin internal clock to supporting modules bus master clock to cpu and dtc /2 to /32 sck2 to sck0 sckcr stc1, stc0 subclock divider (1/128) lpwrcr bus master clock selection circuit figure 22b-1 block diagram of clock pulse generator
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 942 of 1484 rej09b0103-0600 22b.1.2 register configuration the clock pulse generator is controlled by sckcr and lpwrcr. table 22b-1 shows the register configuration. table 22b-1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec note: * lower 16 bits of the address. 22b.2 register descriptions 22b.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control and medium- speed mode control, selection of operation when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): in combination with the ddr of the applicable port, this bit controls output. see section 23b.12, clock output disable function for details. description bit 7 pstop normal operating state sleep mode software standby mode hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 to 4?reserved: these bits are always read as 0 and cannot be modified.
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 943 of 1484 rej09b0103-0600 bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode, watch mode, and subactive mode (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten bits 2 to 0?system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1?? 22b.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit : initial value : r/w : lpwrcr is an 8-bit readable/writable register that performs power-down mode control. the following pertains to bits 1 and 0. for details of the other bits, see section 23b.2.3, low power control register (lpwrcr). lpwrcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode.
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 944 of 1484 rej09b0103-0600 bits 1 and 0?frequency multiplication factor (stc1, stc0): the stc bits specify the frequency multiplication factor of the pll circuit. bit 1 bit 0 stc1 stc0 description 00 1 (initial value) 1 2 10 4 1 setting prohibited note: a system clock frequency multiplied by the multiplication factor (stc1 and stc0) should not exceed the maximum operating frequency defined in section 24, electrical characteristics. 22b.3 oscillator clock pulses may be supplied either by connecting a crystal osc illator or inputting an external clock. in the latter case, the input clock frequency should be between 4 mhz and 5 mhz. 22b.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 22b-2. select the damping resistance r d according to table 22b-2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22pf figure 22b-2 connection of crystal resonator (example) table 22b-2 damping resistance value frequency (mhz) 4 5 r d ( ? ? ? ? ) 500 200
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 945 of 1484 rej09b0103-0600 crystal resonator: figure 22b-3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 18-3. the crystal resonator frequency should not exceed 5 mhz. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 22b-3 crystal resonator equivalent circuit table 22b-3 crystal resonator parameters frequency (mhz) 4 5 r s max ( ? ? ? ? ) 120 80 c 0 max (pf) 77 note on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the osc illator circuit to prevent i nduction from interfering with correct oscillati on. see figure 22b-4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 chip xtal extal avoid figure 22b-4 example of incorrect board design
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 946 of 1484 rej09b0103-0600 external circuitry such as that shown below is recommended around the pll. pllcap pllvss vcc vss r1: 3 k w c1: 470 pf cb: 0.1 m f * note: * cb is laminated ceramic capacitors. (values are preliminary recommended values.) figure 22b-5 points for attention when using pll oscillation circuit place oscillation stabilization capacitor c1 and resistor r1 close to the pllcap pin, and ensure that no other signal lines cross this line. supply the c1 ground from pllvss. separate pllvss from the other vcc and vss lines at the board power supply source, and be sure to insert bypass capacitors cb close to the pins.
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 947 of 1484 rej09b0103-0600 22b.3.2 external clock input circuit configuration an external clock signal can be input as shown in the examples in figure 22b-6. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode. in this case, the input clock frequency should be between 4 mhz and 5 mhz. extal xtal external clock input open (a) xtal pin left open extal xtal note: * in the case of the h8s/2635 group, do not input a complementary clock to the xtal pin. external clock input (b) complementary clock input at xtal pin * figure 22b-6 external clock input (examples)
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 948 of 1484 rej09b0103-0600 external clock table 22b-4 and figure 22b-7 show the input conditions for the external clock. table 22b-4 external clock input conditions v cc = 5.0 v 10% item symbol min. max. unit test conditions external clock input low pulse width t exl 50 ? ns figure 22b-7 external clock input high pulse width t exh 50 ? ns external clock rise time t exr ?5 ns external clock fall time t exf ?5 ns t exh t exl t exr t exf v cc 0.5 extal figure 22b-7 external clock input timing
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 949 of 1484 rej09b0103-0600 22b.4 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. the multiplication factor is set with the stc bits in sckcr. the phase of the rising edge of the internal clock is controlled so as to match that at the extal pin. when the multiplication factor of the pll circuit is changed, the operation varies according to the setting of the stcs bit in sckcr. when stcs = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode, or subactive mode. the transition time count is performed in accordance with the setting of bits sts2 to sts0 in sbycr. [1] the initial pll circuit multiplication factor is 1. [2] a value is set in bits sts2 to sts0 to give the specified transition time. [3] the target value is set in stc1 and stc0, and a transition is made to software standby mode, watch mode, or subactive mode. [4] the clock pulse generator stops and the value set in stc1 and stc0 becomes valid. [5] software standby mode, watch mode, or subactive mode is cleared, and a transition time is secured in accordance with the setting in sts2 to sts0. [6] after the set transition time has elapsed, the lsi resumes operation using the target multiplication factor. if a pc break is set for the sleep instruction that causes a transition to software standby mode in [1], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. in this case, the instruction following the sleep instruction is executed after execution of the rte instruction. when stcs = 1, the lsi operates on the changed multiplication factor immediately after bits stc1 and stc0 are rewritten. 22b.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 22b.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock ( ) or one of the medium-speed clocks ( /2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr.
section 22b clock pulse generator (h8s/2639 group, h8s/2635 group) rev. 6.00 feb 22, 2005 page 950 of 1484 rej09b0103-0600 22b.7 subclock divider the subclock divider divides the input clock into 1/128 to generate sub. 22b.8 note on resonator since various characteristics related to the resonator are closely linked to the user?s board design, thorough evaluation is necessary on the user?s part, for both the mask versions and f-ztat versions, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 951 of 1484 rej09b0103-0600 section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] subclock functions are not available in the hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, and hd6432630f. 23a.1 overview in addition to the normal program execution state, the chip has nine power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting m odules, and so on. the chip operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) sleep mode (4) module stop mode (5) software standby mode (6) hardware standby mode (2) to (6) are low power dissipation states. sleep mode is cpu states, medium-speed mode is a cpu and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the cpu) state. some of these states can be combined. after a reset, the lsi is in high-speed mode with modules other than the dtc in module stop mode. notes: 1. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions only. these functions cannot be used with the other versions. 2. see section 22a.7, subclock osc illator, for the met hod of fixing pins osc1 and osc2 when not used.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 952 of 1484 rej09b0103-0600 table 23a-1 shows the internal state of the lsi in the respective modes. table 23a-2 shows the conditions for shifting between the low power dissipation modes. figure 23a-1 is a mode transition diagram. table 23a-1 lsi internal states in each mode function high- speed medium- speed sleep module stop software standby hardware standby system clock pulse generator functioning functioning functioning functioning halted halted cpu instructions registers functioning medium-speed operation halted (retained) high/medium- speed operation halted (retained) halted (undefined) nmi functioning functioning functioning functioning functioning halted external interrupts irq0 to irq5 peripheral functions wdt1 functioning functioning functioning ? halted (retained) halted (reset) wdt0 functioning functioning functioning ? halted (retained) halted (reset) dtc functioning medium-speed operation functioning halted (retained) halted (retained) halted (reset) pbc functioning medium-speed operation functioning halted (retained) halted (retained) halted (reset) tpu functioning functioning functioning halted (reset) ppg halted (retained) halted (retained) d/a0, 1 sci0 functioning functioning functioning halted (reset) halted (reset) halted (reset) sci1 sci2 pwm a/d ram functioning functioning functioning (dtc) functioning retained retained i/o functioning functioning functioning functioning retained high impedance hcan functioning functioning functioning halted (reset) halted (reset) halted (reset) note: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 953 of 1484 rej09b0103-0600 program-halted state program execution state sck2 to sck0 = 0 sck2 to sck0 0 sleep command sleep command external interrupt * all interrupt stby pin = high res pin = low stby pin = low ssby = 0, lson = 0 ssby = 1, pss = 0, lson = 0 res pin = high : transition after exception processing : low power dissipation mode reset state high-speed mode (main clock) medium-speed mode (main clock) hardware standby mode software standby mode sleep mode (main clock) note: when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. from any state, a transition to hardware standby mode occurs when stby is driven low. * nmi and irq0 to irq5 figure 23a-1 mode transition diagram
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 954 of 1484 rej09b0103-0600 table 23a.2 low power dissipation mode transition conditions status of control bit at transition pre-transition state ssby pss lson dton state after transition invoked by sleep command state after transition back from low power mode invoked by interrupt 0 * 0 * sleep high-speed/medium- speed 0 * 1 * ?? high-speed/ medium-speed 100 * software standby high-speed/medium- speed 101 * ?? 1100? ? 1110? ? 1101? ? 1111? ? subactive 0 0 ** ?? 010 * ?? 011 * ?? 10 ** ?? 1 1 0 0 ? high-speed 1110? ? 1 1 0 1 high-speed ? 1111? ? legend: * : don?t care ?: do not set
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 955 of 1484 rej09b0103-0600 23a.1.1 register configuration power-down modes are controlled by the sbycr, sckcr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 23a-3 summarizes these registers. table 23a-3 power-down mode registers name abbreviation r/w initial value address * 1 standby control register sbycr r/w h'58 h'fde4 system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec timer control/status register tcsr r/w h'00 h'ffa2 mstpcra r/w h'3f h'fde8 module stop control register a, b, c, d mstpcrb r/w h'ff h'fde9 mstpcrc r/w h'ff h'fdea mstpcrd r/w b'11 ****** h'fc60 note: 1. lower 16 bits of the address.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 956 of 1484 rej09b0103-0600 23a.2 register descriptions 23a.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 1 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ope 1 r/w 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit initial value r/w : : : sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'58 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?software standby (ssby): when making a low power dissipation mode transition by executing the sleep instruction, the operating mode is determined in combination with other control bits. note that the value of the ssby bit does not change even when shifting between modes using interrupts. bit 7 ssby description 0 shifts to sleep mode when the sl eep instruction is executed in high-speed mode or medium-speed mode. (initial value) 1 shifts to software standby mode when the sl eep instruction is executed in high- speed mode or medium-speed mode. bits 6 to 4?standby timer select 2 to 0 (sts2 to sts0): these bits select the mcu wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode. with a quartz osc illator (table 23a-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. with an external clock, select a standby time of 2 ms or more (pll oscillator settling time), based on the operating frequency.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 957 of 1484 rej09b0103-0600 bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states (initial value) 10reserved 1 standby time = 16 states (setting prohibited) bit 3?output port enable (ope): this bit specifies whether the output of the address bus and bus control signals ( as , rd , hwr , lwr ) is retained or set to high-impedance state in the software standby mode. bit 3 ope description 0 in software standby mode, address bus and bus control signals are high-impedance. 1 in software standby mode, the output state of the address bus and bus control signals is retained. (initial value) bits 2 to 0?reserved: these bits always return 0 when read, and cannot be written to. 23a.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 958 of 1484 rej09b0103-0600 bit 7? clock output disable (pstop): in combination with the ddr of the applicable port, this bit controls output. see section 23a.8, clock output disable function for details. description bit 7 pstop high-speed mode, medium-speed mode sleep mode software standby mode hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 to 4?reserved: these bits are always read as 0 and cannot be modified. bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten bits 2 to 0?system clock select (sck2 to sck0): these bits select the bus master clock in high-speed mode, and medium-speed mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1??
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 959 of 1484 rej09b0103-0600 23a.2.3 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit initial value r/w : : : the lpwrcr is an 8-bit read/write register that controls the low power dissipation modes. the lpwrcr is initialized to h'00 at a reset and when in hardware standby mode. it is not initialized in software standby mode. the following describes bits 7 to 2. for details of other bits, see section 22a.2.2, low-power control register (lpwrcr). bits 7 to 3?reserved: bits dton, lson, nesel, substp and rfcut must always be written with 0, as this version does not support subclock operation. bit 2?reserved: only write 0 to this bit. 23a.2.4 timer control/status register (tcsr) 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : note: * only write 0 to clear the flag. tcsr is an 8-bit read/write register that selects the clock input to wdt1 tcnt and the mode. here, we describe bit 4. for details of the other bits in this register, see section 12.2.2, timer control/status register (tcsr). the tcsr is initialized to h'00 at a reset and when in hardware standby mode. it is not initialized in software standby mode. bit 4?reserved: the pss bit must always be written with 0 since no subclock functions are available in versions other than the u-mask and w-mask versions.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 960 of 1484 rej09b0103-0600 23a.2.5 module stop control register (mstpcr) mstpcra bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrb bit:76543210 mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrc bit:76543210 mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrd bit:76543210 mstpd7 mstpd6 mstpd5 mstpd4 mstpd3 mstpd2 mstpd1 mstpd0 initial value : 1 1 undefined undefined undefined undefined undefined undefined r/w:r/wr/w?????? mstpcr, comprising four 8-bit readable/writable registers, performs module stop mode control. mstpcra to mstpcrc are initialized to h'3fffff by a reset and in hardware standby mode. mstpcrd is initialized to b'11****** by a reset and in hardware standby mode. they are not initialized in software standby mode.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 961 of 1484 rej09b0103-0600 mstpcra/mstpcrb/mstpcrc bits 7 to 0, mstpcrd bits 7 and 6?module stop (mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0, mstpd7 and mstpd6): these bits specify module stop mode. see table 23a-4 for the method of selecting the on-chip peripheral functions. mstpcra/mstpcrb/ mstpcrc bits 7 to 0, mstpcrd bits 7 and 6 mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0, mstpd7 and mstpd6 description 0 module stop mode is cleared (initial value of mstpa7 and mstpa6) 1 module stop mode is set (initial value of mstpa5?0, mstpb7?0, mstpc7?0, and mstpc7, 6)
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 962 of 1484 rej09b0103-0600 23a.3 medium-speed mode in high-speed mode, when the sck2 to sck0 bits in sckcr are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck2 to sck0 bits. the bus masters other than the cpu (dtc) also operate in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, and lson bit in lpwrcr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit = 1, lpwrcr lson bit = 0, and tcsr (wdt1) pss bit = 0, operation shifts to the software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 23a-2 shows the timing for transition to and clearance of medium-speed mode.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 963 of 1484 rej09b0103-0600 f , bus master clock supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 23a-2 medium-speed mode transition and clearance timing 23a.4 sleep mode 23a.4.1 sleep mode when the sleep instruction is executed when the sbycr ssby bit = 0 and the lpwrcr lson bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. 23a.4.2 exiting sleep mode sleep mode is exited by any interrupt, or signals at the res , or stby pins. exiting sleep mode by interrupts: when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. exiting sleep mode by res pin: setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high starts the cpu performing reset exception processing. exiting sleep mode by stby pin: when the stby pin level is driven low, a transition is made to hardware standby mode.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 964 of 1484 rej09b0103-0600 23a.5 module stop mode 23a.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 23a-4 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, motor control pwm, a/d converter and hcan are retained. after reset clearance, all modules other than dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 965 of 1484 rej09b0103-0600 table 23a-4 mstp bits and corresponding on-chip supporting modules register bit module mstpcra mstpa6 data transfer controller (dtc) mstpa5 16-bit timer pulse unit (tpu) mstpa3 programmable pulse generator (ppg) mstpa2 d/a converter (channel 0, 1) mstpa1 a/d converter mstpa0 * 1 mstpcrb mstpb7 serial communication interface 0 (sci0) mstpb6 serial communication interface 1 (sci1) mstpb5 serial communication interface 2 (sci2) mstpb4 * 2 mstpb3 * 2 mstpb0 * 1 mstpcrc mstpc4 pc break controller (pbc) mstpc3 hcan0 mstpc2 hcan1 mstpc1 * 1 mstpc0 * 1 mstpcrd mstpd7 motor control pwm (pwm) mstpd6 * 1 notes: 1. mstpa0, mstpb0 and mstpc1 to mstpc0 and mstpd6 are readable/writable bits with an initial value of 1. 2. the i 2 c bus interface is available as an option in the h8s/2638 and h8s/2630. in the h8s/2636, mstb4 and mstb3 are readable and writable bits that have 1 as their initial value. 23a.5.2 usage notes dtc module stop: depending on the operating status of the dtc, the mstpa7 and mstpa6 bits may not be set to 1. setting of the dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 8, data transfer controller (dtc).
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 966 of 1484 rej09b0103-0600 on-chip supporting module interrupt: relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode. writing to mstpcr: mstpcr should only be written to by the cpu. 23a.6 software standby mode 23a.6.1 software standby mode a transition is made to software standby mode when the sleep instruction is executed when the sbycr ssby bit = 1 and the lpwrcr lson bit = 0, and the tcsr (wdt1) pss bit = 0. in this mode, the cpu, on-chip supporting modules, and osc illator all stop. however, the contents of the cpu?s internal registers, ram data, and the states of on-chip supporting modules other than the sci, a/d converter, motor control, pwm, hcan and i/o ports, are retained. whether the address bus and bus control signals are placed in the high-impedance state. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 23a.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq5 ), or by means of the res pin or stby pin. ? clearing with an interrupt when an nmi or irq0 to irq5 interrupt request signal is input, clock osc illation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq5 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. ? clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are s upplied to the entire chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 967 of 1484 rej09b0103-0600 ? clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. 23a.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 23a-5 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 23a-5 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz unit 0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 1 0 reserved ? ??????s 1 16 states (setting prohibited) 0.8 1.0 1.3 1.6 2.0 2.6 4.0 : recommended time setting using a external clock: the pll circuit requires time to stabilize, so the standby time should be set to a value of 2 ms or more.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 968 of 1484 rej09b0103-0600 23a.6.4 software standby mode application example figure 23a-3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software sta ndby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator f nmi nmieg ssby nmi exception handling nmieg=1 ssby=1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 23a-3 software standby mode application example
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 969 of 1484 rej09b0103-0600 23a.6.5 usage notes i/o port status: in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. write data buffer function: the write data buffer function and software standby mode cannot be used at the same time. when the write data buffer function is used, the wdbe bit in bcrl should be cleared to 0 to cancel the write data buffer function before entering software standby mode. also check that external writes have finished, by reading external addresses, etc., before executing a sleep instruction to enter software standby mode. see section 7.7, write data buffer function, for details of the write data buffer function. 23a.7 hardware standby mode 23a.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md2 to md0) while the chip is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state.
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 970 of 1484 rej09b0103-0600 23a.7.2 hardware standby mode timing figure 23a-4 shows an example of hardware standby mode t iming. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator res stby oscillation stabilization time reset exception handling figure 23a-4 hardware standby mode timing
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 971 of 1484 rej09b0103-0600 23a.8 clock output disabling function output of the clock can be controlled by means of the pstop bit in sckcr, and ddr for the corresponding port. when the pstop bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. table 23a-6 shows the state of the pin in each processing state. using the on-chip pll circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference*. therefore, consideration should be given to these options when deciding on system board settings. note: * electromagnetic interference: emi (electro magnetic interference) table 23a-6 pin state in each processing state ddr 0 1 1 pstop ? 0 1 hardware standby mode high impedance high impedance high impedance software standby high impedance fixed high fixed high sleep mode high impedance output fixed high high-speed mode, medium-speed mode high impedance output fixed high
section 23a power-down modes [hd64f2636f, hd64f2638f, hd6432636f, hd6432638f, hd64f2630f, hd6432630f, hd64f2635f, hd6432635f, hd6432634f] rev. 6.00 feb 22, 2005 page 972 of 1484 rej09b0103-0600
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 973 of 1484 rej09b0103-0600 section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf, hd6432635f, hd64f2635f, hd6432634f] note: the dtc, pbc, ppb, and d/a converter are not implemented in the h8s/2635 and h8s/2634. 23b.1 overview in addition to the normal program execution state, the chip has nine power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting m odules, and so on. the chip operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) subactive mode * (u-mask, w-mask version, h8s/2635 group only) (4) sleep mode (5) subsleep mode * (u-mask, w-mask version, h8s/2635 group only) (6) watch mode * (u-mask, w-mask version, h8s/2635 group only) (7) module stop mode (8) software standby mode (9) hardware standby mode (2) to (9) are low power dissipation states. sleep mode and subsleep mode are cpu states, medium-speed mode is a cpu and bus master state, subactive mode is a cpu and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the cpu) state. some of these states can be combined.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 974 of 1484 rej09b0103-0600 after a reset, the lsi is in high-speed mode with modules other than the dtc in module stop mode. note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions. tables 23b-1 and 23b-2 show the internal state of the lsi in the respective modes. table 23b-3 shows the conditions for shifting between the low power dissipation modes. figure 23b-1 is a mode transition diagram.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 975 of 1484 rej09b0103-0600 table 23b-1 lsi internal states in each mode (h8s/2636, h8s/2638, h8s/2630) function high- speed medium- speed sleep module stop watch sub- active subsleep software standby hardware standby system clock pulse generator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock pulse generator function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 halted cpu instructions registers function- ing medium- speed operation halted (retained) high/ medium- speed operation halted (retained) subclock operation halted (retained) halted (retained) halted (undefined) nmi halted external interrupts irq0 to irq5 function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing peripheral functions wdt1 function- ing function- ing function- ing ? subclock operation subclock operation subclock operation halted (retained) halted (reset) wdt0 ? function- ing function- ing function- ing halted (retained) subclock operation subclock operation halted (retained) halted (reset) dtc function- ing medium- speed operation function- ing halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) pbc function- ing medium- speed operation function- ing halted (retained) halted (retained) subclock operation halted (retained) halted (retained) halted (reset) tpu iic0 * 2 function- ing function- ing function- ing halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) iic1 * 2 ppg d/a0, 1 sci0 sci1 function- ing function- ing function- ing halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) sci2 pwm a/d ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing retained retained high impedance hcan function- ing function- ing function- ing halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) notes: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. halted if the substp bit in lpwrcr is set to 1. 2. the i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. the product equipped with the i 2 c bus interface is the w-mask version.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 976 of 1484 rej09b0103-0600 table 23b-2 lsi internal states in each mode (h8s/2639 group, h8s/2635 group) function high- speed medium- speed sleep module stop watch sub- active subsleep software standby hardware standby system clock ( ) function- ing function- ing function- ing function- ing halted halted halted halted halted clock pulse generator function- ing function- ing function- ing function- ing function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 halted subclock ( sub) function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 function- ing * 1 halted cpu instructions registers function- ing medium- speed operation halted (retained) high/ medium- speed operation halted (retained) subclock operation halted (retained) halted (retained) halted (undefined) nmi halted external interrupts irq0 to irq5 function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing peripheral functions wdt1 function- ing function- ing function- ing ? subclock operation subclock operation subclock operation halted (retained) halted (reset) wdt0 ? function- ing function- ing function- ing halted (retained) subclock operation subclock operation halted (retained) halted (reset) dtc * 3 function- ing medium- speed operation function- ing halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) tpu iic0 * 2 function- ing function- ing function- ing halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) iic1 * 2 pbc * 3 ppg * 3 d/a0, 1 * 3 sci0 sci1 function- ing function- ing function- ing halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) sci2 pwm a/d ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing retained retained high impedance hcan function- ing function- ing function- ing halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) notes: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. halted if the substp bit in lpwrcr is set to 1. 2. the i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. the product equipped with the i 2 c bus interface is the w-mask version. 3. the dtc, pbc, ppg, da0, and da1 are not implemented in the h8s/2635 and h8s/2634.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 977 of 1484 rej09b0103-0600 program-halted state program execution state sck2 to sck0 = 0 sck2 to sck0 0 sleep command ssby = 1, pss = 1 dton = 1, lson = 1 clock switching exception processing sleep command ssby = 1, pss = 1 dton = 1, lson = 0 after the oscillation stabilization time (sts2 to 0), clock switching exception processing sleep command sleep command external interrupt * 3 all interrupt sleep command sleep command sleep command interrupt * 2 lson bit = 0 interrupt * 2 interrupt * 1 lson bit = 1 stby pin = high res pin = low stby pin = low ssby = 0, lson = 0 ssby = 1, pss = 0, lson = 0 ssby = 0, pss = 1, lson = 1 ssby = 1, pss = 1, dton = 0 res pin = high : transition after exception processing : low power dissipation mode reset state high-speed mode (main clock) medium-speed mode (main clock) sub-active mode (subclock) sub-sleep mode (subclock) hardware standby mode software standby mode sleep mode (main clock) watch mode (subclock) notes: when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. from any state, a transition to hardware standby mode occurs when stby is driven low. always select high-speed mode before making a transition to watch mode or subactive mode. 1. 2. 3. nmi, irq0 to irq5, and wdt1 interrupts nmi, irq0 to irq5, iwdt0 interrupts, and wdt1 interrupt. nmi and irq0 to irq5 figure 23b-1 mode transition diagram
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 978 of 1484 rej09b0103-0600 table 23b.3 low power dissipation mode transition conditions status of control bit at transition pre-transition state ssby pss lson dton state after transition invoked by sleep command state after transition back from low power mode invoked by interrupt 0 * 0 * sleep high-speed/medium- speed high-speed/ medium-speed 0 * 1 * ?? 100 * software standby high-speed/medium- speed 101 * ?? 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 1101? ? 1 1 1 1 subactive ? subactive 0 0 ** ?? 010 * ?? 011 * subsleep subactive 10 ** ?? 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 1 1 0 1 high-speed ? 1111? ? legend: * : don?t care ?: do not set
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 979 of 1484 rej09b0103-0600 23b.1.1 register configuration power-down modes are controlled by the sbycr, sckcr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 23b-4 summarizes these registers. table 23b-4 power-down mode registers name abbreviation r/w initial value address * 1 standby control register sbycr r/w h'58 h'fde4 system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec timer control/status register tcsr r/w h'00 h'ffa2 mstpcra r/w h'3f h'fde8 module stop control register a, b, c, d mstpcrb r/w h'ff h'fde9 mstpcrc r/w h'ff h'fdea mstpcrd r/w b'11 ****** h'fc60 note: 1. lower 16 bits of the address. 23b.2 register descriptions 23b.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 1 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ope 1 r/w 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit initial value r/w : : : sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'58 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?software standby (ssby): when making a low power dissipation mode transition by executing the sleep instruction, the operating mode is determined in combination with other control bits.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 980 of 1484 rej09b0103-0600 note that the value of the ssby bit does not change even when shifting between modes using interrupts. bit 7 ssby description 0 shifts to sleep mode when the sl eep instruction is executed in high-speed mode or medium-speed mode. shifts to subsleep mode when the sl eep instruction is executed in subactive mode. (initial value) 1 shifts to software standby mode, subactive mode, and watch mode when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to watch mode or high-speed mode when the sl eep instruction is executed in subactive mode. bits 6 to 4?standby timer select 2 to 0 (sts2 to sts0): these bits select the mcu wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or subactive mode. with a quartz oscillator (table 23b-6), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. with an external clock, select a standby time of 2 ms or more (pll oscillator settling time), based on the operating frequency. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states (initial value) 10reserved 1 standby time = 16 states (setting prohibited)
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 981 of 1484 rej09b0103-0600 bit 3?output port enable (ope): this bit specifies whether the output of the address bus and bus control signals ( as , rd , hwr , lwr ) is retained or set to high-impedance state in the software standby mode, watch mode, and when making a direct transition. bit 3 ope description 0 in software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. 1 in software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (initial value) bits 2 to 0?reserved: these bits always return 0 when read, and cannot be written to. 23b.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): in combination with the ddr of the applicable port, this bit controls output. see section 23b.12, clock output disable function for details. description bit 7 pstop high-speed mode, medium-speed mode, subactive mode sleep mode, subsleep mode software standby mode, watch mode, direct transition hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 982 of 1484 rej09b0103-0600 bits 6 to 4?reserved: these bits are always read as 0 and cannot be modified. bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten bits 2 to 0?system clock select (sck2 to sck0): these bits select the bus master clock in high-speed mode, medium-speed mode, and subactive mode. set sck2 to sck0 all to 0 when shifting to operation in watch mode or subactive mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1??
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 983 of 1484 rej09b0103-0600 23b.2.3 low-power control register (lpwrcr) 7 dton * 0 r/w 6 lson * 0 r/w 5 nesel * 0 r/w 4 substp * 0 r/w 3 rfcut * 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit initial value r/w : : : note: * bits 7 to 3 in lpwrcr are valid in the u-mask and w-mask versions, and h8s/2635 group; they are reserved bits in all other versions. see section 23a.2.3, low-power control register (lpwrcr), for more information. the lpwrcr is an 8-bit read/write register that controls the low power dissipation modes. the lpwrcr is initialized to h'00 at a reset and when in hardware standby mode. it is not initialized in software standby mode. the following describes bits 7 to 2. for details of other bits, see sections 22a.2.2, 22b.2.2, low-power control register (lpwrcr). bit 7?direct transition on flag (dton): when shifting to low power dissipation mode by executing the sleep instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the subactive modes. the selected operating mode after executing the sleep instruction is determined by the combination of other control bits. bit 7 dton description 0 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . ? when the sleep instruction is executed in s ubactive mode, operation shifts to subsleep mode or watch mode. (initial value) 1 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts directly to subactive mode * , or shifts to sleep mode or software standby mode. ? when the sleep instruction is executed in s ubactive mode, operation shifts directly to high-speed mode, or shifts to subsleep mode. note: * always set high-speed mode when shifting to watch mode or subactive mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 984 of 1484 rej09b0103-0600 bit 6?low-speed on flag (lson): when shifting to low power dissipation mode by executing the sleep instruction, this bit specifies the operating mode, in combination with other control bits. this bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. bit 6 lson description 0 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . ? when the sleep instruction is executed in s ubactive mode, operation shifts to watch mode or shifts directly to high-speed mode. ? operation shifts to high-speed mode when watch mode is cancelled. (initial value) 1 ? when the sleep instruction is executed in high-s peed mode, operation shifts to watch mode or subactive mode. ? when the sleep instruction is executed in s ubactive mode, operation shifts to subsleep mode or watch mode. ? operation shifts to subactive mode when watch mode is cancelled. note: * always set high-speed mode when shifting to watch mode or subactive mode. bit 5?noise elimination sampling frequency select (nesel): this bit selects the sampling frequency of the subclock ( sub) generated by the subclock oscillator is sampled by the clock ( ) generated by the system clock oscillator. set this bit to 0 when =5mhz or more. this setting is disabled in subactive mode, subsleep mode, and watch mode. bit 5 nesel d escription 0 sampling using 1/32 (initial value) 1 sampling using 1/4 bit 4?subclock enable (substp): this bit enables/disables subclock generation. bit 4 substp description 0 enables subclock generation (initial value) 1 disables subclock generation
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 985 of 1484 rej09b0103-0600 bit 3?oscillation circuit feedback resistance control bit (rfcut): this bit turns the internal feedback resistance of the main clock oscillation circuit on/off. bit 3 rfcut description 0 when the main clock is oscillating, sets the feedback resistance on. when the main clock is stopped, sets the feedback resistance off. (initial value) 1 sets the feedback resistance off. bit 2?reserved: only write 0 to this bit. 23b.2.4 timer control/status register (tcsr) 7 ovf 0 r/(w) * 1 6 wt/ it 0 r/w 5 tme 0 r/w 4 pss * 2 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : notes: 1. only write 0 to clear the flag. 2. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions, and h8s/2635 group. in versions other than the u-mask and w-mask versions, and h8s/2635 group, however, the pss bit must always be written with 0 since no subclock functions are available. tcsr is an 8-bit read/write register that selects the clock input to wdt1 tcnt and the mode. here, we describe bit 4. for details of the other bits in this register, see section 12.2.2, timer control/status register (tcsr). the tcsr is initialized to h'00 at a reset and when in hardware standby mode. it is not initialized in software standby mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 986 of 1484 rej09b0103-0600 bit 4?prescaler select (pss): this bit selects the clock source input to wdt1 tcnt. it also controls operation when shifting low power dissipation modes. the operating mode selected after the sleep instruction is executed is determined in combination with other control bits. for details, see the description for clock selection in section 12.2.2, timer control/status register (tcsr), and this section. bit 4 pss description 0 ? tcnt counts the divided clock from the -based prescaler (psm). ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (initial value) 1 ? tcnt counts the divided clock from the subclock-based prescaler (pss). ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, watch mode * 1 * 2 , or subactive mode * 1 * 2 . ? when the sleep instruction is executed in s ubactive mode * 2 , operation shifts to subsleep mode * 2 , watch mode * 2 , or high-speed mode. notes: 1. always set high-speed mode when shifting to watch mode or subactive mode. 2. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions, and h8s/2635 group. in versions other than the u-mask and w-mask versions, and h8s/2635 group, however, the pss bit must always be written with 0 since no subclock functions are available.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 987 of 1484 rej09b0103-0600 23b.2.5 module stop control register (mstpcr) mstpcra bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrb bit:76543210 mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrc bit:76543210 mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrd bit:76543210 mstpd7 mstpd6 mstpd5 mstpd4 mstpd3 mstpd2 mstpd1 mstpd0 initial value : 1 1 undefined undefined undefined undefined undefined undefined r/w:r/wr/w?????? mstpcr, comprising four 8-bit readable/writable registers, performs module stop mode control. mstpcra to mstpcrc are initialized to h'3fffff by a reset and in hardware standby mode. mstpcrd is initialized to b'11****** by a reset and in hardware standby mode. they are not initialized in software standby mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 988 of 1484 rej09b0103-0600 mstpcra/mstpcrb/mstpcrc bits 7 to 0, mstpcrd bits 7 and 6?module stop (mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0, mstpd7 and mstpd6): these bits specify module stop mode. see table 23b-5 for the method of selecting the on-chip peripheral functions. mstpcra/mstpcrb/ mstpcrc bits 7 to 0, mstpcrd bits 7 and 6 mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0, mstpd7 and mstpd6 description 0 module stop mode is cleared (initial value of mstpa7 and mstpa6) 1 module stop mode is set (initial value of mstpa5?0, mstpb7?0, mstpc7?0, and mstpc7, 6) 23b.3 medium-speed mode in high-speed mode, when the sck2 to sck0 bits in sckcr are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck2 to sck0 bits. the bus masters other than the cpu (dtc) also operate in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, and lson bit in lpwrcr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit = 1, lpwrcr lson bit = 0, and tcsr (wdt1) pss bit = 0, operation shifts to the software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 989 of 1484 rej09b0103-0600 when the res pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 23b-2 shows the timing for transition to and clearance of medium-speed mode. f , bus master clock supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 23b-2 medium-speed mode transition and clearance timing 23b.4 sleep mode 23b.4.1 sleep mode when the sleep instruction is executed when the sbycr ssby bit = 0 and the lpwrcr lson bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. 23b.4.2 exiting sleep mode sleep mode is exited by any interrupt, or signals at the res , or stby pins. exiting sleep mode by interrupts: when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 990 of 1484 rej09b0103-0600 exiting sleep mode by res pin: setting the res pin level low selects the reset state. after the stipulated reset input duration, driving the res pin high starts the cpu performing reset exception processing. exiting sleep mode by stby pin: when the stby pin level is driven low, a transition is made to hardware standby mode. 23b.5 module stop mode 23b.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 23b-5 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, motor control pwm, a/d converter and hcan are retained. after reset clearance, all modules other than dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 991 of 1484 rej09b0103-0600 table 23b-5 mstp bits and corresponding on-chip supporting modules register bit module mstpcra mstpa6 data transfer controller (dtc) * 3 mstpa5 16-bit timer pulse unit (tpu) mstpa3 programmable pulse generator (ppg) * 3 mstpa2 d/a converter (channel 0, 1) * 3 mstpa1 a/d converter mstpa0 * 1 mstpcrb mstpb7 serial communication interface 0 (sci0) mstpb6 serial communication interface 1 (sci1) mstpb5 serial communication interface 2 (sci2) mstpb4 i 2 c bus interface 0 (iic0) * 2 mstpb3 i 2 c bus interface 1 (iic1) * 2 mstpb0 * 1 mstpcrc mstpc4 pc break controller (pbc) * 3 mstpc3 hcan0 mstpc2 hcan1 * 3 mstpc1 * 1 mstpc0 * 1 mstpcrd mstpd7 motor control pwm (pwm) mstpd6 * 1 notes: 1. mstpa0, mstpb0 and mstpc1 to mstpc0 and mstpd6 are readable/writable bits with an initial value of 1. 2. the i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, and h8s/2630. the product equipped with the i 2 c bus interface is the w-mask version. when this optional feature is not used or in h8s/2636, mstb4 and mstb3 are readable and writable bits that have 1 as their initial value. 3. the dtc, ppg, d/a converter, pbc, and hcan1 are not implemented in the h8s/2635 and h8s/2634. mstpa6, mstpa3, mstpa2, mstpc4, and mstpc2 are readable/writable bits, but only 1 should be written to them.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 992 of 1484 rej09b0103-0600 23b.5.2 usage notes note: the dtc is not implemented in the h8s/2635 group. dtc module stop: depending on the operating status of the dtc, the mstpa7 and mstpa6 bits may not be set to 1. setting of the dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 8, data transfer controller (dtc). on-chip supporting module interrupt: relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode. writing to mstpcr: mstpcr should only be written to by the cpu. 23b.6 software standby mode 23b.6.1 software standby mode a transition is made to software standby mode when the sleep instruction is executed when the sbycr ssby bit = 1 and the lpwrcr lson bit = 0, and the tcsr (wdt1) pss bit = 0. in this mode, the cpu, on-chip supporting modules, and osc illator all stop * . however, the contents of the cpu?s internal registers, ram data, and the states of on-chip supporting modules other than the sci, a/d converter, motor control pwm, hcan and i/o ports, are retained. whether the address bus and bus control signals are placed in the high-impedance state. in this mode the oscillator stops * , and therefore power dissipation is significantly reduced. note: * the subclock ( sub) operates if the substp bit in lpwrcr is set to 0.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 993 of 1484 rej09b0103-0600 23b.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq5 ), or by means of the res pin or stby pin. ? clearing with an interrupt when an nmi or irq0 to irq5 interrupt request signal is input, clock osc illation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq5 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. ? clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are s upplied to the entire chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. ? clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. 23b.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: 1. setting for h8s/2636, h8s/2638, h8s/2639, h8s/2630 set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 23b-6 shows the standby times for different operating frequencies and settings of bits sts2 to sts0.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 994 of 1484 rej09b0103-0600 table 23b-6 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 5 mhz 4 mhz unit 0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 1.6 2.0 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 3.2 4.1 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 6.5 8.2 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 13.1 16.4 1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 26.2 32.8 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 52.4 65.6 1 0 reserved ????????s 1 16 states (setting prohibited) 0.8 1.0 1.3 1.6 2.0 2.6 3.2 4.0 : recommended time setting 2. setting for h8s/2635, h8s/2634 set bits sts2 to sts0 so that the standby time is at least 12 ms (the oscillation stabilization time). table 23b-7 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 23b-7 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz unit 0 0 0 8192 states 0.41 0.51 0.8 1.0 1.6 2.0 ms 1 16384 states 0.82 1.0 1.6 2.0 3.2 4.1 1 0 32768 states 1.6 2.0 3.3 4.1 6.5 8.2 1 65536 states 3.3 4.1 6.6 8.2 13.1 16.4 1 0 0 131072 states 6.6 8.2 13.1 16.4 26.2 32.8 1 262144 states 13.1 16.4 26.2 32.8 52.4 65.6 1 0 reserved ??????s 1 16 states (setting prohibited) 0.8 1.0 1.6 2.0 3.2 4.0 : recommended time setting
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 995 of 1484 rej09b0103-0600 using an external clock: the pll circuit requires time to stabilize, so the standby time should be set to a value of 2 ms or more. 23b.6.4 software standby mode application example figure 23b-3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software sta ndby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator f nmi nmieg ssby nmi exception handling nmieg=1 ssby=1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 23b-3 software standby mode application example
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 996 of 1484 rej09b0103-0600 23b.6.5 usage notes i/o port status: in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. write data buffer function: the write data buffer function and software standby mode cannot be used at the same time. when the write data buffer function is used, the wdbe bit in bcrl should be cleared to 0 to cancel the write data buffer function before entering software standby mode. also check that external writes have finished, by reading external addresses, etc., before executing a sleep instruction to enter software standby mode. see section 7.9, write data buffer function, for details of the write data buffer function. 23b.7 hardware standby mode 23b.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md2 to md0) while the chip is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 997 of 1484 rej09b0103-0600 23b.7.2 hardware standby mode timing figure 23b-4 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator res stby oscillation stabilization time reset exception handling figure 23b-4 hardware standby mode timing 23b.8 watch mode (u-mask, w-mask version, h8s/2635 group only) 23b.8.1 watch mode cpu operation makes a transition to watch mode when the sleep instruction is executed in high- speed mode or subactive mode with sbycr ssby=1, lpwrcr dton = 0, and tcsr (wdt1) pss = 1. in watch mode, the cpu is stopped and supporting modules other than wdt1 are also stopped. the contents of the cpu?s internal registers, the data in internal ram, and the statuses of the internal supporting modules (excluding the sci, adc, hcan, and motor control pwm) and i/o ports are retained.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 998 of 1484 rej09b0103-0600 23b.8.2 exiting watch mode watch mode is exited by any interrupt (wovi interrupt, nmi pin, or irq0 to irq5 ), or signals at the res , or stby pins. (1) exiting watch mode by interrupts when an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the lpwrcr lson bit = 0 or to subactive mode when the lson bit = 1. when a transition is made to high-speed mode, a stable clock is supplied to all lsi circuits and interrupt exception processing starts after the time set in sbycr sts2 to sts0 has elapsed. in the case of irq0 to irq5 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu. see section 23b.6.3, setting osc illation stabilization time after clearing software standby mode for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. (2) exiting watch mode by res pins for exiting watch mode by the res pins, see, clearing with the res pins in section 23b.6.2, clearing software standby mode. (3) exiting watch mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. 23b.8.3 notes (1) i/o port status the status of the i/o ports is retained in watch mode. also, when the ope bit is set to 1, the address bus and bus control signals continue to be output. therefore, when a high level is output, the current consumption is not diminished by the amount of current to support the high level output. (2) current consumption when waiting for oscillation stabilization the current consumption increases during stabilization of oscillation.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 999 of 1484 rej09b0103-0600 23b.9 subsleep mode (u-mask, w-mask version, h8s/2635 group only) 23b.9.1 subsleep mode when the sleep instruction is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr (wdt1) pss bit = 1, cpu operation shifts to subsleep mode. in subsleep mode, the cpu is stopped. supporting modules other than wdt0, and wdt1 are also stopped. the contents of the cpu?s internal registers, the data in internal ram, and the statuses of the internal supporting modules (excluding the sci, adc, hcan, and motor control pwm) and i/o ports are retained. 23b.9.2 exiting subsleep mode subsleep mode is exited by an interrupt (interrupts from internal supporting modules, nmi pin, or irq0 to irq5 ), or signals at the res or stby pins. (1) exiting subsleep mode by interrupts when an interrupt occurs, subsleep mode is exited and interrupt exception processing starts. in the case of irq0 to irq5 interrupts, subsleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu. (2) exiting subsleep mode by res for exiting subsleep mode by the res pins, see, clearing with the res pins in section 23b.6.2, clearing software standby mode. (3) exiting subsleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 1000 of 1484 rej09b0103-0600 23b.10 subactive mode (u-mask, w-mask version, h8s/2635 group only) 23b.10.1 subactive mode when the sleep instruction is executed in high-speed mode with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 1, and tcsr (wdt1) pss bit = 1, cpu operation shifts to subactive mode. when an interrupt occurs in watch mode, and if the lson bit of lpwrcr is 1, a transition is made to subactive mode. and if an interrupt occurs in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu operates at low speed on the subclock, and the program is executed step by step. supporting modules other than wdt0, and wdt1 are also stopped. when operating the cpu in subactive mode, the sckcr sck2 to sck0 bits must be set to 0. 23b.10.2 exiting subactive mode subactive mode is exited by the sleep instruction or the res or stby pins. (1) exiting subactive mode by sleep instruction when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 0, and tcsr (wdt1) pss bit = 1, the cpu exits subactive mode and a transition is made to watch mode. when the sleep instruction is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr (wdt1) pss bit = 1, a transition is made to subsleep mode. finally, when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 0, and tcsr (wdt1) pss bit = 1, a direct transition is made to high-speed mode (sck0 to sck2 all 0). see section 23b.11, direct transitions for details of direct transitions. (2) exiting subactive mode by res pins for exiting subactive mode by the res pins, see, claering with the res pins in section 23b.6.2, clearing software standby mode. (3) exiting subactive mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 1001 of 1484 rej09b0103-0600 23b.11 direct transitions (u-mask, w-mask version, h8s/2635 group only) 23b.11.1 overview of direct transitions there are three modes, high-speed, medium-speed, and subactive, in which the cpu executes programs. when a direct transition is made, there is no interruption of program execution when shifting between high-speed and subactive modes. direct transitions are enabled by setting the lpwrcr dton bit to 1, then executing the sleep instruction. after a transition, direct transition interrupt exception processing starts. (1) direct transitions from high-speed mode to subactive mode execute the sleep instruction in high-speed mode when the sbycr ssby bit = 1, lpwrcr lson bit = 1, and dton bit = 1, and tscr (wdt1) pss bit = 1 to make a transition to subactive mode. (2) direct transitions from subactive mode to high-speed mode execute the sleep instruction in subactive mode when the sbycr ssby bit = 1, lpwrcr lson bit = 0, and dton bit = 1, and tscr (wdt1) pss bit = 1 to make a direct transition to high-speed mode after the time set in sbycr sts2 to sts0 has elapsed.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 1002 of 1484 rej09b0103-0600 23b.12 clock output disabling function output of the clock can be controlled by means of the pstop bit in sckcr, and ddr for the corresponding port. when the pstop bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. table 23b-8 shows the state of the pin in each processing state. using the on-chip pll circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference*. therefore, consideration should be given to these options when deciding on system board settings. note: * electromagnetic interference: emi (electro magnetic interference) table 23b-8 pin state in each processing state ddr 0 1 1 pstop ? 0 1 hardware standby mode high impedance high impedance high impedance software standby mode, watch mode * , and direct transition high impedance fixed high fixed high sleep mode and subsleep mode * high impedance output fixed high high-speed mode, medium-speed mode, and subactive mode * high impedance output fixed high subactive mode high impedance sub output fixed high note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 1003 of 1484 rej09b0103-0600 23b.13 usage notes 1. when making a transition to subactive mode or watch mode, set the dtc to enter module stop mode (write 1 to the relevant bits in mstpcr), and then read the relevant bits to confirm that they are set to 1 before mode transition. do not clear module stop mode (write 0 to the relevant bits in mstpcr) until a transition from subactive mode to high-speed mode or medium-speed mode has been performed. if a dtc activation source occurs in subactive mode, the dtc will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. the on-chip peripheral modules (dtc and tpu) which halt operation in subactive mode cannot clear an interrupt in subactive mode. therefore, if a transition is made to subactive mode while an interrupt is requested, the cpu interrupt source cannot be cleared. disable the interrupts of each on-chip peripheral module before executing a sleep instruction to enter subactive mode or watch mode. 3. a 1 is always returned when an attempt is made to read the pin status of i/o ports 1, 4, 9, or f during operation in subactive mode. (in the case of port 1, pins 13 to 10 are readable.) in addition, the ports may be used as output ports (except for ports 4 and 9). the procedure for determining the pin status during operation in subactive mode is as follows. [1] use ports 3, a, b, c, d, e, h, and j as input ports. [2] use external interrupt inputs (irq0 to irq5). (if the level sense setting has been selected for the irq pins, an interrupt request is generated by a low-level input.) 4. operation cannot be guaranteed if a transition is made to the subactive mode, subsleep mode, or watch mode when the substp bit in lpwrcr is set to 1 (subclock generation prohibited). to prevent problems, it should be confirmed that the substp bit has been cleared to 0 before transitioning to the subactive mode, subsleep mode, or watch mode. 5. (h8s/2639 group, h8s/2635 group only) the subclock ( sub) is frequency divided internally, so the clock oscillator does not halt even if a transition to the software sta ndby mode occurs when the substp bit in lpwrcr is cleared to 0. the substp bit in lpwrcr should be set to 1 before transitioning to the software standby mode.
section 23b power-down modes [hd64f2636uf, hd6432636uf, hd64f2638uf, hd6432638uf, hd64f2638wf, hd6432638wf, hd64f2639uf, hd6432639uf, hd64f2639wf, hd6432639wf, hd64f2630uf, hd6432630uf, hd64f2630wf, hd6432630wf] rev. 6.00 feb 22, 2005 page 1004 of 1484 rej09b0103-0600
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1005 of 1484 rej09b0103-0600 section 24 electrical characteristics 24.1 h8s/2636 group electrical characteristics 24.1.1 absolute maximum ratings table 24-1 lists the absolute maximum ratings. table 24-1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (osc1, osc2) v in ?0.3 +4.3 v input voltage (xtal, extal) v in ?0.3 to v cc +0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (ports h and j) v in ?0.3 to pwmv cc +0.3 v input voltage (except xtal, extal, osc1, osc2, ports 4, 9, h and j) v in ?0.3 to v cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1006 of 1484 rej09b0103-0600 24.1.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-1. 24 20 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 frequency (mhz) frequency (mhz) power supply voltage (v) power supply voltage (v) operating range of high-speed, medium-speed and sleep modes 32.768 0 3 3.5 4 4.5 5 5.5 6 operating range of watch * , sub-active * and sub-sleep * modes note: * the watch, subactive, and subsleep modes are available in the u-mask version only. figure 24-1 power supply voltage and operating ranges
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1007 of 1484 rej09b0103-0600 24.1.3 dc characteristics table 24-2 lists the dc characteristics. table 24-3 lists the permissible output currents. table 24-2 dc characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 * 6 item symbol min. typ. max. unit test conditions irq0 to irq5 v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? input high voltage res , stby , nmi, fwe, md2 to md0 v ih v cc ? 0.7 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 ports 1, 3, f 2.2 ? v cc + 0.3 ports a to e v cc 0.8 ? v cc + 0.3 ports h, j pwmv cc 0.8 ?pwmv cc + 0.3 hrxd0, hrxd1 2.2 ? v cc + 0.3 ports 4 and 9 av cc 0.7 ? av cc + 0.3 input low voltage res , stby , nmi, fwe, md2 to md0 v il ?0.3 ? 0.5 v extal ?0.3 ? 0.8 ports 1, 3, f ?0.3 ? 0.8 ports a to e ?0.3 ? v cc 0.2 ports h, j ?0.3 ? pwmv cc 0.2 hrxd0, hrxd1 ?0.3 ? v cc 0.2 ports 4, 9 ?0.3 ? av cc 0.2
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1008 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions output high voltage ports 1, 3, a to f, h,j htxd0, htxd1 v oh v cc ? 0.5 3.5 ? ? ? ? vi oh = ?200 a i oh = ?1 ma pwm1a to pwm1h, pwm2a to pwm2h pwmv cc ? 0.5 ?i oh = ?15 ma output low voltage all output pins except pwm1a to pwm1h, pwm2a to pwm2h v ol ??0.4vi ol = 1.6 ma pwm1a to pwm1h, pwm2a to pwm2h ??0.5vi ol = 15 ma res | i in |? ?1.0 a input leakage current stby , nmi , md2 to md0 ??1.0 v in =0.5 v to v cc ? 0.5 v hrxd0, hrxd1, fwe ??1.0 ports 4, 9 ? ? 1.0 v in = 0.5 v to av cc ? 0.5 v three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 ? i tsi ? ?1.0 av in = 0.5 v to v cc ? 0.5 v mos input pull-up current ports a to e ?i p 50 300 av in = 0 v res c in ? ? 30 pf input capacitance nmi ? ? 30 all input pins except res and nmi ??15 v in = 0 v f = 1 mhz t a = 25c
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1009 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions current dissipation * 2 normal operation i cc * 4 ? 75 90 ma f = 20 mhz sleep mode ? 65 80 all modules stopped ?57 ? ma f = 20 mhz (reference value) medium- speed mode ( /32) ?49 ? subactive mode * 5 ? 130 220 a using 32.768 khz crystal resonator subsleep mode * 5 ? 80 160 watch mode * 5 ?30 60 ?2.0 5.0 at a 50c standby mode * 3 ? ? 20 50c < t a analog power supply current during a/d and d/a conversion al cc ?1.0 2.0 maav cc = 5.0 v idle ? 0.1 5.0 a reference current during a/d and d/a conversion al cc ?4.0 5.0 mav ref = 5.0 v idle ? 0.1 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih (min.) = v cc ? 0.5 v, v il (max.) = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc 0.9, and v il (max.) = 0.3 v. 4. i cc depends on v cc and f as follows: i cc (max.) = 30 (ma) + 0.54 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 30 (ma) + 0.45 (ma/(mhz v)) v cc f (sleep mode) 5. the watch, subactive, and subsleep modes are available in the u-mask version only. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 6. if the motor-control pwm timer is not used, do not leave the pmwv cc , or pmwv ss pins open. if the motor-control pwm timer is not used, apply a voltage of between 4.5 and 5.5 v to the pwmv cc pin, for instance, by connecting it to v cc .
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1010 of 1484 rej09b0103-0600 table 24-3 permissible output currents conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test condition all output pins except pwm1a to pwm1h, pwm2a to pwm2h i ol ??10ma permissible output low current (per pin) i ol ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output low current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h i ol ??80ma i ol ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c all output pins except pwm1a to pwm1h, pwm2a to pwm2h ?i oh ??2.0ma permissible output high current (per pin) ?i oh ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output high current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h ?i oh ??40ma ?i oh ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c note: to protect chip reliability, do not exceed the output current values in table 24-3.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1011 of 1484 rej09b0103-0600 24.1.4 ac characteristics figure 24-2 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 50 pf: ports 10 to 13, a to f (in case of expansion bus control signal output pin setting) c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? input/output timing measurement levels ? low level: 0.8 v ? high level: 2.0 v figure 24-2 output load circuit
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1012 of 1484 rej09b0103-0600 (1) clock timing table 24-4 lists the clock timing table 24-4 clock timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition 20mhz item symbol min. max. unit test conditions clock cycle time t cyc 50 250 ns figure 24-9 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rise time t cr ?10ns clock fall time t cf ?10ns clock oscillator settling time at reset (crystal) t osc1 20 ? ms figure 24-10 clock oscillator settling time in software standby (crystal) t osc2 8 ? ms figure 23a-3 figure 23b-3 external clock output stabilization delay time t dext 2 ? ms figure 24-10 32-khz clock oscillation settling time t osc3 ?2s subclock oscillator frequency f sub 32.768 khz subclock ( sub ) cycle time t sub 30.5 s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1013 of 1484 rej09b0103-0600 (2) control signal timing table 24-5 lists the control signal timing. table 24-5 control signal timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 24-11 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 24-12 nmi hold time t nmih 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1014 of 1484 rej09b0103-0600 (3) bus timing table 24-6 lists the bus timing. table 24-6 bus timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions address delay time t ad ?35ns address setup time t as 0.5 t cyc ? 20 ?ns figure 24-13 to figure 24-17 address hold time t ah 0.5 t cyc ? 15 ?ns as delay time t asd ?20ns rd delay time 1 t rsd1 ?20ns rd delay time 2 t rsd2 ?20ns read data setup time t rds 20 ? ns read data hold time t rdh 0?ns read data access time1 t acc1 ? 1.0 t cyc ? 48 ns read data access time2 t acc2 ? 1.5 t cyc ? 45 ns read data access time3 t acc3 ? 2.0 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 45 ns read data access time 5 t acc5 ? 3.0 t cyc ? 50 ns wr delay time 1 t wrd1 ?20ns wr delay time 2 t wrd2 ?20ns wr pulse width 1 t wsw1 1.0 t cyc ? 20 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 20 ? ns write data delay time t wdd ?30ns write data setup time t wds 0.5 t cyc ? 20 ? ns write data hold time t wdh 0.5 t cyc ? 10 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1015 of 1484 rej09b0103-0600 (4) timing of on-chip supporting modules table 24-7 lists the timing of on-chip s upporting modules. table 24-7 timing of on-chip supporting modules conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions i/o port output data delay time t pw d ?50ns output data delay time 2 t pw d2 ?50 figure 24-18 figure 24-19 input data setup time t prs 30 ? input data hold time t prh 30 ? ppg pulse output delay time t pod ? 50 ns figure 24-20 tpu timer output delay time t tocd ? 50 ns figure 24-21 timer input setup time t tics 30 ? timer clock input setup time t tcks 30 ? ns figure 24-22 single edge t tckwh 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? pwm pulse output delay time t mpw mod ? 50 ns figure 24-23 sci asynchronous t scyc 4?t cyc figure 24-24 input clock cycle synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?1.5t cyc input clock fall time t sckf ?1.5 transmit data delay time t txd ? 50 ns figure 24-25 receive data setup time (synchronous) t rxs 50 ? receive data hold time (synchronous) t rxh 50 ? a/d converter trigger input setup time t trgs 50 ? ns figure 24-26
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1016 of 1484 rej09b0103-0600 condition item symbol min. max. unit test conditions hcan * transmit data delay time t htxd ? 100 ns figure 24-27 receive data setup time t hrxs 100 ? receive data hold time t hrxh 100 ? note: * the hcan input signal is asynchronous. however, its state is judged to have changed at the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. the hcan output signal is also asynchronous. its state changes based on the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. 24.1.5 a/d conversion characteristics table 24-8 lists the a/d conversion characteristics. table 24-8 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? ? s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k ? nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1017 of 1484 rej09b0103-0600 24.1.6 d/a conversion characteristics table 24-9 shows the d/a conversion characteristics. table 24-9 d/a conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit test conditions resolution 888bits conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 1.5 2.0 lsb 2-m ? resistive load ? ? 1.5 lsb 4-m ? resistive load
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1018 of 1484 rej09b0103-0600 24.1.7 flash memory characteristics table 24-10 shows the flash memory characteristics. table 24-10 flash memory characteristics conditions: v cc =4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss , av ss = 0 v t a = 0 to +75c (programming/erasing operating temperature range: regular specification) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ?10200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 11?s wait time after psu bit setting * 1 t spsu 50 50 ? s wait time after p bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 55?s wait time after psu bit clear * 1 t cpsu 55?s wait time after pv bit setting * 1 t spv 44?s wait time after h'ff dummy write * 1 t spvr 22?s wait time after pv bit clear * 1 t cpv 22?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1 * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 11?s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1019 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test condition erase wait time after h'ff dummy write * 1 t sevr 22?s wait time after ev bit clear * 1 t cev 44?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times notes: 1. make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time) 4. to specify the maximum programming time value (t p (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n)= 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max.), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 [ms], n = 12 times when t se = 10 [ms], n = 120 times
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1020 of 1484 rej09b0103-0600 24.2 h8s/2638 group electrical characteristics 24.2.1 absolute maximum ratings table 24-11 lists the absolute maximum ratings. table 24-11 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (osc1, osc2) v in ?0.3 +4.3 v input voltage (xtal, extal) v in ?0.3 to v cc +0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (ports h and j) v in ?0.3 to pwmv cc +0.3 v input voltage (except xtal, extal, osc1, osc2, ports 4, 9, h and j) v in ?0.3 to v cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1021 of 1484 rej09b0103-0600 24.2.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-3. 24 20 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 frequency (mhz) frequency (mhz) power supply voltage (v) power supply voltage (v) operating range of high-speed, medium-speed and sleep modes 32.768 0 3 3.5 4 4.5 5 5.5 6 operating range of watch * , sub-active * and sub-sleep * modes note: * the watch, subactive, and subsleep modes are available in the u-mask and w-mask versions only. figure 24-3 power supply voltage and operating ranges
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1022 of 1484 rej09b0103-0600 24.2.3 dc characteristics table 24-12 lists the dc characteristics. table 24-13 lists the permissible output currents. table 24-12 dc characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 * 6 item symbol min. typ. max. unit test conditions irq0 to irq5 v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? input high voltage res , stby , nmi, fwe, md2 to md0 v ih v cc ? 0.7 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 ports 1, 3, f 2.2 ? v cc + 0.3 ports a to e v cc 0.8 ? v cc + 0.3 ports h, j pwmv cc 0.8 ?pwmv cc + 0.3 hrxd0, hrxd1 2.2 ? v cc + 0.3 ports 4 and 9 av cc 0.7 ? av cc + 0.3 input low voltage res , stby , nmi, fwe, md2 to md0 v il ?0.3 ? 0.5 v extal ?0.3 ? 0.8 ports 1, 3, f ?0.3 ? 0.8 ports a to e ?0.3 ? v cc 0.2 ports h, j ?0.3 ? pwmv cc 0.2 hrxd0, hrxd1 ?0.3 ? v cc 0.2 ports 4, 9 ?0.3 ? av cc 0.2
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1023 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions output high voltage ports 1, 3, a to f, h,j htxd0, htxd1 (excluding p34 and p35 * 7 ) v oh v cc ? 0.5 ? ? v i oh = ?200 a p34, p35 * 7 v cc ? 2.5 ? ? i oh = ?100 a ports 1, 3, a to f, h, j htxd0, htxd1 (excluding p34 and p35 * 7 ) 3.5 ? ? i oh = ?1 ma pwm1a to pwm1h, pwm2a to pwm2h pwmv cc ? 0.5 ?i oh = ?15 ma output low voltage all output pins except pwm1a to pwm1h, pwm2a to pwm2h v ol ??0.4vi ol = 1.6 ma pwm1a to pwm1h, pwm2a to pwm2h ??0.5vi ol = 15 ma res | i in |? ?1.0 a input leakage current stby , nmi , md2 to md0 ??1.0 v in = 0.5 v to v cc ? 0.5 v hrxd0, hrxd1, fwe ??1.0 ports 4, 9 ? ? 1.0 v in = 0.5 v to av cc ? 0.5 v three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 ? i tsi ? ?1.0 av in = 0.5 v to v cc ? 0.5 v
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1024 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions mos input pull-up current ports a to e ?i p 50 300 av in = 0 v res c in ? ? 30 pf input capacitance nmi ? ? 30 all input pins except res and nmi ??15 v in = 0 v f = 1 mhz t a = 25c current dissipation * 2 normal operation i cc * 4 ? 75 90 ma f = 20 mhz sleep mode ? 65 80 all modules stopped ?57? ma f = 20 mhz (reference value) medium- speed mode ( /32) ?49? subactive mode * 5 ? 130 220 a using 32.768 khz crystal resonator subsleep mode * 5 ? 80 160 watch mode * 5 ?3060 ?2.05.0 at a 50c standby mode * 3 ? ? 20 50c < t a analog power supply current during a/d and d/a conversion al cc ?1.02.0 maav cc = 5.0 v idle ? 0.1 5.0 a reference current during a/d and d/a conversion al cc ?4.05.0 mav ref = 5.0 v idle ? 0.1 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih (min.) = v cc ? 0.5 v, v il (max.) = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc 0.9, and v il (max.) = 0.3 v.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1025 of 1484 rej09b0103-0600 4. i cc depends on v cc and f as follows: i cc (max.) = 30 (ma) + 0.54 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 30 (ma) + 0.45 (ma/(mhz v)) v cc f (sleep mode) 5. the watch, subactive, and subsleep modes are available in the u-mask and w-mask versions only. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 6. if the motor-control pwm timer is not used, do not leave the pmwv cc , or pmwv ss pins open. if the motor-control pwm timer is not used, apply a voltage of between 4.5 and 5.5 v to the pwmv cc pin, for instance, by connecting it to v cc . 7. the characteristics of pins 34 and 35 apply to the w-mask version.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1026 of 1484 rej09b0103-0600 table 24-13 permissible output currents conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test condition all output pins except pwm1a to pwm1h, pwm2a to pwm2h i ol ??10ma permissible output low current (per pin) i ol ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output low current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h i ol ??80ma i ol ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c all output pins except pwm1a to pwm1h, pwm2a to pwm2h ?i oh ??2.0ma permissible output high current (per pin) ?i oh ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output high current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h ? i oh ??40ma ? i oh ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c note: to protect chip reliability, do not exceed the output current values in table 24-13.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1027 of 1484 rej09b0103-0600 table 24-14 bus drive characteristics [option] * conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) applicable pins: scl1-0, sda1-0 item symbol min. typ. max. unit test conditions v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? v cc = 4.5 v to 5.5 v input high voltage v ih ? v cc 0.7 ? v cc + 0.5 v input low voltage v il ? 0.5 ? v cc 0.3 v output low voltage v ol ??0.7vi ol = 8 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 3 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 1.6 ma, v cc = 3.3 v to 5.5 v input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25 c three-state leakage current (off state) ? i tsi ? ??1.0 a v in = 0.5 v to v cc ? 5.5 v scl, sda, output fall time t of 20 + 0.1cb ? 250 ns note: * available when using i 2 c bus interface (the w-mask version only).
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1028 of 1484 rej09b0103-0600 24.2.4 ac characteristics figure 24-4 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 50 pf: ports 10 to 13, a to f (in case of expansion bus control signal output pin setting) c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? input/output timing measurement levels ? low level: 0.8 v ? high level: 2.0 v figure 24-4 output load circuit
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1029 of 1484 rej09b0103-0600 (1) clock timing table 24-15 lists the clock timing table 24-15 clock timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition 20mhz item symbol min. max. unit test conditions clock cycle time t cyc 50 250 ns figure 24-9 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rise time t cr ?10ns clock fall time t cf ?10ns clock oscillator settling time at reset (crystal) t osc1 20 ? ms figure 24-10 clock oscillator settling time in software standby (crystal) t osc2 8 ? ms figure 23a-3 figure 23b-3 external clock output stabilization delay time t dext 2 ? ms figure 24-10 32-khz clock oscillation settling time t osc3 ?2s subclock oscillator frequency f sub 32.768 khz subclock ( sub ) cycle time t sub 30.5 s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1030 of 1484 rej09b0103-0600 (2) control signal timing table 24-16 lists the control signal timing. table 24-16 control signal timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 24-11 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 24-12 nmi hold time t nmih 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1031 of 1484 rej09b0103-0600 (3) bus timing table 24-17 lists the bus timing. table 24-17 bus timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions address delay time t ad ?35ns address setup time t as 0.5 t cyc ? 20 ?ns figure 24-13 to figure 24-17 address hold time t ah 0.5 t cyc ? 15 ?ns as delay time t asd ?20ns rd delay time 1 t rsd1 ?20ns rd delay time 2 t rsd2 ?20ns read data setup time t rds 20 ? ns read data hold time t rdh 0?ns read data access time1 t acc1 ? 1.0 t cyc ? 48 ns read data access time2 t acc2 ? 1.5 t cyc ? 45 ns read data access time3 t acc3 ? 2.0 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 45 ns read data access time 5 t acc5 ? 3.0 t cyc ? 50 ns wr delay time 1 t wrd1 ?20ns wr delay time 2 t wrd2 ?20ns wr pulse width 1 t wsw1 1.0 t cyc ? 20 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 20 ? ns write data delay time t wdd ?30ns write data setup time t wds 0.5 t cyc ? 20 ? ns write data hold time t wdh 0.5 t cyc ? 10 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1032 of 1484 rej09b0103-0600 (4) timing of on-chip supporting modules table 24-18 lists the timing of on-chip supporting m odules. table 24-18 timing of on-chip supporting modules conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions i/o port output data delay time t pw d ?50ns output data delay time 2 t pw d2 ?50 figure 24-18 figure 24-19 input data setup time t prs 30 ? input data hold time t prh 30 ? ppg pulse output delay time t pod ? 50 ns figure 24-20 tpu timer output delay time t tocd ? 50 ns figure 24-21 timer input setup time t tics 30 ? timer clock input setup time t tcks 30 ? ns figure 24-22 single edge t tckwh 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? pwm pulse output delay time t mpw mod ? 50 ns figure 24-23 sci asynchronous t scyc 4?t cyc figure 24-24 input clock cycle synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?1.5t cyc input clock fall time t sckf ?1.5 transmit data delay time t txd ? 50 ns figure 24-25 receive data setup time (synchronous) t rxs 50 ? receive data hold time (synchronous) t rxh 50 ? a/d converter trigger input setup time t trgs 50 ? ns figure 24-26
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1033 of 1484 rej09b0103-0600 condition item symbol min. max. unit test conditions hcan * transmit data delay time t htxd ? 100 ns figure 24-27 receive data setup time t hrxs 100 ? receive data hold time t hrxh 100 ? note: * the hcan input signal is asynchronous. however, its state is judged to have changed at the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. the hcan output signal is also asynchronous. its state changes based on the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. table 24-19 i 2 c bus timing [option] * 1 conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, = 5 mhz to maximum operating frequency, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. typ. max. unit notes scl input cycle time t scl 12t cyc ? ? ns figure 24-28 scl input high pulse width t sclh 3t cyc ?? ns scl input low pulse width t scll 5t cyc ?? ns scl, sda input rise time t sr ?? 7.5t cyc * 2 ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse elimination time t sp ??1t cyc ns sda input bus free time t buf 5t cyc ?? ns start condition input hold time t stah 3t cyc ?? ns retransmission start condition input setup time t stas 3t cyc ?? ns stop condition input setup time t stos 3t cyc ?? ns data input setup time t sdas 0.5t cyc ?? ns data input hold time t sdah 0??ns scl, sda capacitive load c b ? ? 400 pf notes: 1. available when using i 2 c bus interface (the w-mask version only). 2. 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 15.4, usage notes.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1034 of 1484 rej09b0103-0600 24.2.5 a/d conversion characteristics table 24-20 lists the a/d conversion characteristics. table 24-20 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? ? s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k ? nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1035 of 1484 rej09b0103-0600 24.2.6 d/a conversion characteristics table 24-21 shows the d/a conversion characteristics. table 24-21 d/a conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit test conditions resolution 888bits conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 1.5 2.0 lsb 2-m ? resistive load ? ? 1.5 lsb 4-m ? resistive load
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1036 of 1484 rej09b0103-0600 24.2.7 flash memory characteristics table 24-22 shows the flash memory characteristics. table 24-22 flash memory characteristics conditions: v cc =4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss , av ss = 0 v t a = 0 to +75c (programming/erasing operating temperature range: regular specification) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ?10200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 11?s wait time after psu bit setting * 1 t spsu 50 50 ? s wait time after p bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 55?s wait time after psu bit clear * 1 t cpsu 55?s wait time after pv bit setting * 1 t spv 44?s wait time after h'ff dummy write * 1 t spvr 22?s wait time after pv bit clear * 1 t cpv 22?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1 * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 11?s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1037 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test condition erase wait time after h'ff dummy write * 1 t sevr 22?s wait time after ev bit clear * 1 t cev 44?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times notes: 1. make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time) 4. to specify the maximum programming time value (t p (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n)= 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max.)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 [ms], n = 12 times when t se = 10 [ms], n = 120 times
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1038 of 1484 rej09b0103-0600 24.3 h8s/2639 group, h8s/2635 group electrical characteristics 24.3.1 absolute maximum ratings table 24-23 lists the absolute maximum ratings. table 24-23 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (xtal * , extal) v in ?0.3 to v cc +0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (ports h and j) v in ?0.3 to pwmv cc +0.3 v input voltage (except xtal, extal, ports 4, 9, h and j) v in ?0.3 to v cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. note: * in the case of the h8s/2635 group, do not input a signal to the xtal pin.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1039 of 1484 rej09b0103-0600 24.3.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-5. 24 20 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 frequency (mhz) * 1 frequency (mhz) * 2 power supply voltage (v) power supply voltage (v) operating range of high-speed, medium-speed and sleep modes sub 0 3 3.5 4 4.5 5 5.5 6 operating range of watch, sub-active and sub-sleep modes notes: 1. an input clock frequency of 4 to 5 mhz should be used. for operation at 20 mhz, input a 5 mhz clock and use the pll to multiply it ( 4). 2. the maximum internal sub frequency is 39.06 khz (5 mhz/128). figure 24-5 power supply voltage and operating ranges
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1040 of 1484 rej09b0103-0600 24.3.3 dc characteristics table 24-24 lists the dc characteristics. table 24-25 lists the permissible output currents. table 24-24 dc characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 * 5 item symbol min. typ. max. unit test conditions irq0 to irq5 v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? input high voltage res , stby , nmi, fwe, md2 to md0 v ih v cc ? 0.7 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 ports 1, 3, f 2.2 ? v cc + 0.3 ports a to e v cc 0.8 ? v cc + 0.3 ports h, j pwmv cc 0.8 ?pwmv cc + 0.3 hrxd0, hrxd1 * 7 2.2 ? v cc + 0.3 ports 4 and 9 av cc 0.7 ? av cc + 0.3 input low voltage res , stby , nmi, fwe, md2 to md0 v il ?0.3 ? 0.5 v extal ?0.3 ? 0.8 ports 1, 3, f ?0.3 ? 0.8 ports a to e ?0.3 ? v cc 0.2 ports h, j ?0.3 ? pwmv cc 0.2 hrxd0, hrxd1 * 7 ?0.3 ? v cc 0.2 ports 4, 9 ?0.3 ? av cc 0.2
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1041 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions output high voltage ports 1, 3, a to f, h,j htxd0, htxd1 * 7 (excluding p34 and p35 * 6 ) v oh v cc ? 0.5 ? ? v i oh = ?200 a p34, p35 * 6 v cc ? 2.5 ? ? i oh = ?100 a ports 1, 3, a to f, h, j htxd0, htxd1 * 7 (excluding p34 and p35 * 6 ) 3.5 ? ? i oh = ?1 ma pwm1a to pwm1h, pwm2a to pwm2h pwmv cc ? 0.5 ?? i oh = ?15 ma output low voltage all output pins except pwm1a to pwm1h, pwm2a to pwm2h v ol ??0.4vi ol = 1.6 ma pwm1a to pwm1h, pwm2a to pwm2h ??0.5vi ol = 15 ma res | i in |? ?1.0 a stby , nmi , md2 to md0 ??1.0 v in =0.5 v to v cc ? 0.5 v hrxd0, hrxd1 * 7 , fwe ??1.0 input leakage current ports 4, 9 ? ? 1.0 v in = 0.5 v to av cc ? 0.5 v three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 * 7 ? i tsi ? ??1.0 av in =0.5 v to v cc ? 0.5 v
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1042 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions mos input pull-up current ports a to e ?i p 50 ? 300 av in = 0 v res c in ? ? 30 pf nmi ? ? 30 input capacitance all input pins except res and nmi ??15 v in = 0 v f = 1 mhz t a = 25c normal operation i cc * 4 ? 75 90 ma f = 20 mhz sleep mode ? 65 80 current dissipation * 2 (h8s/2639 group) all modules stopped ?57? ma f = 20 mhz (reference value) medium- speed mode ( /32) ?49? subactive mode ?0.71.0 ma subsleep mode ?0.71.0 subclock (using 4.19 mhz crystal oscillator) watch mode ? 0.6 1.0 ?2.05.0 at a 50c standby mode * 3 ? ? 20 50c < t a normal operation i cc * 8 ?6065 sleep mode ? 50 55 ma f = 20 mhz current dissipation * 2 (h8s/2635 group) all modules stopped ?40? medium- speed mode ( /32) ?45? ma f = 20 mhz (reference value) subactive mode ? 0.35 0.4 subsleep mode ? 0.3 0.35 watch mode ? 0.25 0.3 ma subclock (using 5.0 mhz crystal oscillator) ?2.05.0 at a 50c standby mode ? ? 20 50c < t a
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1043 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions analog power supply current during a/d and d/a * 7 conversion al cc ?1.02.0 maav cc = 5.0 v idle ? 0.1 5.0 a reference current during a/d and d/a * 7 conversion al cc ?4.05.0 mav ref = 5.0 v idle ? 0.1 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih (min.) = v cc ? 0.5 v, v il (max.) = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc 0.9, and v il (max.) = 0.3 v. 4. i cc depends on v cc and f as follows: i cc (max.) = 30 (ma) + 0.54 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 30 (ma) + 0.45 (ma/(mhz v)) v cc f (sleep mode) 5. if the motor-control pwm timer is not used, do not leave the pmwv cc , or pmwv ss pins open. if the motor-control pwm timer is not used, apply a voltage of between 4.5 and 5.5 v to the pwmv cc pin, for instance, by connecting it to v cc . 6. the characteristics of pins 34 and 35 apply to the w-mask version. 7. the htxd1, hrxd1 pins, and d/a converter are not available in the h8s/2635 group. 8. i cc depends on v cc and f as follows: i cc (max.) = 17 (ma) + 0.43 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 17 (ma) + 0.34 (ma/(mhz v)) v cc f (sleep mode)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1044 of 1484 rej09b0103-0600 table 24-25 permissible output currents conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test condition all output pins except pwm1a to pwm1h, pwm2a to pwm2h i ol ??10ma permissible output low current (per pin) pwm1a to pwm1h, pwm2a to pwm2h i ol ??25mat a = 85c ??30mat a = 25c ??40mat a = ?40c permissible output low current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h i ol ??80ma i ol ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c all output pins except pwm1a to pwm1h, pwm2a to pwm2h ?i oh ??2.0ma permissible output high current (per pin) ?i oh ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output high current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h ? i oh ??40ma ? i oh ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c note: to protect chip reliability, do not exceed the output current values in table 24-25.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1045 of 1484 rej09b0103-0600 table 24-26 bus drive characteristics [option] * conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) applicable pins: scl1 to 0, sda1 to 0 item symbol min. typ. max. unit test conditions v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? v cc = 4.5 v to 5.5 v input high voltage v ih ? v cc 0.7 ? v cc + 0.5 v input low voltage v il ? 0.5 ? v cc 0.3 v output low voltage v ol ??0.7vi ol = 8 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 3 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 1.6 ma, v cc = 3.3 v to 5.5 v input capacitance c in ? ? 20 pf v in = 0 v, f = 1mhz, t a = 25 c three-state leakage current (off state) ? i tsi ? ??1.0 av in = 0.5 v to v cc ? 5.5 v scl, sda, output fall time t of 20 + 0.1cb ? 250 ns note: * available when using the i 2 c bus interface (the w-mask version only).
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1046 of 1484 rej09b0103-0600 24.3.4 ac characteristics figure 24-6 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 50 pf: ports 10 to 13, a to f (in case of expansion bus control signal output pin setting) c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? input/output timing measurement levels ? low level: 0.8 v ? high level: 2.0 v figure 24-6 output load circuit
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1047 of 1484 rej09b0103-0600 (1) clock timing table 24-27 lists the clock timing table 24-27 clock timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition 20mhz item symbol min. max. unit test conditions clock cycle time t cyc 50 250 ns figure 24-9 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rise time t cr ?10ns clock fall time t cf ?10ns clock oscillator settling time at reset (crystal) t osc1 20 ? ms figure 24-10 clock oscillator settling time in software standby (crystal) (h8s/2639 group) t osc2 8 ? ms figure 23a-3 figure 23b-3 clock oscillator settling time in software standby (crystal) (h8s/2635 group) 12 ? external clock output stabilization delay time t dext 2 ? ms figure 24-10 subclock oscillator frequency f sub 31.25 39.6 khz subclock ( sub ) cycle time t sub 25.6 32.0 s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1048 of 1484 rej09b0103-0600 (2) control signal timing table 24-28 lists the control signal timing. table 24-28 control signal timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 24-11 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 24-12 nmi hold time t nmih 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1049 of 1484 rej09b0103-0600 (3) bus timing table 24-29 lists the bus timing. table 24-29 bus timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions address delay time t ad ?35ns address setup time t as 0.5 t cyc ? 20 ?ns figure 24-13 to figure 24-17 address hold time t ah 0.5 t cyc ? 15 ?ns as delay time t asd ?20ns rd delay time 1 t rsd1 ?20ns rd delay time 2 t rsd2 ?20ns read data setup time t rds 20 ? ns read data hold time t rdh 0?ns read data access time1 t acc1 ? 1.0 t cyc ? 48 ns read data access time2 t acc2 ? 1.5 t cyc ? 45 ns read data access time3 t acc3 ? 2.0 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 45 ns read data access time 5 t acc5 ? 3.0 t cyc ? 50 ns wr delay time 1 t wrd1 ?20ns wr delay time 2 t wrd2 ?20ns wr pulse width 1 t wsw1 1.0 t cyc ? 20 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 20 ? ns write data delay time t wdd ?30ns write data setup time t wds 0.5 t cyc ? 20 ? ns write data hold time t wdh 0.5 t cyc ? 10 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1050 of 1484 rej09b0103-0600 (4) timing of on-chip supporting modules table 24-30 lists the timing of on-chip supporting m odules. table 24-30 timing of on-chip supporting modules conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions i/o port output data delay time t pw d ?50ns output data delay time 2 t pw d2 ?50 figure 24-18 figure 24-19 input data setup time t prs 30 ? input data hold time t prh 30 ? ppg * 1 pulse output delay time t pod ? 50 ns figure 24-20 tpu timer output delay time t tocd ? 50 ns figure 24-21 timer input setup time t tics 30 ? timer clock input setup time t tcks 30 ? ns figure 24-22 single edge t tckwh 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? pwm pulse output delay time t mpw mod ? 50 ns figure 24-23 sci asynchronous t scyc 4?t cyc figure 24-24 input clock cycle synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?1.5t cyc input clock fall time t sckf ?1.5 transmit data delay time t txd ? 50 ns figure 24-25 receive data setup time (synchronous) t rxs 50 ? receive data hold time (synchronous) t rxh 50 ? a/d converter trigger input setup time t trgs 50 ? ns figure 24-26
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1051 of 1484 rej09b0103-0600 condition item symbol min. max. unit test conditions hcan * 2 transmit data delay time t htxd ? 100 ns figure 24-27 receive data setup time t hrxs 100 ? receive data hold time t hrxh 100 ? notes: 1. the ppg output is not available in the h8s2635 group. 2. the hcan input signal is asynchronous. however, its state is judged to have changed at the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. the hcan output signal is also asynchronous. its state changes based on the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. table 24-31 i 2 c bus timing [option] * 1 conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, = 5 mhz to maximum operating frequency, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. typ. max. unit notes scl input cycle time t scl 12t cyc ? ? ns figure 24-28 scl input high pulse width t sclh 3t cyc ?? ns scl input low pulse width t scll 5t cyc ?? ns scl, sda input rise time t sr ?? 7.5t cyc * 2 ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse elimination time t sp ??1t cyc ns sda input bus free time t buf 5t cyc ?? ns start condition input hold time t stah 3t cyc ?? ns retransmission start condition input setup time t stas 3t cyc ?? ns stop condition input setup time t stos 3t cyc ?? ns data input setup time t sdas 0.5t cyc ?? ns data input hold time t sdah 0??ns scl, sda capacitive load c b ? ? 400 pf notes: 1. available when using i 2 c bus interface (the w-mask version only). 2. 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 15.4, usage notes.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1052 of 1484 rej09b0103-0600 24.3.5 a/d conversion characteristics table 24-32 lists the a/d conversion characteristics. table 24-32 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? ? s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k ? nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1053 of 1484 rej09b0103-0600 24.3.6 d/a conversion characteristics * table 24-33 shows the d/a conversion characteristics. note: * the d/a conversion is not implemented in the h8s/2635 and h8s/2634. table 24-33 d/a conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit test conditions resolution 888bits conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 1.5 2.0 lsb 2-m ? resistive load ? ? 1.5 lsb 4-m ? resistive load
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1054 of 1484 rej09b0103-0600 24.3.7 flash memory characteristics table 24-34 shows the flash memory characteristics. table 24-34 flash memory characteristics conditions: v cc =4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss , av ss = 0 v t a = 0 to +75c (programming/erasing operating temperature range: regular specification) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ?10200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 11?s wait time after psu bit setting * 1 t spsu 50 50 ? s wait time after p bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 55?s wait time after psu bit clear * 1 t cpsu 55?s wait time after pv bit setting * 1 t spv 44?s wait time after h'ff dummy write * 1 t spvr 22?s wait time after pv bit clear * 1 t cpv 22?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1 * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 11?s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1055 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test condition erase wait time after h'ff dummy write * 1 t sevr 22?s wait time after ev bit clear * 1 t cev 44?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times notes: 1. make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time) 4. to specify the maximum programming time value (t p (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n)= 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max.)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 [ms], n = 12 times when t se = 10 [ms], n = 120 times
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1056 of 1484 rej09b0103-0600 24.4 h8s/2630 group electrical characteristics 24.4.1 absolute maximum ratings table 24-35 lists the absolute maximum ratings. table 24-35 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (osc1, osc2) v in ?0.3 +4.3 v input voltage (xtal, extal) v in ?0.3 to v cc +0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (ports h and j) v in ?0.3 to pwmv cc +0.3 v input voltage (except xtal, extal, osc1, osc2, ports 4, 9, h and j) v in ?0.3 to v cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1057 of 1484 rej09b0103-0600 24.4.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24-7. 24 20 16 12 8 4 0 3 3.5 4 4.5 5 5.5 6 frequency (mhz) frequency (mhz) power supply voltage (v) power supply voltage (v) operating range of high-speed, medium-speed and sleep modes 32.768 0 3 3.5 4 4.5 5 5.5 6 operating range of watch * , sub-active * and sub-sleep * modes note: * the watch, subactive, and subsleep modes are available in the u-mask and w-mask versions only. figure 24-7 power supply voltage and operating ranges
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1058 of 1484 rej09b0103-0600 24.4.3 dc characteristics table 24-36 lists the dc characteristics. table 24-36 lists the permissible output currents. table 24-36 dc characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 * 6 item symbol min. typ. max. unit test conditions irq0 to irq5 v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? input high voltage res , stby , nmi, fwe, md2 to md0 v ih v cc ? 0.7 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 ports 1, 3, f 2.2 ? v cc + 0.3 ports a to e v cc 0.8 ? v cc + 0.3 ports h, j pwmv cc 0.8 ?pwmv cc + 0.3 hrxd0, hrxd1 2.2 ? v cc + 0.3 ports 4 and 9 av cc 0.7 ? av cc + 0.3 input low voltage res , stby , nmi, fwe, md2 to md0 v il ?0.3 ? 0.5 v extal ?0.3 ? 0.8 ports 1, 3, f ?0.3 ? 0.8 ports a to e ?0.3 ? v cc 0.2 ports h, j ?0.3 ? pwmv cc 0.2 hrxd0, hrxd1 ?0.3 ? v cc 0.2 ports 4, 9 ?0.3 ? av cc 0.2
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1059 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions output high voltage ports 1, 3, a to f, h,j htxd0, htxd1 (excluding p34 and p35 * 7 ) v oh v cc ? 0.5 ? ? v i oh = ?200 a p34, p35 * 7 v cc ? 2.5 ? ? i oh = ?100 a ports 1, 3, a to f, h, j htxd0, htxd1 (excluding p34 and p35 * 7 ) 3.5 ? ? i oh = ?1 ma pwm1a to pwm1h, pwm2a to pwm2h pwmv cc ? 0.5 ?? i oh = ?15 ma output low voltage all output pins except pwm1a to pwm1h, pwm2a to pwm2h v ol ??0.4vi ol = 1.6 ma pwm1a to pwm1h, pwm2a to pwm2h ??0.5vi ol = 15 ma res | i in |? ?1.0 a input leakage current stby , nmi , md2 to md0 ??1.0 v in = 0.5 v to v cc ? 0.5 v hrxd0, hrxd1, fwe ??1.0 ports 4, 9 ? ? 1.0 v in = 0.5 v to av cc ? 0.5 v three-state leakage current (off state) ports 1, 3, a to f, h, j htxd0, htxd1 ? i tsi ? ??1.0 av in = 0.5 v to v cc ? 0.5 v
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1060 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test conditions mos input pull-up current ports a to e ?i p 50 ? 300 av in = 0 v res c in ? ? 30 pf nmi ? ? 30 input capacitance all input pins except res and nmi ??15 v in = 0 v f = 1 mhz t a = 25c current dissipation * 2 normal operation i cc * 4 ? 75 90 ma f = 20 mhz sleep mode ? 65 80 all modules stopped ? 57 ? ma f = 20 mhz (reference value) medium- speed mode ( /32) ?49? subactive mode * 5 ? 130 220 a using 32.768 khz crystal resonator subsleep mode * 5 ? 80 160 watch mode * 5 ?3060 ?2.05.0 at a 50c standby mode * 3 ? ? 20 50c < t a analog power supply current during a/d and d/a conversion al cc ?1.02.0 maav cc = 5.0 v idle ? 0.1 5.0 a reference current during a/d and d/a conversion al cc ?4.05.0 mav ref = 5.0 v idle ? 0.1 5.0 a ram standby voltage v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih (min.) = v cc ? 0.5 v, v il (max.) = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc 0.9, and v il (max.) = 0.3 v.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1061 of 1484 rej09b0103-0600 4. i cc depends on v cc and f as follows: i cc (max.) = 30 (ma) + 0.54 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 30 (ma) + 0.45 (ma/(mhz v)) v cc f (sleep mode) 5. the watch, subactive, and subsleep modes are available in the u-mask and w-mask versions only. see section 22a.7, subclock oscillator, for the method of fixing pins osc1 and osc2. 6. if the motor-control pwm timer is not used, do not leave the pmwv cc , or pmwv ss pins open. if the motor-control pwm timer is not used, apply a voltage of between 4.5 and 5.5 v to the pwmv cc pin, for instance, by connecting it to v cc . 7. the characteristics of pins 34 and 35 apply to the w-mask version.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1062 of 1484 rej09b0103-0600 table 24-37 permissible output currents conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min. typ. max. unit test condition all output pins except pwm1a to pwm1h, pwm2a to pwm2h i ol ??10ma permissible output low current (per pin) i ol ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output low current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h i ol ??80ma i ol ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c all output pins except pwm1a to pwm1h, pwm2a to pwm2h ?i oh ??2.0ma permissible output high current (per pin) ?i oh ??25mat a = 85c pwm1a to pwm1h, pwm2a to pwm2h ??30mat a = 25c ??40mat a = ?40c permissible output high current (total) total of all output pins excepting pwm1a to pwm1h, and pwm2a to pwm2h ? i oh ??40ma ? i oh ? ? 150 ma t a = 85c total of pwm1a to pwm1h, and pwm2a to pwm2h ? ? 180 ma t a = 25c ? ? 220 ma t a = ?40c note: to protect chip reliability, do not exceed the output current values in table 24-37.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1063 of 1484 rej09b0103-0600 table 24-38 bus drive characteristics [option] * conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) applicable pins: scl1-0, sda1-0 item symbol min. typ. max. unit test conditions v t ? 1.0 ? ? v v t + ??v cc 0.7 schmitt trigger input voltage v t + ? v t ? 0.4 ? ? v cc = 4.5 v to 5.5 v input high voltage v ih ? v cc 0.7 ? v cc + 0.5 v input low voltage v il ? 0.5 ? v cc 0.3 v output low voltage v ol ??0.7vi ol = 8 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 3 ma, v cc = 4.5 v to 5.5 v ??0.4 i ol = 1.6 ma, v cc = 3.3 v to 5.5 v input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25 c three-state leakage current (off state) ? i tsi ? ??1.0 a v in = 0.5 v to v cc ? 5.5 v scl, sda, output fall time t of 20 + 0.1cb ? 250 ns note: * available when using i 2 c bus interface (the w-mask version only).
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1064 of 1484 rej09b0103-0600 24.4.4 ac characteristics figure 24-8 show, the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 50 pf: ports 10 to 13, a to f (in case of expansion bus control signal output pin setting) c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? input/output timing measurement levels ? low level: 0.8 v ? high level: 2.0 v figure 24-8 output load circuit
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1065 of 1484 rej09b0103-0600 (1) clock timing table 24-39 lists the clock timing table 24-39 clock timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition 20mhz item symbol min. max. unit test conditions clock cycle time t cyc 50 250 ns figure 24-9 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rise time t cr ?10ns clock fall time t cf ?10ns clock oscillator settling time at reset (crystal) t osc1 20 ? ms figure 24-10 clock oscillator settling time in software standby (crystal) t osc2 8 ? ms figure 23a-3 figure 23b-3 external clock output stabilization delay time t dext 2 ? ms figure 24-10 32-khz clock oscillation settling time t osc3 ?2s subclock oscillator frequency f sub 32.768 khz subclock ( sub ) cycle time t sub 30.5 s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1066 of 1484 rej09b0103-0600 (2) control signal timing table 24-40 lists the control signal timing. table 24-40 control signal timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 24-11 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 24-12 nmi hold time t nmih 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1067 of 1484 rej09b0103-0600 (3) bus timing table 24-41 lists the bus timing. table 24-41 bus timing conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions address delay time t ad ?35ns address setup time t as 0.5 t cyc ? 20 ?ns figure 24-13 to figure 24-17 address hold time t ah 0.5 t cyc ? 15 ?ns as delay time t asd ?20ns rd delay time 1 t rsd1 ?20ns rd delay time 2 t rsd2 ?20ns read data setup time t rds 20 ? ns read data hold time t rdh 0?ns read data access time1 t acc1 ? 1.0 t cyc ? 48 ns read data access time2 t acc2 ? 1.5 t cyc ? 45 ns read data access time3 t acc3 ? 2.0 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 45 ns read data access time 5 t acc5 ? 3.0 t cyc ? 50 ns wr delay time 1 t wrd1 ?20ns wr delay time 2 t wrd2 ?20ns wr pulse width 1 t wsw1 1.0 t cyc ? 20 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 20 ? ns write data delay time t wdd ?30ns write data setup time t wds 0.5 t cyc ? 20 ? ns write data hold time t wdh 0.5 t cyc ? 10 ? ns
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1068 of 1484 rej09b0103-0600 (4) timing of on-chip supporting modules table 24-42 lists the timing of on-chip supporting m odules. table 24-42 timing of on-chip supporting modules conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. max. unit test conditions i/o port output data delay time t pw d ?50ns output data delay time 2 t pw d2 ?50 figure 24-18 figure 24-19 input data setup time t prs 30 ? input data hold time t prh 30 ? ppg pulse output delay time t pod ? 50 ns figure 24-20 tpu timer output delay time t tocd ? 50 ns figure 24-21 timer input setup time t tics 30 ? timer clock input setup time t tcks 30 ? ns figure 24-22 single edge t tckwh 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? pwm pulse output delay time t mpw mod ? 50 ns figure 24-23 sci asynchronous t scyc 4?t cyc figure 24-24 input clock cycle synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?1.5t cyc input clock fall time t sckf ?1.5 transmit data delay time t txd ? 50 ns figure 24-25 receive data setup time (synchronous) t rxs 50 ? receive data hold time (synchronous) t rxh 50 ? a/d converter trigger input setup time t trgs 50 ? ns figure 24-26
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1069 of 1484 rej09b0103-0600 condition item symbol min. max. unit test conditions hcan * transmit data delay time t htxd ? 100 ns figure 24-27 receive data setup time t hrxs 100 ? receive data hold time t hrxh 100 ? note: * the hcan input signal is asynchronous. however, its state is judged to have changed at the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. the hcan output signal is also asynchronous. its state changes based on the leading edge (two clock cycles) of the ck clock signal shown in figure 24-27. table 24-43 i 2 c bus timing [option] * 1 conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, = 5 mhz to maximum operating frequency, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item symbol min. typ. max. unit notes scl input cycle time t scl 12t cyc ? ? ns figure 24-28 scl input high pulse width t sclh 3t cyc ?? ns scl input low pulse width t scll 5t cyc ?? ns scl, sda input rise time t sr ?? 7.5t cyc * 2 ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse elimination time t sp ??1t cyc ns sda input bus free time t buf 5t cyc ?? ns start condition input hold time t stah 3t cyc ?? ns retransmission start condition input setup time t stas 3t cyc ?? ns stop condition input setup time t stos 3t cyc ?? ns data input setup time t sdas 0.5t cyc ?? ns data input hold time t sdah 0??ns scl, sda capacitive load c b ? ? 400 pf notes: 1. available when using i 2 c bus interface (the w-mask version only). 2. 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 15.4, usage notes.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1070 of 1484 rej09b0103-0600 24.4.5 a/d conversion characteristics table 24-44 lists the a/d conversion characteristics. table 24-44 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? ? s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k ? nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1071 of 1484 rej09b0103-0600 24.4.6 d/a conversion characteristics table 24-45 shows the d/a conversion characteristics. table 24-45 d/a conversion characteristics conditions: v cc = 4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition item min. typ. max. unit test conditions resolution 888bits conversion time ? ? 10 s 20-pf capacitive load absolute accuracy ? 1.5 2.0 lsb 2-m ? resistive load ? ? 1.5 lsb 4-m ? resistive load
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1072 of 1484 rej09b0103-0600 24.4.7 flash memory characteristics table 24-46 shows the flash memory characteristics. table 24-46 flash memory characteristics conditions: v cc =4.5 v to 5.5 v, pwmv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = pwmv ss = pllv ss , av ss = 0 v t a = 0 to +75c (programming/erasing operating temperature range: regular specification) item symbol min. typ. max. unit test condition programming time * 1 * 2 * 4 t p ?10200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 11?s wait time after psu bit setting * 1 t spsu 50 50 ? s wait time after p bit setting * 1 * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 55?s wait time after psu bit clear * 1 t cpsu 55?s wait time after pv bit setting * 1 t spv 44?s wait time after h'ff dummy write * 1 t spvr 22?s wait time after pv bit clear * 1 t cpv 22?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1 * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 11?s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1073 of 1484 rej09b0103-0600 item symbol min. typ. max. unit test condition erase wait time after h'ff dummy write * 1 t sevr 22?s wait time after ev bit clear * 1 t cev 44?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times notes: 1. make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time) 4. to specify the maximum programming time value (t p (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p bit setting should be changed as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n)= 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max.)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max.) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 [ms], n = 12 times when t se = 10 [ms], n = 120 times
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1074 of 1484 rej09b0103-0600 24.5 operation timing the operation timing is shown below. 24.5.1 clock timing the clock timing is shown below. t ch t cf t cyc t cl t cr figure 24-9 system clock timing t osc1 t osc1 extal v cc stby res t dext t dext figure 24-10 oscillator settling timing
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1075 of 1484 rej09b0103-0600 24.5.2 control signal timing the control signal timing is shown below. t resw t ress t ress res figure 24-11 reset input timing t irqs irq edge input t irqh t nmis t nmih t irqs irq level input nmi irq t nmiw t irqw figure 24-12 interrupt input timing
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1076 of 1484 rej09b0103-0600 24.5.3 bus timing the bus timing is shown below. t rsd2 t 1 t ad as a 23 to a0 t asd rd (read) hwr , lwr (write) t 2 t as t asd t acc2 t rsd1 t acc3 t rds t rdh t wrd2 t wdd t wsw1 t wdh d15 to d0 (read) d15 to d0 (write) t ah t wrd2 figure 24-13 basic bus timing (two-state access)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1077 of 1484 rej09b0103-0600 t rsd2 t 2 as a 23 to a0 t asd rd (read) t 3 t as t ah t asd t acc4 t rsd1 t acc5 t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t 1 t wdd t ad figure 24-14 basic bus timing (three-state access)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1078 of 1484 rej09b0103-0600 t 1 t 2 t w t 3 t as t rsd1 t asd t asd t rsd2 t ad t rdh t wdh t rds t wds t wrd2 t wrd1 t ah t wdd as a 23 to a0 rd (read) d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) figure 24-15 basic bus timing (three-state access with one wait state)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1079 of 1484 rej09b0103-0600 t rsd2 t 1 a s a 23 to a0 t 2 t ah t acc3 t rds d15 to d0 (read) t 2 or t 3 t as t 1 t asd t asd t rdh t ad rd (read) figure 24-16 burst rom access timing (two-state access)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1080 of 1484 rej09b0103-0600 t 1 as a 23 to a0 t 1 t acc1 d15 to d0 (read) t 2 or t 3 t rdh t ad rd (read) t rds t rsd2 figure 24-17 burst rom access timing (one-state access) 24.5.4 on-chip supporting module timing the on-chip supporting module t iming is shown below. ports 1, 3, 4, 9 a to f (read) t 2 t 1 t pwd t prh t prs ports 1, 3, a to f (write) figure 24-18 i/o port input/output timing (ports 1, 3, 4, 9, a to f)
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1081 of 1484 rej09b0103-0600 bus cycle t 1 t 2 t 3 t 4 t prh t pwd2 t prs ports h, j (read) ports h, j (write) figure 24-19 i/o port (ports h and j) input/output timing po15 to po8 t pod figure 24-20 ppg output timing * note: * the ppg output is not implemented in the h8s/2635 and h8s/2634.
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1082 of 1484 rej09b0103-0600 t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 24-21 tpu input/output timing t tcks t tcks tclka to tclkd t tckwh t tckwl figure 24-22 tpu clock input timing pwm1a to pwm1h, pwm2a to pwm2h t mpwmod figure 24-23 motor control pwm output timing sck0 to sck2 t sckw t sckr t sckf t scyc figure 24-24 sck clock input timing
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1083 of 1484 rej09b0103-0600 txd0 to txd2 (transit data) rxd0 to rxd2 (receive data) sck0 to sck2 t rxs t rxh t txd figure 24-25 sci input/output timing (clock synchronous mode) adtrg t trgs figure 24-26 a/d converter external trigger input timing ck htxd0, htxd1 (transmit data) hrxd0, hrxd1 (receive data) t h txd t hrxh t hrxs preliminary figure 24-27 hcan input/output timing
section 24 electrical characteristics rev. 6.00 feb 22, 2005 page 1084 of 1484 rej09b0103-0600 t buf t stah t stas t sp t stos t sclh t scll t sf t sr t scl t sdah t sdas p * s * s r * v ih v il sda0 to sda1 scl0 to scl1 note: * s, p, and sr indicate the following conditions. s: start condition p: stop condition sr : retransmission start condition figure 24-28 i 2 c bus interface input/output timing (option) * note: * i 2 c bus interface is available a an option in the h8s/2638, h8s/2639, and h8s/2630 only. 24.6 usage note although both the f-ztat and mask rom versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip rom, and the layout patterns. therefore, if a system is evaluated using the f-ztat version, a similar evaluation should also be performed using the mask rom version.
appendix a instruction set rev. 6.00 feb 22, 2005 page 1085 of 1484 rej09b0103-0600 appendix a instruction set a.1 instruction list operand notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement +add ? subtract multiply divide logical and logical or logical exclusive or transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ? logical not (logical complement) ( ) < > contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
appendix a instruction set rev. 6.00 feb 22, 2005 page 1086 of 1484 rej09b0103-0600 condition code notation symbol changes according to the result of instruction * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 ? not affected by execution of the instruction
appendix a instruction set rev. 6.00 feb 22, 2005 page 1087 of 1484 rej09b0103-0600 table a-1 instruction set (1) data transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov mov.b #xx:8,rd b 2 mov.b rs,rd b 2 mov.b @ers,rd b 2 mov.b @(d:16,ers),rd b 4 mov.b @(d:32,ers),rd b 8 mov.b @ers+,rd b 2 mov.b @aa:8,rd b 2 mov.b @aa:16,rd b 4 mov.b @aa:32,rd b 6 mov.b rs,@erd b 2 mov.b rs,@(d:16,erd) b 4 mov.b rs,@(d:32,erd) b 8 mov.b rs,@-erd b 2 mov.b rs,@aa:8 b 2 mov.b rs,@aa:16 b 4 mov.b rs,@aa:32 b 6 mov.w #xx:16,rd w 4 mov.w rs,rd w 2 mov.w @ers,rd w 2 #xx:8 rd8 ? ? 0 ? 1 rs8 rd8 ? ? 0 ? 1 @ers rd8 ? ? 0 ? 2 @(d:16,ers) rd8 ? ? 0 ? 3 @(d:32,ers) rd8 ? ? 0 ? 5 @ers rd8,ers32+1 ers32 ? ? 0 ? 3 @aa:8 rd8 ? ? 0 ? 2 @aa:16 rd8 ? ? 0 ? 3 @aa:32 rd8 ? ? 0 ? 4 rs8 @erd ? ? 0 ? 2 rs8 @(d:16,erd) ? ? 0 ? 3 rs8 @(d:32,erd) ? ? 0 ? 5 erd32-1 erd32,rs8 @erd ? ? 0 ? 3 rs8 @aa:8 ? ? 0 ? 2 rs8 @aa:16 ? ? 0 ? 3 rs8 @aa:32 ? ? 0 ? 4 #xx:16 rd16 ? ? 0 ? 2 rs16 rd16 ? ? 0 ? 1 @ers rd16 ? ? 0 ? 2 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1088 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov mov.w @(d:16,ers),rd w 4 mov.w @(d:32,ers),rd w 8 mov.w @ers+,rd w 2 mov.w @aa:16,rd w 4 mov.w @aa:32,rd w 6 mov.w rs,@erd w 2 mov.w rs,@(d:16,erd) w 4 mov.w rs,@(d:32,erd) w 8 mov.w rs,@-erd w 2 mov.w rs,@aa:16 w 4 mov.w rs,@aa:32 w 6 mov.l #xx:32,erd l 6 mov.l ers,erd l 2 mov.l @ers,erd l 4 mov.l @(d:16,ers),erd l 6 mov.l @(d:32,ers),erd l 10 mov.l @ers+,erd l 4 mov.l @aa:16,erd l 6 mov.l @aa:32,erd l 8 @(d:16,ers) rd16 ? ? 0 ? 3 @(d:32,ers) rd16 ? ? 0 ? 5 @ers rd16,ers32+2 ers32 ? ? 0 ? 3 @aa:16 rd16 ? ? 0 ? 3 @aa:32 rd16 ? ? 0 ? 4 rs16 @erd ? ? 0 ? 2 rs16 @(d:16,erd) ? ? 0 ? 3 rs16 @(d:32,erd) ? ? 0 ? 5 erd32-2 erd32,rs16 @erd ? ? 0 ? 3 rs16 @aa:16 ? ? 0 ? 3 rs16 @aa:32 ? ? 0 ? 4 #xx:32 erd32 ? ? 0 ? 3 ers32 erd32 ? ? 0 ? 1 @ers erd32 ? ? 0 ? 4 @(d:16,ers) erd32 ? ? 0 ? 5 @(d:32,ers) erd32 ? ? 0 ? 7 @ers erd32,ers32+4 ers32 ? ? 0 ? 5 @aa:16 erd32 ? ? 0 ? 5 @aa:32 erd32 ? ? 0 ? 6 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1089 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov pop push ldm * 4 stm * 4 movfpe movtpe mov.l ers,@erd l 4 mov.l ers,@(d:16,erd) l 6 mov.l ers,@(d:32,erd) l 10 mov.l ers,@-erd l 4 mov.l ers,@aa:16 l 6 mov.l ers,@aa:32 l 8 pop.w rn w 2 pop.l ern l 4 push.w rn w 2 push.l ern l 4 ldm @sp+,(erm-ern) l 4 stm (erm-ern),@-sp l 4 movfpe @aa:16,rd movtpe rs,@aa:16 ers32 @erd ? ? 0 ? 4 ers32 @(d:16,erd) ? ? 0 ? 5 ers32 @(d:32,erd) ? ? 0 ? 7 erd32-4 erd32,ers32 @ erd ? ? 0 ? 5 ers32 @aa:16 ? ? 0 ? 5 ers32 @aa:32 ? ? 0 ? 6 @sp rn16,sp+2 sp ? ? 0 ? 3 @sp ern32,sp+4 sp ? ? 0 ? 5 sp-2 sp,rn16 @sp ? ? 0 ? 3 sp-4 sp,ern32 @sp ? ? 0 ? 5 (@sp ern32,sp+4 sp) ? ? ? ? ? ? 7/9/11 [1] repeated for each register restored (sp-4 sp,ern32 @sp) ? ? ? ? ? ? 7/9/11 [1] repeated for each register saved [2] [2] operation condition code ihnzvc advanced no. of states * 1 ?????????? ?????????? cannot be used in this lsi cannot be used in this lsi
appendix a instruction set rev. 6.00 feb 22, 2005 page 1090 of 1484 rej09b0103-0600 (2) arithmetic instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic add addx adds inc daa sub add.b #xx:8,rd b 2 add.b rs,rd b 2 add.w #xx:16,rd w 4 add.w rs,rd w 2 add.l #xx:32,erd l 6 add.l ers,erd l 2 addx #xx:8,rd b 2 addx rs,rd b 2 adds #1,erd l 2 adds #2,erd l 2 adds #4,erd l 2 inc.b rd b 2 inc.w #1,rd w 2 inc.w #2,rd w 2 inc.l #1,erd l 2 inc.l #2,erd l 2 daa rd b 2 sub.b rs,rd b 2 sub.w #xx:16,rd w 4 rd8+#xx:8 rd8 ? 1 rd8+rs8 rd8 ? 1 rd16+#xx:16 rd16 ? [3] 2 rd16+rs16 rd16 ? [3] 1 erd32+#xx:32 erd32 ? [4] 3 erd32+ers32 erd32 ? [4] 1 rd8+#xx:8+c rd8 ? [5] 1 rd8+rs8+c rd8 ? [5] 1 erd32+1 erd32 ? ? ? ? ? ? 1 erd32+2 erd32 ? ? ? ? ? ? 1 erd32+4 erd32 ? ? ? ? ? ? 1 rd8+1 rd8 ? ? ? 1 rd16+1 rd16 ? ? ? 1 rd16+2 rd16 ? ? ? 1 erd32+1 erd32 ? ? ? 1 erd32+2 erd32 ? ? ? 1 rd8 decimal adjust rd8 ? * * 1 rd8-rs8 rd8 ? 1 rd16-#xx:16 rd16 ? [3] 2 operation condition code ihnzvc advanced no. of states * 1 ??? ? ???????? ?? ????? ???????? ???????? ???????? ?????? ???????? ?? ??
appendix a instruction set rev. 6.00 feb 22, 2005 page 1091 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic sub subx subs dec das mulxu mulxs sub.w rs,rd w 2 sub.l #xx:32,erd l 6 sub.l ers,erd l 2 subx #xx:8,rd b 2 subx rs,rd b 2 subs #1,erd l 2 subs #2,erd l 2 subs #4,erd l 2 dec.b rd b 2 dec.w #1,rd w 2 dec.w #2,rd w 2 dec.l #1,erd l 2 dec.l #2,erd l 2 das rd b 2 mulxu.b rs,rd b 2 mulxu.w rs,erd w 2 mulxs.b rs,rd b 4 mulxs.w rs,erd w 4 rd16-rs16 rd16 ? [3] 1 erd32-#xx:32 erd32 ? [4] 3 erd32-ers32 erd32 ? [4] 1 rd8-#xx:8-c rd8 ? [5] 1 rd8-rs8-c rd8 ? [5] 1 erd32-1 erd32 ? ? ? ? ? ? 1 erd32-2 erd32 ? ? ? ? ? ? 1 erd32-4 erd32 ? ? ? ? ? ? 1 rd8-1 rd8 ? ? ? 1 rd16-1 rd16 ? ? ? 1 rd16-2 rd16 ? ? ? 1 erd32-1 erd32 ? ? ? 1 erd32-2 erd32 ? ? ? 1 rd8 decimal adjust rd8 ? * * ? 1 rd8 rs8 rd16 (unsigned multiplication) ? ? ? ? ? ? 3 rd16 rs16 erd32 ? ? ? ? ? ? 4 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) ? ? ? ? 4 rd16 rs16 erd32 ? ? ? ? 5 (signed multiplication) operation condition code ihnzvc advanced no. of states * 1 ?? ?? ?????? ?????? ????? ??? ????? ????? ????? ??
appendix a instruction set rev. 6.00 feb 22, 2005 page 1092 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic divxu divxs cmp neg extu divxu.b rs,rd b 2 divxu.w rs,erd w 2 divxs.b rs,rd b 4 divxs.w rs,erd w 4 cmp.b #xx:8,rd b 2 cmp.b rs,rd b 2 cmp.w #xx:16,rd w 4 cmp.w rs,rd w 2 cmp.l #xx:32,erd l 6 cmp.l ers,erd l 2 neg.b rd b 2 neg.w rd w 2 neg.l erd l 2 extu.w rd w 2 extu.l erd l 2 rd16 rs8 rd16 (rdh: remainder, ? ? [6] [7] ? ? 12 rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, ? ? [6] [7] ? ? 20 rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, ? ? [8] [7] ? ? 13 rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, ? ? [8] [7] ? ? 21 rd: quotient) (signed division) rd8-#xx:8 ? 1 rd8-rs8 ? 1 rd16-#xx:16 ? [3] 2 rd16-rs16 ? [3] 1 erd32-#xx:32 ? [4] 3 erd32-ers32 ? [4] 1 0-rd8 rd8 ? 1 0-rd16 rd16 ? 1 0-erd32 erd32 ? 1 0 ( of rd16) ? ? 0 0 ? 1 0 ( of erd32) ? ? 0 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ??? ?? ??????????? ????????? ????????? ?????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1093 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic exts tas mac clrmac ldmac stmac exts.w rd w 2 exts.l erd l 2 tas @erd * 3 b 4 mac @ern+,@erm+ ? 4 clrmac ? 2 ldmac ers,mach l 2 ldmac ers,macl l 2 stmac mach,erd l 2 stmac macl,erd l 2 ( of rd16) ? ? 0 ? 1 ( of rd16) ( of erd32) ? ? 0 ? 1 ( of erd32) @erd-0 ccr set, (1) ? ? 0 ? 4 ( < bit 7 > of @erd) @ern @erm+mac mac ? ? ? ? ? ? 4 (signed multiplication) [10] [10] [10] ern+2 ern,erm+2 erm 0 mach,macl ? ? ? ? ? ? 2 [11] ers mach ? ? ? ? ? ? 2 [11] ers macl ? ? ? ? ? ? 2 [11] mach erd ? ? ? 1 [11] macl erd ? ? ? 1 [11] operation condition code ihnzvc advanced no. of states * 1 ?? ?? ?? ? ? ? ? ? ?
appendix a instruction set rev. 6.00 feb 22, 2005 page 1094 of 1484 rej09b0103-0600 (3) logical instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic and or xor not and.b #xx:8,rd b 2 and.b rs,rd b 2 and.w #xx:16,rd w 4 and.w rs,rd w 2 and.l #xx:32,erd l 6 and.l ers,erd l 4 or.b #xx:8,rd b 2 or.b rs,rd b 2 or.w #xx:16,rd w 4 or.w rs,rd w 2 or.l #xx:32,erd l 6 or.l ers,erd l 4 xor.b #xx:8,rd b 2 xor.b rs,rd b 2 xor.w #xx:16,rd w 4 xor.w rs,rd w 2 xor.l #xx:32,erd l 6 xor.l ers,erd l 4 not.b rd b 2 not.w rd w 2 not.l erd l 2 rd8 #xx:8 rd8 ? ? 0 ? 1 rd8 rs8 rd8 ? ? 0 ? 1 rd16 #xx:16 rd16 ? ? 0 ? 2 rd16 rs16 rd16 ? ? 0 ? 1 erd32 #xx:32 erd32 ? ? 0 ? 3 erd32 ers32 erd32 ? ? 0 ? 2 rd8 #xx:8 rd8 ? ? 0 ? 1 rd8 rs8 rd8 ? ? 0 ? 1 rd16 #xx:16 rd16 ? ? 0 ? 2 rd16 rs16 rd16 ? ? 0 ? 1 erd32 #xx:32 erd32 ? ? 0 ? 3 erd32 ers32 erd32 ? ? 0 ? 2 rd8 #xx:8 rd8 ? ? 0 ? 1 rd8 rs8 rd8 ? ? 0 ? 1 rd16 #xx:16 rd16 ? ? 0 ? 2 rd16 rs16 rd16 ? ? 0 ? 1 erd32 #xx:32 erd32 ? ? 0 ? 3 erd32 ers32 erd32 ? ? 0 ? 2 ? rd8 rd8 ? ? 0 ? 1 ? rd16 rd16 ? ? 0 ? 1 ? erd32 erd32 ? ? 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ????????????????????? ?????????????????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1095 of 1484 rej09b0103-0600 (4) shift instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic shal shar shll shal.b rd b 2 shal.b #2,rd b 2 shal.w rd w 2 shal.w #2,rd w 2 shal.l erd l 2 shal.l #2,erd l 2 shar.b rd b 2 shar.b #2,rd b 2 shar.w rd w 2 shar.w #2,rd w 2 shar.l erd l 2 shar.l #2,erd l 2 shll.b rd b 2 shll.b #2,rd b 2 shll.w rd w 2 shll.w #2,rd w 2 shll.l erd l 2 shll.l #2,erd l 2 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ?????? ?????????????????? c msb lsb msb lsb 0 c msb lsb c 0
appendix a instruction set rev. 6.00 feb 22, 2005 page 1096 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic shlr rotxl rotxr shlr.b rd b 2 shlr.b #2,rd b 2 shlr.w rd w 2 shlr.w #2,rd w 2 shlr.l erd l 2 shlr.l #2,erd l 2 rotxl.b rd b 2 rotxl.b #2,rd b 2 rotxl.w rd w 2 rotxl.w #2,rd w 2 rotxl.l erd l 2 rotxl.l #2,erd l 2 rotxr.b rd b 2 rotxr.b #2,rd b 2 rotxr.w rd w 2 rotxr.w #2,rd w 2 rotxr.l erd l 2 rotxr.l #2,erd l 2 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ???????????? c msb lsb 0 c msb lsb c msb lsb
appendix a instruction set rev. 6.00 feb 22, 2005 page 1097 of 1484 rej09b0103-0600 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? 0 1 ? ? ? 0 1 1 ? ? 0 1 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic rotl rotr rotl.b rd b 2 rotl.b #2,rd b 2 rotl.w rd w 2 rotl.w #2,rd w 2 rotl.l erd l 2 rotl.l #2,erd l 2 rotr.b rd b 2 rotr.b #2,rd b 2 rotr.w rd w 2 rotr.w #2,rd w 2 rotr.l erd l 2 rotr.l #2,erd l 2 operation condition code ihnzvc advanced no. of states * 1 ???????????? ???????????? ???????????? c msb lsb c msb lsb
appendix a instruction set rev. 6.00 feb 22, 2005 page 1098 of 1484 rej09b0103-0600 (5) bit-manipulation instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bset bclr bset #xx:3,rd b 2 bset #xx:3,@erd b 4 bset #xx:3,@aa:8 b 4 bset #xx:3,@aa:16 b 6 bset #xx:3,@aa:32 b 8 bset rn,rd b 2 bset rn,@erd b 4 bset rn,@aa:8 b 4 bset rn,@aa:16 b 6 bset rn,@aa:32 b 8 bclr #xx:3,rd b 2 bclr #xx:3,@erd b 4 bclr #xx:3,@aa:8 b 4 bclr #xx:3,@aa:16 b 6 bclr #xx:3,@aa:32 b 8 bclr rn,rd b 2 bclr rn,@erd b 4 bclr rn,@aa:8 b 4 bclr rn,@aa:16 b 6 (#xx:3 of rd8) 1 ? ? ? ? ? ? 1 (#xx:3 of @erd) 1 ? ? ? ? ? ? 4 (#xx:3 of @aa:8) 1 ? ? ? ? ? ? 4 (#xx:3 of @aa:16) 1 ? ? ? ? ? ? 5 (#xx:3 of @aa:32) 1 ? ? ? ? ? ? 6 (rn8 of rd8) 1 ? ? ? ? ? ? 1 (rn8 of @erd) 1 ? ? ? ? ? ? 4 (rn8 of @aa:8) 1 ? ? ? ? ? ? 4 (rn8 of @aa:16) 1 ? ? ? ? ? ? 5 (rn8 of @aa:32) 1 ? ? ? ? ? ? 6 (#xx:3 of rd8) 0 ? ? ? ? ? ? 1 (#xx:3 of @erd) 0 ? ? ? ? ? ? 4 (#xx:3 of @aa:8) 0 ? ? ? ? ? ? 4 (#xx:3 of @aa:16) 0 ? ? ? ? ? ? 5 (#xx:3 of @aa:32) 0 ? ? ? ? ? ? 6 (rn8 of rd8) 0 ? ? ? ? ? ? 1 (rn8 of @erd) 0 ? ? ? ? ? ? 4 (rn8 of @aa:8) 0 ? ? ? ? ? ? 4 (rn8 of @aa:16) 0 ? ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1099 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bclr bnot btst bclr rn,@aa:32 b 8 bnot #xx:3,rd b 2 bnot #xx:3,@erd b 4 bnot #xx:3,@aa:8 b 4 bnot #xx:3,@aa:16 b 6 bnot #xx:3,@aa:32 b 8 bnot rn,rd b 2 bnot rn,@erd b 4 bnot rn,@aa:8 b 4 bnot rn,@aa:16 b 6 bnot rn,@aa:32 b 8 btst #xx:3,rd b 2 btst #xx:3,@erd b 4 btst #xx:3,@aa:8 b 4 btst #xx:3,@aa:16 b 6 (rn8 of @aa:32) 0 ? ? ? ? ? ? 6 ( #xx:3 of rd8) [ ? (#xx:3 of rd8)] ? ? ? ? ? ? 1 (#xx:3 of @erd) ? ? ? ? ? ? 4 [ ? (#xx:3 of @erd)] (#xx:3 of @aa:8) ? ? ? ? ? ? 4 [ ? (#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? ? ? ? ? ? 5 [ ? (#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? ? ? ? ? ? 6 [ ? (#xx:3 of @aa:32)] (rn8 of rd8) [ ? (rn8 of rd8)] ? ? ? ? ? ? 1 (rn8 of @erd) [ ? (rn8 of @erd)] ? ? ? ? ? ? 4 (rn8 of @aa:8) [ ? (rn8 of @aa:8)] ? ? ? ? ? ? 4 (rn8 of @aa:16) ? ? ? ? ? ? 5 [ ? (rn8 of @aa:16)] (rn8 of @aa:32) ? ? ? ? ? ? 6 [ ? (rn8 of @aa:32)] ? (#xx:3 of rd8) z ? ? ? ? ? 1 ? (#xx:3 of @erd) z ? ? ? ? ? 3 ? (#xx:3 of @aa:8) z ? ? ? ? ? 3 ? (#xx:3 of @aa:16) z ? ? ? ? ? 4 operation condition code ihnzvc advanced no. of states * 1 ????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1100 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic btst bld bild bst btst #xx:3,@aa:32 b 8 btst rn,rd b 2 btst rn,@erd b 4 btst rn,@aa:8 b 4 btst rn,@aa:16 b 6 btst rn,@aa:32 b 8 bld #xx:3,rd b 2 bld #xx:3,@erd b 4 bld #xx:3,@aa:8 b 4 bld #xx:3,@aa:16 b 6 bld #xx:3,@aa:32 b 8 bild #xx:3,rd b 2 bild #xx:3,@erd b 4 bild #xx:3,@aa:8 b 4 bild #xx:3,@aa:16 b 6 bild #xx:3,@aa:32 b 8 bst #xx:3,rd b 2 bst #xx:3,@erd b 4 bst #xx:3,@aa:8 b 4 ? (#xx:3 of @aa:32) z ? ? ? ? ? 5 ? (rn8 of rd8) z ? ? ? ? ? 1 ? (rn8 of @erd) z ? ? ? ? ? 3 ? (rn8 of @aa:8) z ? ? ? ? ? 3 ? (rn8 of @aa:16) z ? ? ? ? ? 4 ? (rn8 of @aa:32) z ? ? ? ? ? 5 (#xx:3 of rd8) c ? ? ? ? ? 1 (#xx:3 of @erd) c ? ? ? ? ? 3 (#xx:3 of @aa:8) c ? ? ? ? ? 3 (#xx:3 of @aa:16) c ? ? ? ? ? 4 (#xx:3 of @aa:32) c ? ? ? ? ? 5 ? (#xx:3 of rd8) c ? ? ? ? ? 1 ? (#xx:3 of @erd) c ? ? ? ? ? 3 ? (#xx:3 of @aa:8) c ? ? ? ? ? 3 ? (#xx:3 of @aa:16) c ? ? ? ? ? 4 ? (#xx:3 of @aa:32) c ? ? ? ? ? 5 c (#xx:3 of rd8) ? ? ? ? ? ? 1 c (#xx:3 of @erd24) ? ? ? ? ? ? 4 c (#xx:3 of @aa:8) ? ? ? ? ? ? 4 operation condition code ihnzvc advanced no. of states * 1 ?????????? ??????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1101 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bst bist band biand bor bst #xx:3,@aa:16 b 6 bst #xx:3,@aa:32 b 8 bist #xx:3,rd b 2 bist #xx:3,@erd b 4 bist #xx:3,@aa:8 b 4 bist #xx:3,@aa:16 b 6 bist #xx:3,@aa:32 b 8 band #xx:3,rd b 2 band #xx:3,@erd b 4 band #xx:3,@aa:8 b 4 band #xx:3,@aa:16 b 6 band #xx:3,@aa:32 b 8 biand #xx:3,rd b 2 biand #xx:3,@erd b 4 biand #xx:3,@aa:8 b 4 biand #xx:3,@aa:16 b 6 biand #xx:3,@aa:32 b 8 bor #xx:3,rd b 2 bor #xx:3,@erd b 4 c (#xx:3 of @aa:16) ? ? ? ? ? ? 5 c (#xx:3 of @aa:32) ? ? ? ? ? ? 6 ? c (#xx:3 of rd8) ? ? ? ? ? ? 1 ? c (#xx:3 of @erd24) ? ? ? ? ? ? 4 ? c (#xx:3 of @aa:8) ? ? ? ? ? ? 4 ? c (#xx:3 of @aa:16) ? ? ? ? ? ? 5 ? c (#xx:3 of @aa:32) ? ? ? ? ? ? 6 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd24) c ? ? ? ? ? 3 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd24)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd24) c ? ? ? ? ? 3 operation condition code ihnzvc advanced no. of states * 1 ????????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1102 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bor bior bxor bixor bor #xx:3,@aa:8 b 4 bor #xx:3,@aa:16 b 6 bor #xx:3,@aa:32 b 8 bior #xx:3,rd b 2 bior #xx:3,@erd b 4 bior #xx:3,@aa:8 b 4 bior #xx:3,@aa:16 b 6 bior #xx:3,@aa:32 b 8 bxor #xx:3,rd b 2 bxor #xx:3,@erd b 4 bxor #xx:3,@aa:8 b 4 bxor #xx:3,@aa:16 b 6 bxor #xx:3,@aa:32 b 8 bixor #xx:3,rd b 2 bixor #xx:3,@erd b 4 bixor #xx:3,@aa:8 b 4 bixor #xx:3,@aa:16 b 6 bixor #xx:3,@aa:32 b 8 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd24)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd24) c ? ? ? ? ? 3 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd24)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1 ??????????????????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1103 of 1484 rej09b0103-0600 (6) branch instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bcc always ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 never ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c z=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c z=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 v=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bra d:8(bt d:8) ? 2 if condition is true then bra d:16(bt d:16) ? 4 pc pc+d brn d:8(bf d:8) ? 2 else next; brn d:16(bf d:16) ? 4 bhi d:8 ? 2 bhi d:16 ? 4 bls d:8 ? 2 bls d:16 ? 4 bcc d:b(bhs d:8) ? 2 bcc d:16(bhs d:16) ? 4 bcs d:8(blo d:8) ? 2 bcs d:16(blo d:16) ? 4 bne d:8 ? 2 bne d:16 ? 4 beq d:8 ? 2 beq d:16 ? 4 bvc d:8 ? 2 bvc d:16 ? 4
appendix a instruction set rev. 6.00 feb 22, 2005 page 1104 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bcc v=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n v=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n v=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z (n v)=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z (n v)=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bvs d:8 ? 2 bvs d:16 ? 4 bpl d:8 ? 2 bpl d:16 ? 4 bmi d:8 ? 2 bmi d:16 ? 4 bge d:8 ? 2 bge d:16 ? 4 blt d:8 ? 2 blt d:16 ? 4 bgt d:8 ? 2 bgt d:16 ? 4 ble d:8 ? 2 ble d:16 ? 4
appendix a instruction set rev. 6.00 feb 22, 2005 page 1105 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic jmp bsr jsr rts jmp @ern ? 2 jmp @aa:24 ? 4 jmp @@aa:8 ? 2 bsr d:8 ? 2 bsr d:16 ? 4 jsr @ern ? 2 jsr @aa:24 ? 4 jsr @@aa:8 ? 2 rts ? 2 pc ern ? ? ? ? ? ? pc aa:24 ? ? ? ? ? ? pc @aa:8 ? ? ? ? ? ? pc @-sp,pc pc+d:8 ? ? ? ? ? ? pc @-sp,pc pc+d:16 ? ? ? ? ? ? pc @-sp,pc ern ? ? ? ? ? ? pc @-sp,pc aa:24 ? ? ? ? ? ? pc @-sp,pc @aa:8 ? ? ? ? ? ? pc @sp+ ? ? ? ? ? ? operation condition code ihnzvc advanced no. of states * 1 2 3 5 4 5 4 5 6 5
appendix a instruction set rev. 6.00 feb 22, 2005 page 1106 of 1484 rej09b0103-0600 (7) system control instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic trapa rte sleep ldc trapa #xx:2 ? rte ? sleep ? ldc #xx:8,ccr b 2 ldc #xx:8,exr b 4 ldc rs,ccr b 2 ldc rs,exr b 2 ldc @ers,ccr w 4 ldc @ers,exr w 4 ldc @(d:16,ers),ccr w 6 ldc @(d:16,ers),exr w 6 ldc @(d:32,ers),ccr w 10 ldc @(d:32,ers),exr w 10 ldc @ers+,ccr w 4 ldc @ers+,exr w 4 ldc @aa:16,ccr w 6 ldc @aa:16,exr w 6 ldc @aa:32,ccr w 8 ldc @aa:32,exr w 8 pc @-sp,ccr @-sp, 1 ? ? ? ? ? 8 [13] exr @-sp, pc exr @sp+,ccr @sp+, 5 [13] pc @sp+ transition to power-down state ? ? ? ? ? ? 2 #xx:8 ccr 1 #xx:8 exr ? ? ? ? ? ? 2 rs8 ccr 1 rs8 exr ? ? ? ? ? ? 1 @ers ccr 3 @ers exr ? ? ? ? ? ? 3 @(d:16,ers) ccr 4 @(d:16,ers) exr ? ? ? ? ? ? 4 @(d:32,ers) ccr 6 @(d:32,ers) exr ? ? ? ? ? ? 6 @ers ccr,ers32+2 ers32 4 @ers exr,ers32+2 ers32 ? ? ? ? ? ? 4 @aa:16 ccr 4 @aa:16 exr ? ? ? ? ? ? 4 @aa:32 ccr 5 @aa:32 exr ? ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix a instruction set rev. 6.00 feb 22, 2005 page 1107 of 1484 rej09b0103-0600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic stc andc orc xorc nop stc ccr,rd b 2 stc exr,rd b 2 stc ccr,@erd w 4 stc exr,@erd w 4 stc ccr,@(d:16,erd) w 6 stc exr,@(d:16,erd) w 6 stc ccr,@(d:32,erd) w 10 stc exr,@(d:32,erd) w 10 stc ccr,@-erd w 4 stc exr,@-erd w 4 stc ccr,@aa:16 w 6 stc exr,@aa:16 w 6 stc ccr,@aa:32 w 8 stc exr,@aa:32 w 8 andc #xx:8,ccr b 2 andc #xx:8,exr b 4 orc #xx:8,ccr b 2 orc #xx:8,exr b 4 xorc #xx:8,ccr b 2 xorc #xx:8,exr b 4 nop ? 2 ccr rd8 ? ? ? ? ? ? 1 exr rd8 ? ? ? ? ? ? 1 ccr @erd ? ? ? ? ? ? 3 exr @erd ? ? ? ? ? ? 3 ccr @(d:16,erd) ? ? ? ? ? ? 4 exr @(d:16,erd) ? ? ? ? ? ? 4 ccr @(d:32,erd) ? ? ? ? ? ? 6 exr @(d:32,erd) ? ? ? ? ? ? 6 erd32-2 erd32,ccr @erd ? ? ? ? ? ? 4 erd32-2 erd32,exr @erd ? ? ? ? ? ? 4 ccr @aa:16 ? ? ? ? ? ? 4 exr @aa:16 ? ? ? ? ? ? 4 ccr @aa:32 ? ? ? ? ? ? 5 exr @aa:32 ? ? ? ? ? ? 5 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 pc pc+2 ? ? ? ? ? ? 1 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix a instruction set rev. 6.00 feb 22, 2005 page 1108 of 1484 rej09b0103-0600 (8) block transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic eepmov notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of r4l or r4. 3. only register er0, er1, er4, or er5 should be used when using the tas instruction. 4. only register er0 to er6 should be used when using the stm/ldm instruction. [1] seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] cannot be used in this lsi. [3] set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] retains its previous value when the result is zero; otherwise cleared to 0. [6] set to 1 when the divisor is negative; otherwise cleared to 0. [7] set to 1 when the divisor is zero; otherwise cleared to 0. [8] set to 1 when the quotient is negative; otherwise cleared to 0. [9] one additional state is required for execution when exr is valid. [10] mac instruction results are indicated in the flags when the stmac instruction is executed. [11] a maximum of three additional states are required for execution of one of these instructions within three states after ex ecution of a mac instruction. for example, if there is a one-state instruction (such as nop) between a mac instruction and one of these in structions, that instruction will be two states longer. eepmov.b ? 4 eepmov.w ? 4 if r4l 0 ? ? ? ? ? ? 4+2n * 2 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4l-1 r4l until r4l=0 else next; if r4 0 ? ? ? ? ? ? 4+2n * 2 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4-1 r4 until r4=0 else next; operation condition code ihnzvc advanced no. of states * 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1109 of 1484 rej09b0103-0600 a.2 instruction codes table a-2 shows the instruction codes.
appendix a instruction set rev. 6.00 feb 22, 2005 page 1110 of 1484 rej09b0103-0600 table a-2 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b ? ? ? ? 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0erd 0imm 0imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm
appendix a instruction set rev. 6.00 feb 22, 2005 page 1111 of 1484 rej09b0103-0600 bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0
appendix a instruction set rev. 6.00 feb 22, 2005 page 1112 of 1484 rej09b0103-0600 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm
appendix a instruction set rev. 6.00 feb 22, 2005 page 1113 of 1484 rej09b0103-0600 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs
appendix a instruction set rev. 6.00 feb 22, 2005 page 1114 of 1484 rej09b0103-0600 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b ? ? b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs
appendix a instruction set rev. 6.00 feb 22, 2005 page 1115 of 1484 rej09b0103-0600 btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b ? b b w w l l b b b w w l l b w b w ? ? 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0erd 0imm 0imm 0 0 7 6 6 7 7 7 6 6 0 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a 1 rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 a rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm
appendix a instruction set rev. 6.00 feb 22, 2005 page 1116 of 1484 rej09b0103-0600 exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l ? ? ? ? ? ? b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp abs abs disp disp
appendix a instruction set rev. 6.00 feb 22, 2005 page 1117 of 1484 rej09b0103-0600 0 0 rd abs rs rd ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm * 3 ldmac mac mov w w l l l l l ? b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 ers ers ern 0 0 0 0 ern+1 ern+2 ern+3 erm 0 0 0 0 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 3 3 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 2 3 6 rs 0 2 8 a 0 rs 0 1 0 0 0 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 6 b b d d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp
appendix a instruction set rev. 6.00 feb 22, 2005 page 1118 of 1484 rej09b0103-0600 mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * 1 mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs cannot be used in this lsi disp disp
appendix a instruction set rev. 6.00 feb 22, 2005 page 1119 of 1484 rej09b0103-0600 neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l ? b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm
appendix a instruction set rev. 6.00 feb 22, 2005 page 1120 of 1484 rej09b0103-0600 rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l ? ? b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd
appendix a instruction set rev. 6.00 feb 22, 2005 page 1121 of 1484 rej09b0103-0600 shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l ? b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp
appendix a instruction set rev. 6.00 feb 22, 2005 page 1122 of 1484 rej09b0103-0600 stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd * 2 trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm * 3 stmac sub subs subx tas trapa xor w w w w l l l l l b w w l l l l l b b b ? b b w w l l 1 00 ers imm 0 0 0 0 0 0 0 0 ers ers erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 2 2 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 2 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm
appendix a instruction set rev. 6.00 feb 22, 2005 page 1123 of 1484 rej09b0103-0600 xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm notes: bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. only register er0, er1, er4, or er5 should be used when using the tas instruction. only register er0 to er6 should be used when using the stm/ldm instruction. legend: address register 32-bit register register field general register register field general register register field general register 000 001 111 er0 er1 er7 0000 0001 0111 1000 1001 1111 r0 r1 r7 e0 e1 e7 0000 0001 0111 1000 1001 1111 r0h r1h r7h r0l r1l r7l 16-bit register 8-bit register imm: abs: disp: rs, rd, rn: ers, erd, ern, erm: the register fields specify general registers as follows. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn) register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to oper and symbols ers, erd, ern, and erm) 1. 2. 3.
appendix a instruction set rev. 6.00 feb 22, 2005 page 1124 of 1484 rej09b0103-0600 a.3 operation code map table a-3 shows the operation code map. instruction code 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(3) table a-3 operation code map (1)
appendix a instruction set rev. 6.00 feb 22, 2005 page 1125 of 1484 rej09b0103-0600 instruction code 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe * or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe * d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al table a.3(3) table a.3(3) table a.3(3) table a.3(4) table a.3(4) table a-3 operation code map (2) note: * cannot be used in this lsi .
appendix a instruction set rev. 6.00 feb 22, 2005 page 1126 of 1484 rej09b0103-0600 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification field. aa is the absolute address specification. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef 1. 2. bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist table a-3 operation code map (3)
appendix a instruction set rev. 6.00 feb 22, 2005 page 1127 of 1484 rej09b0103-0600 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef table a-3 operation code map (4)
appendix a instruction set rev. 6.00 feb 22, 2005 page 1128 of 1484 rej09b0103-0600 a.4 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the cpu. table a-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a-4 indicates the number of states required for each cycle. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffc7:8 from table a-5: i = l = 2, j = k = m = n = 0 from table a-4: s i = 4, s l = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table a-5: i = j = k = 2, l = m = n = 0 from table a-4: s i = s j = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24
appendix a instruction set rev. 6.00 feb 22, 2005 page 1129 of 1484 rej09b0103-0600 table a-4 number of states per cycle access conditions external device on-chip supporting module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 223 + m word data access s m 4 4 6 + 2m internal operation s n 111 1111 legend: m: number of wait states inserted into external device access
appendix a instruction set rev. 6.00 feb 22, 2005 page 1130 of 1484 rej09b0103-0600 table a-5 number of cycles in instruction execution instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.w rs,rd 1 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2
appendix a instruction set rev. 6.00 feb 22, 2005 page 1131 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1 bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2
appendix a instruction set rev. 6.00 feb 22, 2005 page 1132 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1 bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1133 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2 bsr bsr d:8 2 2 bsr d:16 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2
appendix a instruction set rev. 6.00 feb 22, 2005 page 1134 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac clrmac 1 1 * 3 cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19
appendix a instruction set rev. 6.00 feb 22, 2005 page 1135 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n eepmov eepmov.b 2 2n+2 * 2 eepmov.w 2 2n+2 * 2 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 2 2 1 jsr jsr @ern 2 2 jsr @aa:24 2 2 1 jsr @@aa:8 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1136 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n ldm ldm.l @sp+, (ern-ern+1) 24 1 ldm.l @sp+, (ern-ern+2) 26 1 ldm.l @sp+, (ern-ern+3) 28 1 ldmac ldmac ers,mach 1 1 * 3 ldmac ers,macl 1 1 * 3 mac mac @ern+,@erm+ 2 2 mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@-erd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1137 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@-erd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2 mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@-erd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 movfpe movfpe @:aa:16,rd can not be used in this lsi movtpe movtpe rs,@:aa:16 mulxs mulxs.b rs,rd 2 2 mulxs.w rs,erd 2 3 mulxu mulxu.b rs,rd 1 2 mulxu.w rs,erd 1 3 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1138 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1 rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1139 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3 * 1 1 rts rts 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1 shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1
appendix a instruction set rev. 6.00 feb 22, 2005 page 1140 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@-erd 2 1 1 stc.w exr,@-erd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm stm.l (ern-ern+1), @-sp 24 1 stm.l (ern-ern+2), @-sp 26 1 stm.l (ern-ern+3), @-sp 28 1 stmac stmac mach,erd 1 0 * 3 stmac macl,erd 1 0 * 3 sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas * 4 tas @erd 2 2 trapa trapa #x:2 2 2 2/3 * 1 2
appendix a instruction set rev. 6.00 feb 22, 2005 page 1141 of 1484 rej09b0103-0600 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc #xx:8,exr 2 notes: 1. 2 when exr is invalid, 3 when exr is valid. 2. when n bytes of data are transferred. 3. an internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction.
appendix a instruction set rev. 6.00 feb 22, 2005 page 1142 of 1484 rej09b0103-0600 a.5 bus states during instruction execution table a-6 indicates the types of cycles that occur during instruction execution by the cpu. see table a-4 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation, 1 state r:w ea 12345678 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address
appendix a instruction set rev. 6.00 feb 22, 2005 page 1143 of 1484 rej09b0103-0600 figure a-1 shows timing waveforms for the address bus and the rd , hwr , and lwr signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. a ddress bus rd hwr , lwr r:w 2nd fetching 2nd byte of instruction at jump address fetching 1nd byte of instruction at jump address fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a-1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states)
appendix a instruction set rev. 6.00 feb 22, 2005 page 1144 of 1484 rej09b0103-0600 instruction add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea 1 2 3 4 5 6 7 8 9 table a-6 instruction execution cycles
appendix a instruction set rev. 6.00 feb 22, 2005 page 1145 of 1484 rej09b0103-0600 instruction ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1146 of 1484 rej09b0103-0600 instruction bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1147 of 1484 rej09b0103-0600 instruction bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w :m stack (h) w:w stack (l) bsr d:16 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1148 of 1484 rej09b0103-0600 instruction 1 2 3 4 5 6 7 8 9 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac r:w next internal operation, 1 state cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next repeated n times * 2 exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next
appendix a instruction set rev. 6.00 feb 22, 2005 page 1149 of 1484 rej09b0103-0600 instruction inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern r:w next r:w ea w:w :m stack (h) w:w stack (l) jsr @aa:24 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state jsr @@aa:8 r:w next r:w:m aa:8 r:w aa:8 w:w :m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 (ern?ern+1) * 9 1 state ldm.l @sp+,(ern?ern+2) * 9 r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ern?ern+3) * 9 r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach r:w next internal operation, repeated n times * 3 1 state 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1150 of 1484 rej09b0103-0600 instruction ldmac ers,macl r:w next internal operation, 1 state mac @ern+,@erm+ r:w 2nd r:w next r:w eah r:w eam mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@ ? erd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@ ? erd r:w next internal operation, w:w ea 1 state mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1151 of 1484 rej09b0103-0600 instruction 1 2 3 4 5 6 7 8 9 mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@?erd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in this lsi movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 2 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 3 states mulxu.b rs,rd r:w next internal operation, 2 states mulxu.w rs,erd r:w next internal operation, 3 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next
appendix a instruction set rev. 6.00 feb 22, 2005 page 1152 of 1484 rej09b0103-0600 instruction pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 4 1 state rts r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 4 1 state shal.b rd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1153 of 1484 rej09b0103-0600 instruction shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation:m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@ ? erd r:w 2nd r:w next internal operation, w:w ea 1 state stc exr,@ ? erd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1154 of 1484 rej09b0103-0600 instruction stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ern ? ern+1),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern ? ern+2),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern ? ern+3),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd r:w next stmac macl,erd r:w next sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd * 8 r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1155 of 1484 rej09b0103-0600 instruction reset exception handling r:w vec r:w vec+2 internal operation, r:w * 5 1 state interrupt exception handling r:w * 6 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state notes: 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instruct ion. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. start address after return. 5. start address of the program. 6. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mod e the read operation is replaced by an internal operation. 7. start address of the interrupt-handling routine. 8. only register er0, er1, er4, or er5 should be used when using the tas instruction. 9. only register er0 to er6 should be used when using the stm/ldm instruction. 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 6.00 feb 22, 2005 page 1156 of 1484 rej09b0103-0600 a.6 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands si di ri dn ? 0 1 * z' c' the i-th bit of the source operand the i-th bit of the destination operand the i-th bit of the result the specified bit in the destination operand not affected modified according to the result of the instruction (see definition) always cleared to 0 always set to 1 undetermined (no guaranteed value) z flag before instruction execution c flag before instruction execution
appendix a instruction set rev. 6.00 feb 22, 2005 page 1157 of 1484 rej09b0103-0600 table a-7 condition code modification instruction h n z v c definition add h = sm?4 dm?4 + dm?4 rmC4 + sm?4 rmC4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm adds ????? addx h = sm?4 dm?4 + dm?4 rmC4 + sm?4 rmC4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm and ? 0? n = rm z = rm rmC1 ...... r0 andc stores the corresponding bits of the result. no flags change when the operand is exr. band ???? c = c' dn bcc ????? bclr ????? biand ???? c = c' dn bild ???? c = dn bior ???? c = c' + dn bist ????? bixor ???? c = c' dn + c' dn bld ???? c = dn bnot ????? bor ???? c = c' + dn bset ????? bsr ????? bst ????? btst ? ? ?? z = dn bxor ???? c = c' dn + c' dn
appendix a instruction set rev. 6.00 feb 22, 2005 page 1158 of 1484 rej09b0103-0600 instruction h n z v c definition clrmac ????? cmp h = sm?4 dmC4 + dmC4 rm?4 + sm?4 rm?4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm daa * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic carry das * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic borrow dec ? ?n = rm z = rm rmC1 ...... r0 v = dm rm divxs ? ? ? n = sm dm + sm dm z = sm smC1 ...... s0 divxu ? ?? n = sm z = sm smC1 ...... s0 eepmov ????? exts ? 0? n = rm z = rm rmC1 ...... r0 extu ? 0 0? z = rm rmC1 ...... r0 inc ? ?n = rm z = rm rmC1 ...... r0 v = dm rm jmp ????? jsr ????? ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ????? ldmac ????? mac ?????
appendix a instruction set rev. 6.00 feb 22, 2005 page 1159 of 1484 rej09b0103-0600 instruction h n z v c definition mov ? 0? n = rm z = rm rmC1 ...... r0 movfpe can not be used in this lsi. movtpe mulxs ? ? ? n = r2m z = r2m r2mC1 ...... r0 mulxu ????? neg h = dm?4 + rm?4 n = rm z = rm rmC1 ...... r0 v = dm rm c = dm + rm nop ????? not ? 0? n = rm z = rm rmC1 ...... r0 or ? 0? n = rm z = rm rmC1 ...... r0 orc stores the corresponding bits of the result. no flags change when the operand is exr. pop ? 0? n = rm z = rm rmC1 ...... r0 push ? 0? n = rm z = rm rmC1 ...... r0 rotl ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm?1 (2-bit shift) rotr ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift)
appendix a instruction set rev. 6.00 feb 22, 2005 page 1160 of 1484 rej09b0103-0600 instruction h n z v c definition rotxl ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm?1 (2-bit shift) rotxr ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts ????? shal ? n = rm z = rm rmC1 ...... r0 v = dm dm?1 + dm dmC1 (1-bit shift) v = dm dm?1 dm?2 dm dmC1 dmC2 (2-bit shift) c = dm (1-bit shift) or c = dm?1 (2-bit shift) shar ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) shll ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm?1 (2-bit shift) shlr ? 0 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep ????? stc ????? stm ????? stmac ? ? n = 1 if mac instruction resulted in negative value in mac register z = 1 if mac instruction resulted in zero value in mac register v = 1 if mac instruction resulted in overflow
appendix a instruction set rev. 6.00 feb 22, 2005 page 1161 of 1484 rej09b0103-0600 instruction h n z v c definition sub h = sm?4 dmC4 + dmC4 rm?4 + sm?4 rm?4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm subs ????? subx h = sm?4 dmC4 + dmC4 rm?4 + sm?4 rm?4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm tas ? 0? n = dm z = dm dmC1 ...... d0 trapa ????? xor ? 0? n = rm z = rm rmC1 ...... r0 xorc stores the corresponding bits of the result. no flags change when the operand is exr.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1162 of 1484 rej09b0103-0600 appendix b internal i/o register b.1 address address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width mra sm1 sm0 dm1 dm0 md1 md0 dts sz dtc * 7 8/16/32 h'ebc0 to h'efbf mrb chne disel ?????? sar dar cra crb h'f800 mcr0 mcr7 ? mcr5 ? ? mcr2 mcr1 mcr0 hcan0 8/16 h'f801gsr0????gsr3gsr2gsr1gsr0 h'f802 bcr0 bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 h'f803 bcr15 bcr14 bcr13 bcr12 bcr11 bcr10 bcr9 bcr8 h'f804 mbcr mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? h'f805 mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 h'f806 txpr txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? h'f807 txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 h'f808 txcr txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? h'f809 txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 h'f80a txack txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? h'f80b txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 h'f80c aback aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? h'f80d aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 h'f80e rxpr rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 h'f80f rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8 h'f810 rfpr rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 hcan0 8/16 h'f811 rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 h'f812 irr irr7 irr6 irr5 irr4 irr3 irr2 irr1 irr0 h'f813 ???irr12??irr9irr8 h'f814 mbimr mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 h'f815 mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 h'f816 imr imr7 imr6 imr5 imr4 imr3 imr2 imr1 ? h'f817 ???imr12??imr9imr8 h'f818 rec h'f819 tec
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1163 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f81a umsr umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 hcan0 8/16 h'f81b umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 h'f81c lafml lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 h'f81d lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 h'f81e lafmh lafmh7 lafmh6 lafmh5 ? ? ? lafmh1 lafmh0 h'f81f lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 h'f820mc0[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f821mc0[2]???????? h'f822mc0[3]???????? h'f823mc0[4]???????? h'f824 mc0[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f825 mc0[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f826 mc0[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f827 mc0[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f828mc1[1]????dlc3dlc2dlc1dlc0 h'f829mc1[2]???????? h'f82amc1[3]???????? h'f82bmc1[4]???????? h'f82c mc1[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f82d mc1[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f82e mc1[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f82f mc1[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f830mc2[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f831mc2[2]???????? h'f832mc2[3]???????? h'f833mc2[4]???????? h'f834 mc2[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f835 mc2[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f836 mc2[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f837 mc2[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f838mc3[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f839mc3[2]???????? h'f83amc3[3]???????? h'f83bmc3[4]???????? h'f83c mc3[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f83d mc3[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f83e mc3[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f83f mc3[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1164 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f840mc4[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f841mc4[2]???????? h'f842mc4[3]???????? h'f843mc4[4]???????? h'f844 mc4[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f845 mc4[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f846 mc4[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f847 mc4[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f848mc5[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f849mc5[2]???????? h'f84amc5[3]???????? h'f84bmc5[4]???????? h'f84c mc5[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f84d mc5[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f84e mc5[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f84f mc5[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f850mc6[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f851mc6[2]???????? h'f852mc6[3]???????? h'f853mc6[4]???????? h'f854 mc6[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f855 mc6[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f856 mc6[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f857 mc6[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f858mc7[1]????dlc3dlc2dlc1dlc0 h'f859mc7[2]???????? h'f85amc7[3]???????? h'f85bmc7[4]???????? h'f85c mc7[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f85d mc7[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f85e mc7[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f85f mc7[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f860mc8[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f861mc8[2]???????? h'f862mc8[3]???????? h'f863mc8[4]???????? h'f864 mc8[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f865 mc8[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f866 mc8[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f867 mc8[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1165 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f868mc9[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f869mc9[2]???????? h'f86amc9[3]???????? h'f86bmc9[4]???????? h'f86c mc9[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f86d mc9[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f86e mc9[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f86f mc9[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f870mc10[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f871mc10[2]???????? h'f872mc10[3]???????? h'f873mc10[4]???????? h'f874 mc10[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f875 mc10[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f876 mc10[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f877 mc10[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f878mc11[1]????dlc3dlc2dlc1dlc0 h'f879mc11[2]???????? h'f87amc11[3]???????? h'f87bmc11[4]???????? h'f87c mc11[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f87d mc11[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f87e mc11[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f87f mc11[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f880mc12[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f881mc12[2]???????? h'f882mc12[3]???????? h'f883mc12[4]???????? h'f884 mc12[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f885 mc12[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f886 mc12[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f887 mc12[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f888mc13[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f889mc13[2]???????? h'f88amc13[3]???????? h'f88bmc13[4]???????? h'f88c mc13[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f88d mc13[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f88e mc13[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f88f mc13[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1166 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f890mc14[1]????dlc3dlc2dlc1dlc0hcan08/16 h'f891mc14[2]???????? h'f892mc14[3]???????? h'f893mc14[4]???????? h'f894 mc14[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f895 mc14[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f896 mc14[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f897 mc14[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f898mc15[1]????dlc3dlc2dlc1dlc0 h'f899mc15[2]???????? h'f89amc15[3]???????? h'f89bmc15[4]???????? h'f89c mc15[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'f89d mc15[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'f89e mc15[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'f89f mc15[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'f8b0 md01 hcan0 8/16 h'f8b1 md02 h'f8b2 md03 h'f8b3 md04 h'f8b4 md05 h'f8b5 md06 h'f8b6 md07 h'f8b7 md08 h'f8b8 md11 hcan0 8/16 h'f8b9 md12 h'f8ba md13 h'f8bb md14 h'f8bc md15 h'f8bd md16 h'f8be md17 h'f8bf md18 h'f8c0 md21 hcan0 8/16 h'f8c1 md22 h'f8c2 md23 h'f8c3 md24 h'f8c4 md25 h'f8c5 md26 h'f8c6 md27 h'f8c7 md28
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1167 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f8c8 md31 hcan0 8/16 h'f8c9 md32 h'f8ca md33 h'f8cb md34 h'f8cc md35 h'f8cd md36 h'f8ce md37 h'f8cf md38 h'f8d0 md41 hcan0 8/16 h'f8d1 md42 h'f8d2 md43 h'f8d3 md44 h'f8d4 md45 h'f8d5 md46 h'f8d6 md47 h'f8d7 md48 h'f8d8 md51 hcan0 8/16 h'f8d9 md52 h'f8da md53 h'f8db md54 h'f8dc md55 h'f8dd md56 h'f8de md57 h'f8df md58 h'f8e0 md61 hcan0 8/16 h'f8e1 md62 h'f8e2 md63 h'f8e3 md64 h'f8e4 md65 h'f8e5 md66 h'f8e6 md67 h'f8e7 md68 h'f8e8 md71 hcan0 8/16 h'f8e9 md72 h'f8ea md73 h'f8eb md74 h'f8ec md75 h'f8ed md76 h'f8ee md77 h'f8ef md78
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1168 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f8f0 md81 hcan0 8/16 h'f8f1 md82 h'f8f2 md83 h'f8f3 md84 h'f8f4 md85 h'f8f5 md86 h'f8f6 md87 h'f8f7 md88 h'f8f8 md91 hcan0 8/16 h'f8f9 md92 h'f8fa md93 h'f8fb md94 h'f8fc md95 h'f8fd md96 h'f8fe md97 h'f8ff md98 h'f900 md101 hcan0 8/16 h'f901 md102 h'f902 md103 h'f903 md104 h'f904 md105 h'f905 md106 h'f906 md107 h'f907 md108 h'f908 md111 hcan0 8/16 h'f909 md112 h'f90a md113 h'f90b md114 h'f90c md115 h'f90d md116 h'f90e md117 h'f90f md118 h'f910 md121 hcan0 8/16 h'f911 md122 h'f912 md123 h'f913 md124 h'f914 md125 h'f915 md126 h'f916 md127 h'f917 md128
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1169 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f918 md131 hcan0 8/16 h'f919 md132 h'f91a md133 h'f91b md134 h'f91c md135 h'f91d md136 h'f91e md137 h'f91f md138 h'f920 md141 hcan0 8/16 h'f921 md142 h'f922 md143 h'f923 md144 h'f924 md145 h'f925 md146 h'f926 md147 h'f927 md148 h'f928 md151 h'f929 md152 h'f92a md153 h'f92b md154 h'f92c md155 h'f92d md156 h'f92e md157 h'f92f md158 h'fa00 mcr mcr7 ? mcr5 ? ? mcr2 mcr1 mcr0 hcan1 * 7 8/16 h'fa01gsr????gsr3gsr2gsr1gsr0 h'fa02 bcr bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 h'fa03 bcr15 bcr14 bcr13 bcr12 bcr11 bcr10 bcr9 bcr8 h'fa04 mbcr mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? h'fa05 mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 h'fa06 txpr txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? h'fa07 txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 h'fa08 txcr txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? h'fa09 txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 h'fa0a txack txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? h'fa0b txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 h'fa0c aback aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? h'fa0d aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 h'fa0e rxpr rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 h'fa0f rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1170 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fa10 rfpr rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 hcan1 * 7 8/16 h'fa11 rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 h'fa12 irr irr7 irr6 irr5 irr4 irr3 irr2 irr1 irr0 h'fa13 ???irr12??irr9irr8 h'fa14 mbimr mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 h'fa15 mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 h'fa16 imr imr7 imr6 imr5 imr4 imr3 imr2 imr1 imr0 h'fa17 ???imr12??imr9imr8 h'fa18 rec h'fa19 tec h'fa1a umsr umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 h'fa1b umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 h'fa1c lafml lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 h'fa1d lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 h'fa1e lafmh lafmh7 lafmh6 lafmh5 ? ? ? lafmh1 lafmh0 h'fa1f lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 h'fa20mc0[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa21mc0[2]???????? h'fa22mc0[3]???????? h'fa23mc0[4]???????? h'fa24 mc0[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa25 mc0[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa26 mc0[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa27 mc0[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa28mc1[1]????dlc3dlc2dlc1dlc0 h'fa29mc1[2]???????? h'fa2amc1[3]???????? h'fa2bmc1[4]???????? h'fa2c mc1[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa2d mc1[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa2e mc1[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa2f mc1[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa30mc2[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa31mc2[2]???????? h'fa32mc2[3]???????? h'fa33mc2[4]???????? h'fa34 mc2[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa35 mc2[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa36 mc2[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa37 mc2[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa38mc3[1]????dlc3dlc2dlc1dlc0 h'fa39mc3[2]????????
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1171 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fa3amc3[3]???????? hcan1 * 7 8/16 h'fa3bmc3[4]???????? h'fa3c mc3[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa3d mc3[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa3e mc3[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa3f mc3[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa40mc4[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa41mc4[2]???????? h'fa42mc4[3]???????? h'fa43mc4[4]???????? h'fa44 mc4[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa45 mc4[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa46 mc4[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa47 mc4[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa48mc5[1]????dlc3dlc2dlc1dlc0 h'fa49mc5[2]???????? h'fa4amc5[3]???????? h'fa4bmc5[4]???????? h'fa4c mc5[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa4d mc5[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa4e mc5[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa4f mc5[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa50mc6[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa51mc6[2]???????? h'fa52mc6[3]???????? h'fa53mc6[4]???????? h'fa54 mc6[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa55 mc6[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa56 mc6[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa57 mc6[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa58mc7[1]????dlc3dlc2dlc1dlc0 h'fa59mc7[2]???????? h'fa5amc7[3]???????? h'fa5bmc7[4]???????? h'fa5c mc7[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa5d mc7[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa5e mc7[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa5f mc7[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1172 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fa60mc8[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa61mc8[2]???????? h'fa62mc8[3]???????? h'fa63mc8[4]???????? h'fa64 mc8[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa65 mc8[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa66 mc8[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa67 mc8[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa68mc9[1]????dlc3dlc2dlc1dlc0 h'fa69mc9[2]???????? h'fa6amc9[3]???????? h'fa6bmc9[4]???????? h'fa6c mc9[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa6d mc9[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa6e mc9[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa6f mc9[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa70mc10[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa71mc10[2]???????? h'fa72mc10[3]???????? h'fa73mc10[4]???????? h'fa74 mc10[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa75 mc10[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa76 mc10[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa77 mc10[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa78mc11[1]????dlc3dlc2dlc1dlc0 h'fa79mc11[2]???????? h'fa7amc11[3]???????? h'fa7bmc11[4]???????? h'fa7c mc11[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa7d mc11[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa7e mc11[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa7f mc11[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa80mc12[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa81mc12[2]???????? h'fa82mc12[3]???????? h'fa83mc12[4]???????? h'fa84 mc12[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa85 mc12[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa86 mc12[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa87 mc12[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa88mc13[1]????dlc3dlc2dlc1dlc0 h'fa89mc13[2]????????
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1173 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fa8amc13[3]???????? hcan1 * 7 8/16 h'fa8bmc13[4]???????? h'fa8c mc13[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa8d mc13[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa8e mc13[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa8f mc13[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa90mc14[1]????dlc3dlc2dlc1dlc0hcan1 * 7 8/16 h'fa91mc14[2]???????? h'fa92mc14[3]???????? h'fa93mc14[4]???????? h'fa94 mc14[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa95 mc14[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa96 mc14[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa97 mc14[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fa98mc15[1]????dlc3dlc2dlc1dlc0 h'fa99mc15[2]???????? h'fa9amc15[3]???????? h'fa9bmc15[4]???????? h'fa9c mc15[5] std_id2 std_id1 std_id0 rtr ide ? exd_id17 exd_id16 h'fa9d mc15[6] std_id10 std_id9 std_id8 std_id7 std_id6 std_id5 std_id4 std_id3 h'fa9e mc15[7] exd_id7 exd_id6 exd_id5 exd_id4 exd_id3 exd_id2 exd_id1 exd_id0 h'fa9f mc15[8] exd_id15 exd_id14 exd_id13 exd_id12 exd_id11 exd_id10 exd_id9 exd_id8 h'fab0 md01 hcan1 * 7 8/16 h'fab1 md02 h'fab2 md03 h'fab3 md04 h'fab4 md05 h'fab5 md06 h'fab6 md07 h'fab7 md08 h'fab8 md11 h'fab9 md12 h'faba md13 h'fabb md14 h'fabc md15 h'fabd md16 h'fabe md17 h'fabf md18
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1174 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fac0 md21 hcan1 * 7 8/16 h'fac1 md22 h'fac2 md23 h'fac3 md24 h'fac4 md25 h'fac5 md26 h'fac6 md27 h'fac7 md28 h'fac8 md31 h'fac9 md32 h'faca md33 h'facb md34 h'facc md35 h'facd md36 h'face md37 h'facf md38 h'fad0 md41 hcan1 * 7 8/16 h'fad1 md42 h'fad2 md43 h'fad3 md44 h'fad4 md45 h'fad5 md46 h'fad6 md47 h'fad7 md48 h'fad8 md51 h'fad9 md52 h'fada md53 h'fadb md54 h'fadc md55 h'fadd md56 h'fade md57 h'fadf md58 h'fae0 md61 hcan1 * 7 8/16 h'fae1 md62 h'fae2 md63 h'fae3 md64 h'fae4 md65 h'fae5 md66 h'fae6 md67 h'fae7 md68 h'fae8 md71 h'fae9 md72
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1175 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'faea md73 hcan1 * 7 8/16 h'faeb md74 h'faec md75 h'faed md76 h'faee md77 h'faef md78 h'faf0 md81 hcan1 * 7 8/16 h'faf1 md82 h'faf2 md83 h'faf3 md84 h'faf4 md85 h'faf5 md86 h'faf6 md87 h'faf7 md88 h'faf8 md91 h'faf9 md92 h'fafa md93 h'fafb md94 h'fafc md95 h'fafd md96 h'fafe md97 h'faff md98 h'fb00 md101 hcan1 * 7 8/16 h'fb01 md102 h'fb02 md103 h'fb03 md104 h'fb04 md105 h'fb05 md106 h'fb06 md107 h'fb07 md108 h'fb08 md111 h'fb09 md112 h'fb0a md113 h'fb0b md114 h'fb0c md115 h'fb0d md116 h'fb0e md117 h'fb0f md118
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1176 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fb10 md121 hcan1 * 7 8/16 h'fb11 md122 h'fb12 md123 h'fb13 md124 h'fb14 md125 h'fb15 md126 h'fb16 md127 h'fb17 md128 h'fb18 md131 h'fb19 md132 h'fb1a md133 h'fb1b md134 h'fb1c md135 h'fb1d md136 h'fb1e md137 h'fb1f md138 h'fb20 md141 hcan1 * 7 8/16 h'fb21 md142 h'fb22 md143 h'fb23 md144 h'fb24 md145 h'fb25 md146 h'fb26 md147 h'fb27 md148 h'fb28 md151 h'fb29 md152 h'fb2a md153 h'fb2b md154 h'fb2c md155 h'fb2d md156 h'fb2e md157 h'fb2f md158
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1177 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fc00 pwcr1 ? ? ie cmf cst cks2 cks1 cks0 16 h'fc02 pwocr1 oe1h oe1g oe1f oe1e oe1d oe1c oe1b oe1a h'fc04 pwpr1 ops1h ops1g ops1f ops1e ops1d ops1c ops1b ops1a motor control pw m timer 1 h'fc06pwcyr1?????? h'fc08pwbfr1a???ots??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc0apwbfr1c???ots??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc0cpwbfr1e???ots??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc0epwbfr1g???ots??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc10 pwcr2 ? ? ie cmf cst cks2 cks1 cks0 16 h'fc12 pwocr2 oe2h oe2g oe2f oe2e oe2d oe2c oe2b oe2a h'fc14 pwpr2 ops2h ops2g ops2f ops2e ops2d ops2c ops2b ops2a motor control pw m timer 2 h'fc16pwcyr2?????? h'fc18pwbfr2a???tds??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc1apwbfr2b???tds??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc1cpwbfr2c???tds??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc1epwbfr2d???tds??dt9dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 h'fc20 phddr ph7ddr ph6ddr ph5ddr ph4ddr ph3ddr ph2ddr ph1ddr ph0ddr port 16 h'fc21 pjddr pj7ddr pj6ddr pj5ddr pj4ddr pj3ddr pj2ddr pj1ddr pj0ddr h'fc24 phdr ph7dr ph6dr ph5dr ph4dr ph3dr ph2dr ph1dr ph0dr h'fc25 pjdr pj7dr pj6dr pj5dr pj4dr pj3dr pj2dr pj1dr pj0dr h'fc28 porth ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 h'fc29 portj pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1178 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fc60mstpcrdmstpd7??????? system 8 h'fdb4 sckx * 4 ? iicx1 iicx0 iice ? ? ? ? iic * 4 8 h'fdb5 ddcswr * 4 swe sw ie if clr3 clr2 clr1 clr0 h'fde4 sbycr ssby sts2 sts1 sts0 ope ? ? ? system 8 h'fde5 syscr macs ? intm1 intm0 nmieg ? ? rame h'fde6sckcrpstop???stcssck2sck1sck0 h'fde7mdcr?????mds2mds1mds1 h'fde8 mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 h'fde9 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 h'fdea mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 h'fdebpfcr????ae3ae2ae1ae0 h'fdec lpwrcr dton * 3 lson * 3 nesel * 3 substp * 3 rfcut * 3 ? stc1 stc0 h'fe00bara???????? pbc * 7 8 h'fe01 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'fe02 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'fe03 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 h'fe04barb???????? h'fe05 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'fe06 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'fe07 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 h'fe08 bcra cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea h'fe09 bcrb cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea h'fe12iscrh????irq5scbirq5scairq4scbirq4scaint8 h'fe13 iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca h'fe14 ier ? ? irq5e irq4e irq3e irq2e irq1e irq0e h'fe15 isr ? ? irq5f irq4f irq3f irq2f irq1f irq0f h'fe16 dtcera dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 dtc * 7 8 h'fe17 dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 h'fe18 dtcerc dtcec7 dtcec6 dtcec5 dtcec4 dtcec3 dtcec2 dtcec1 dtcec0 h'fe19 dtcerd dtced7 dtced6 dtced5 dtced4 dtced3 dtced2 dtced1 dtced0 h'fe1a dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 h'fe1b dtcerf dtcef7 dtcef6 dtcef5 dtcef4 dtcef3 dtcef2 dtcef1 dtcef0 h'fe1c dtcerg dtceg7 dtceg6 dtceg5 dtceg4 dtceg3 dtceg2 dtceg1 dtceg0 h'fe1f dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'fe26 pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg * 7 8 h'fe27 pmr g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov h'fe28 nderh nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fe29 nderl nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fe2a podrh pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 h'fe2b podrl pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 h'fe2c ndrh ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 h'fe2d ndrl ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1179 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fe2e ndrh ???? ndr11 ndr10 ndr9 ndr8 ppg * 7 8 h'fe2f ndrl ???? ndr3 ndr2 ndr1 ndr0 h'fe30 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port 8 h'fe32 p3ddr ? ? p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'fe39paddr????pa3ddrpa2ddrpa1ddrpa0ddr h'fe3a pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'fe3b pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'fe3c pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'fe3d peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'fe3e pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr ? ? pf0ddr h'fe40 papcr ????pa3pcrpa2pcrpa1pcrpa0pcrport8 h'fe41 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'fe42 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'fe43 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'fe44 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'fe46 p3odr ? ? p35odr p34odr p33odr p32odr p31odr p30odr h'fe47paodr????pa3odrpa2odrpa1odrpa0odr h'fe48 pbodr pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr h'fe49 pcodr pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr h'fe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 8/16 h'fe81 tmdr3 ? ? bfb bfa md3 md2 md1 md0 h'fe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'fe84 tier3 ttge ? ? tciev tgied tgiec tgieb tgiea h'fe85tsr3???tcfvtgfdtgfctgfbtgfa h'fe86 tcnt3 h'fe87 h'fe88 tgr3a h'fe89 h'fe8a tgr3b h'fe8b h'fe8c tgr3c h'fe8d h'fe8e tgr3d h'fe8f h'fe90 tcr4 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu4 8/16 h'fe91tmdr4????md3md2md1md0 h'fe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe94 tier4 ttge ? tcieu tciev ? ? tgieb tgiea h'fe95 tsr4 tcfd ? tcfu tcfv ? ? tgfb tgfa
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1180 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fe96 tcnt4 tpu4 8/16 h'fe97 h'fe98 tgr4a h'fe99 h'fe9a tgr4b h'fe9b h'fea0 tcr5 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 8/16 h'fea1tmdr5????md3md2md1md0 h'fea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fea4 tier5 ttge ? tcieu tciev ? ? tgieb tgiea h'fea5 tsr5 tcfd ? tcfu tcfv ? ? tgfb tgfa h'fea6 tcnt5 h'fea7 h'fea8 tgr5a h'fea9 h'feaa tgr5b h'feab h'feb0 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tpu all 8 h'feb1 tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 h'fec0 ipra ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int 8 h'fec1 iprb ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec2iprc?????ipr2 * 7 ipr1 * 7 ipr0 * 7 h'fec3 iprd ? ipr6 ipr5 ipr4 ? ? ? ? h'fec4 ipre ? ipr6 * 7 ipr5 * 7 ipr4 * 7 ? ipr2 ipr1 ipr0 h'fec5 iprf ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec6 iprg ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec7 iprh ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec9iprj?????ipr2ipr1ipr0 h'feca iprk ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fecc iprm ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fece reserved h'fed0 abw cr abw 7 abw 6 abw 5 abw 4 abw 3 abw 2 abw 1 abw 0 8 h'fed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 bus controller h'fed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 h'fed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 h'fed4 bcrh icis1 icis0 brstrm brsts1 brsts0 ? ? ? h'fed5bcrl??????wdbe? h'fedbramer????ramsram2ram1ram0rom8 h'ff00 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port 8 h'ff02 p3dr ? ? p35dr p34dr p33dr p32dr p31dr p30dr h'ff09padr????pa3drpa2drpa1drpa0dr
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1181 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff0a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr port 8 h'ff0b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff0c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ff0d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ff0e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr ? ? pf0dr h'ff10 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 8/16 h'ff11 tmdr0 ? ? bfb bfa md3 md2 md1 md0 h'ff12 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff13 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ff14 tier0 ttge ? ? tciev tgied tgiec tgieb tgiea h'ff15tsr0???tcfvtgfdtgfctgfbtgfa h'ff16 tnct0 h'ff17 h'ff18 tgr0a h'ff19 h'ff1a tgr0b h'ff1b h'ff1c tgr0c h'ff1d h'ff1e tgr0d h'ff1f h'ff20 tcr1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 8/16 h'ff21tmdr1????md3md2md1md0 h'ff22 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff24 tier1 ttge ? tcieu tciev ? ? tgieb tgiea h'ff25 tsr1 tcfd ? tcfu tcfv ? ? tgfb tgfa h'ff26 tnct1 h'ff27 h'ff28 tgr1a h'ff29 h'ff2a tgr1b h'ff2b h'ff30 tcr2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 8/16 h'ff31tmdr2????md3md2md1md0 h'ff32 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff34 tier2 ttge ? tcieu tciev ? ? tgieb tgiea h'ff35 tsr2 tcfd ? tcfu tcfv ? ? tgfb tgfa h'ff36 tnct2 h'ff37 h'ff38 tgr2a h'ff39 h'ff3a tgr2b h'ff3b
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1182 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff74 (read/write) tcsr0 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt0 8 h'ff75 (read) tcnt0 h'ff76????????? h'ff77 (read) rstcsr0wovfrste?????? h'ff78 smr0 c/ a chr pe o/ e stop mp cks1 cks0 8 smr0 gm blk pe o/ e bcp1 bcp0 cks1 cks0 iccr0 * 4 ice ieic mst trs acke bbsy iric scp h'ff79 brr0 icsr0 * 4 estp stop irtr aasx al aas adz ackb sci0, iic0 * 4 , smart card interface 0 h'ff7a scr0 tie rie te re mpie teie cke1 cke0 h'ff7b tdr0 h'ff7c ssr0 tdre rdrf orer fer per tend mpb mpbt ssr0 tdre rdrf orer ers per tend mpb mpbt h'ff7d rdr0 h'ff7escmr0????sdirsinv?smif icdr0/ sarx0 * 4 icdr7/ svax6 icdr6/ svax5 icdr5/ svax4 icdr4/ svax3 icdr3/ svax2 icdr2/ svax1 icdr1/ svax0 icdr0/fsx h'ff7f icmr0/ sar0 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/fs iic0 * 4 h'ff80 smr1 c/ a chr pe o/ e stop mp cks1 cks0 8 smr1 gm blk pe o/ e bcp1 bcp0 cks1 cks0 iccr1 * 4 ice ieic mst trs acke bbsy iric scp h'ff81 brr1 sci1, iic1 * 4 , smart card interface 1 icsr1 * 4 estp stop irtr aasx al aas adz ackb h'ff82 scr1 tie rie te re mpie teie cke1 cke0 h'ff83 tdr1 h'ff84 ssr1 tdre rdrf orer fer per tend mpb mpbt ssr1 tdre rdrf orer ers per tend mpb mpbt h'ff85 rdr1 h'ff86scmr1????sdirsinv?smif icdr1/ sarx1 * 4 icdr7/ svarx6 icdr6/ svarx5 icdr5/ svarx4 icdr4/ svarx3 icdr3/ svarx2 icdr2/ svarx1 icdr1/ svarx0 icdr0/fsx h'ff87 icmr1/ sar1 * 4 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/fs iic1 * 4 h'ff88 smr2 c/ a chr pe o/ e stop mp cks1 cks0 8 smr2 gm blk pe o/ e bcp1 bcp0 cks1 cks0 h'ff89 brr2 sci2, smart card interface 2 h'ff8a scr2 tie rie te re mpie teie cke1 cke0 h'ff8b tdr2 h'ff8c ssr2 tdre rdrf orer fer per tend mpb mpbt ssr2 tdre rdrf orer ers per tend mpb mpbt h'ff8d rdr2 h'ff8escmr2????sdirsinv?smif
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1183 of 1484 rej09b0103-0600 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8 h'ff91 addral ad1 ad0 ?????? h'ff92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff93 addrbl ad1 ad0 ?????? h'ff94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff95 addrcl ad1 ad0 ?????? h'ff96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff97 addrdl ad1 ad0 ?????? h'ff98 adcsr adf adie adst scan ch3 ch2 ch1 ch0 h'ff99 adcr trgs1 trgs0 ? ? cks1 cks0 ? ? h'ffa2 (read/write) tcsr1 ovf wt/ it tme pss * 1 rst/ nmi cks2 cks1 cks0 wdt1 16 h'ffa3 (read) tcnt1 h'ffa4 dadr0 d/a0, 1 8 h'ffa5 dadr1 h'ffa6 dacr01 daoe1 daoe0 dae ? ? ? ? ? h'ffa8 flmcr1 fwe swe esu psu ev pv e p flash 8 h'ffa9flmcr2fler??????? h'ffaa ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffab ebr2 ? ? eb13 * 8 eb12 * 8 eb11 * 6 eb10 * 5 eb9 eb8 h'ffac flpwcr pdwnd * 2 ??????? h'ffb0 port1 p17 p16 p15 p14 p13 p12 p11 p10 port 8 h'ffb2 port3 ? ? p35 p34 p33 p32 p31 p30 h'ffb3 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ffb8port9????p93p92p91p90 h'ffb9porta????pa3pa2pa1pa0 h'ffba portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ffbb portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ffbc portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ffbd porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ffbe portf pf7 pf6 pf5 pf4 pf3 ? ? pf0 notes: 1. bit 4 (pss) in tcsr of wdt1 is valid in the u-mask and w-mask versions, and h8s/2635 group. in versions other than the u-mask and w-mask versions, and h8s/2635 group, however, the pss bit must always be written with 0 since no subclock functions are available. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the u-mask and w-mask versions, and h8s/2635 group. subclock functions may be used with the u-mask and w-mask versions, and h8s/2635 group. 3. bits dton, lson, nesel, and substp in lpwrcr are valid in the u-mask and w-mask versions, and h8s/2635 group. in versions other than the u-mask and w-mask versions, and h8s/2635 group, however, these bits must always be written with 0 since no subclock functions are available. 4. an i 2 c bus interface can only be added to the h8s/2638, h8s/2639, and h8s/2630. therefore, iic related registers are valid only in the h8s/2638, h8s/2639, and h8s/2630. 5. this bit is reserved in the h8s/2636. 6. this bit is reserved in the h8s/2636 and h8s/2635. 7. these bits are not available in the h8s/2635 and h8s/2634. 8. these bits are reserved in the h8s/2636, h8s/2638, h8s/2639, and h8s/2635. these bits are valid in the h8s/2630 only.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1184 of 1484 rej09b0103-0600 b.2 functions dacr ? d/a control register h'fffa d/a converter register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes ( ? ) indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? d/a enabled daoe1 0 1 conversion result dae * 0 1 0 1 * daoe0 0 1 0 1 channel 0 and 1 d/a conversion disabled channel 0 d/a conversion enabled channel 1 d/a conversion disabled channel 0 and 1 d/a conversion enabled channel 0 d/a conversion disabled channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled d/a output enable 0 0 analog output da0 disabled 1 channel 0 d/a conversion enabled. analog output da0 enabled d/a output enable 1 0 analog output da1 disabled 1 channel 1 d/a conversion enabled. analog output da1 enabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1185 of 1484 rej09b0103-0600 mra?dtc mode register a h'ebc0 to h'efbf dtc * 7 sm1 undefined ? 6 sm0 undefined ? 5 dm1 undefined ? 4 dm0 undefined ? 3 md1 undefined ? 0 sz undefined ? 2 md0 undefined ? 1 dts undefined ? bit initial value read/write dtc data transfer size 0 byte-size transfer 1 word-size transfer dtc transfer mode select 0 destination side is repeat area or block area 1 source side is repeat area or block area dtc mode 0 normal mode repeat mode 0 1 1 block transfer mode 0 ? 1 destination address mode 0 dar is fixed dar is incremented after a transfer (by + 1 when sz = 0; by + 2 when sz = 1) ? 0 1 dar is decremented after a transfer (by ? 1 when sz = 0; by ? 2 when sz = 1) 1 source address mode 0 sar is fixed sar is incremented after a transfer (by + 1 when sz = 0; by + 2 when sz = 1) ? 0 1 sar is decremented after a transfer (by ? 1 when sz = 0; by ? 2 when sz = 1) 1 note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1186 of 1484 rej09b0103-0600 mrb?dtc mode register b h'ebc0 to h'efbf dtc * 7 chne undefined ? 6 disel undefined ? 5 ? undefined ? 4 ? undefined ? 3 ? undefined ? 0 ? undefined ? 2 ? undefined ? 1 ? undefined ? bit initial value read/write dtc interrupt select 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 1 after a data transfer ends, the cpu interrupt is enabled dtc chain transfer enable 0 end of dtc data transfer 1 dtc chain transfer note: * this register is not available in the h8s/2635 and h8s/2634. sar?dtc source address register h'ebc0 to h'efbf dtc * 23 unde- fined ? bit initial value read/write 22 unde- fined ? 21 unde- fined ? 20 unde- fined ? 19 unde- fined ? 4 unde- fined ? 3 unde- fined ? 2 unde- fined ? 1 unde- fined ? 0 unde- fined ? - - - - - - - - - - - - specify dtc transfer data source address note: * this register is not available in the h8s/2635 and h8s/2634. dar?dtc destination address register h'ebc0 to h'efbf dtc * 23 unde- fined ? bit initial value read/write 22 unde- fined ? 21 unde- fined ? 20 unde- fined ? 19 unde- fined ? 4 unde- fined ? 3 unde- fined ? 2 unde- fined ? 1 unde- fined ? 0 unde- fined ? - - - - - - - - - - - - specify dtc transfer data destination address note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1187 of 1484 rej09b0103-0600 cra?dtc transfer count register a h'ebc0 to h'efbf dtc * 15 unde- fined ? bit initial value read/write 14 unde- fined ? 13 unde- fined ? 12 unde- fined ? 11 unde- fined ? 10 unde- fined ? 9 unde- fined ? 8 unde- fined ? 7 unde- fined ? 6 unde- fined ? 5 unde- fined ? 4 unde- fined ? 3 unde- fined ? 2 unde- fined ? 1 unde- fined ? 0 unde- fined ? crah cral specify the number of dtc data transfers note: * this register is not available in the h8s/2635 and h8s/2634. crb?dtc transfer count register b h'ebc0 to h'efbf dtc * 15 unde- fined ? bit initial value read/write 14 unde- fined ? 13 unde- fined ? 12 unde- fined ? 11 unde- fined ? 10 unde- fined ? 9 unde- fined ? 8 unde- fined ? 7 unde- fined ? 6 unde- fined ? 5 unde- fined ? 4 unde- fined ? 3 unde- fined ? 2 unde- fined ? 1 unde- fined ? 0 unde- fined ? specify the number of dtc block data transfers note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1188 of 1484 rej09b0103-0600 mcr0?master control register mcr1?master control register h'f800 h'fa00 hcan0 hcan1 * hcan sleep mode 0 hcan sleep mode released 1 transition to hcan sleep mode enabled message transmission method 0 transmission order determined by message identifier priority 1 0 1 transmission order determined by mailbox (buffer) number priority (txpr1 > txpr15) halt request hcan normal operating mode hcan halt mode transition request hcan sleep mode release 0 hcan sleep mode release by can bus operation disabled 1 hcan sleep mode release by can bus operation enabled 7 mcr7 0 r/w 6 ? 0 r 5 mcr5 0 r/w 4 ? 0 r 3 ? 0 r 0 mcr0 1 r/w 2 mcr2 0 r/w 1 mcr1 0 r/w bit initial value read/write reset request 0 normal operating mode (mcr0 = 0 and gsr3 = 0) [setting condition] ? when 0 is written after an hcan reset 1 hcan reset mode transition request note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1189 of 1484 rej09b0103-0600 gsr0?general status register gsr1?general status register h'f801 h'fa01 hcan0 hcan1 * 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 gsr3 1 r 0 gsr0 0 r 2 gsr2 1 r 1 gsr1 0 r bit initial value read/write transmit/receive warning flag 0 [reset condition] when tec < 96 and rec < 96 or tec 256 1 when tec 96 or rec 96 bus off flag 0 [reset condition] recovery from bus off state 1 when tec 256 (bus off state) reset status bit 0 normal operating state [setting condition] after an hcan internal reset 1 configuration mode [reset condition] mcr0 reset mode and sleep mode message transmission status flag 0 message transmission period 1 [reset condition] idle state note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1190 of 1484 rej09b0103-0600 bcr0?bit configuration register bcr1?bit configuration register h'f802 h'fa02 hcan0 hcan1 * 15 bcr7 0 r/w 14 bcr6 0 r/w 13 bcr5 0 r/w 12 bcr4 0 r/w 11 bcr3 0 r/w 8 bcr0 0 r/w 10 bcr2 0 r/w 9 bcr1 0 r/w bit initial value read/write resynchronization jump width 0 bit synchronization width = 1 time quantum bit synchronization width = 2 time quanta 0 1 1 bit synchronization width = 3 time quanta 0 bit synchronization width = 4 time quanta 1 baud rate prescaler 02 system clock 4 system clock 0 0 0 06 system clock 0 . . . . . . . . . . . . . . 128 system clock 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 1 7 bcr15 0 r/w 6 bcr14 0 r/w 5 bcr13 0 r/w 4 bcr12 0 r/w 3 bcr11 0 r/w 0 bcr8 0 r/w 2 bcr10 0 r/w 1 bcr9 0 r/w bit initial value read/write time segment 2 0 setting prohibited tseg2 = 2 time quanta 0 1 tseg2 = 3 time quanta 0 tseg2 = 4 time quanta 1 0 1 1 tseg2 = 5 time quanta tseg2 = 6 time quanta 0 1 tseg2 = 7 time quanta 0 tseg2 = 8 time quanta 1 0 1 time segment 1 0 setting prohibited setting prohibited 0 0 0 0 setting prohibited tseg1 = 4 time quanta 0 . . . . . . . . . . tseg1 = 5 time quanta tseg1 = 16 time quanta 1 1 0 0 1 1 0 1 0 0 0 01 1 0 1 0 1 bit sample point 0 bit sampling at one point (end of time segment 1 (tseg1)) 1 bit sampling at three points (end of time segment 1 (tseg1) and preceding and following time quanta) note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1191 of 1484 rej09b0103-0600 mbcr0?mailbox configuration register mbcr1?mailbox configuration register h'f804 h'fa04 hcan0 hcan1 * 15 mbcr7 0 r/w 14 mbcr6 0 r/w 13 mbcr5 0 r/w 12 mbcr4 0 r/w 11 mbcr3 0 r/w 8 ? 1 r 10 mbcr2 0 r/w 9 mbcr1 0 r/w 7 mbcr15 0 r/w 6 mbcr14 0 r/w 5 mbcr13 0 r/w 4 mbcr12 0 r/w 3 mbcr11 0 r/w 0 mbcr8 0 r/w 2 mbcr10 0 r/w 1 mbcr9 0 r/w bit initial value read/write bit initial value read/write mailbox setting register 0 corresponding mailbox is set for transmission 1 corresponding mailbox is set for reception note: * this register is not available in the h8s/2635 and h8s/2634. txpr0?transmit wait register txpr1?transmit wait register h'f806 h'fa06 hcan0 hcan1 * 15 txpr7 0 r/w 14 txpr6 0 r/w 13 txpr5 0 r/w 12 txpr4 0 r/w 11 txpr3 0 r/w 8 ? 0 r 10 txpr2 0 r/w 9 txpr1 0 r/w 7 txpr15 0 r/w 6 txpr14 0 r/w 5 txpr13 0 r/w 4 txpr12 0 r/w 3 txpr11 0 r/w 0 txpr8 0 r/w 2 txpr10 0 r/w 1 txpr9 0 r/w bit initial value read/write bit initial value read/write transmit wait register 0 transmit message idle state in corresponding mailbox [clearing condition] message transmission completion and cancellation completion 1 transmit message transmit wait in corresponding mailbox (can bus arbitration) note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1192 of 1484 rej09b0103-0600 txcr0?transmit wait cancel register txcr1?transmit wait cancel register h'f808 h'fa08 hcan0 hcan1 * 15 txcr7 0 r/w 14 txcr6 0 r/w 13 txcr5 0 r/w 12 txcr4 0 r/w 11 txcr3 0 r/w 8 ? 0 r 10 txcr2 0 r/w 9 txcr1 0 r/w 7 txcr15 0 r/w 6 txcr14 0 r/w 5 txcr13 0 r/w 4 txcr12 0 r/w 3 txcr11 0 r/w 0 txcr8 0 r/w 2 txcr10 0 r/w 1 txcr9 0 r/w bit initial value read/write bit initial value read/write transmit wait cancel register 0 transmit message cancellation idle state in corresponding mailbox [clearing condition] completion of txpr clearing (when transmit message is canceled normally) 1 txpr cleared for corresponding mailbox (transmit message cancellation) note: * this register is not available in the h8s/2635 and h8s/2634. txack0?transmit acknowledge register txack1?transmit acknowledge register h'f80a h'fa04 hcan0 hcan1 * 15 txack7 0 r/w 14 txack6 0 r/w 13 txack5 0 r/w 12 txack4 0 r/w 11 txack3 0 r/w 8 ? 0 r 10 txack2 0 r/w 9 txack1 0 r/w 7 txack15 0 r/w 6 txack14 0 r/w 5 txack13 0 r/w 4 txack12 0 r/w 3 txack11 0 r/w 0 txack8 0 r/w 2 txack10 0 r/w 1 txack9 0 r/w bit initial value read/write bit initial value read/write transmit acknowledge register 0 [clearing condition] writing 1 1 completion of message transmission for corresponding mailbox note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1193 of 1484 rej09b0103-0600 aback0?abort acknowledge register aback1?abort acknowledge register h'f80c h'fa0c hcan0 hcan1 * 15 aback7 0 r/w 14 aback6 0 r/w 13 aback5 0 r/w 12 aback4 0 r/w 11 aback3 0 r/w 8 ? 0 r 10 aback2 0 r/w 9 aback1 0 r/w 7 aback15 0 r/w 6 aback14 0 r/w 5 aback13 0 r/w 4 aback12 0 r/w 3 aback11 0 r/w 0 aback8 0 r/w 2 aback10 0 r/w 1 aback9 0 r/w bit initial value read/write bit initial value read/write abort acknowledge register 0 [clearing condition] writing 1 1 completion of transmit message cancellation for corresponding mailbox note: * this register is not available in the h8s/2635 and h8s/2634. rxpr0?receive complete register rxpr1?receive complete register h'f80e h'fa0e hcan0 hcan1 * 15 rxpr7 0 r/w 14 rxpr6 0 r/w 13 rxpr5 0 r/w 12 rxpr4 0 r/w 11 rxpr3 0 r/w 8 rxpr0 0 r/w 10 rxpr2 0 r/w 9 rxpr1 0 r/w 7 rxpr15 0 r/w 6 rxpr14 0 r/w 5 rxpr13 0 r/w 4 rxpr12 0 r/w 3 rxpr11 0 r/w 0 rxpr8 0 r/w 2 rxpr10 0 r/w 1 rxpr9 0 r/w bit initial value read/write bit initial value read/write receive complete register 0 [clearing condition] writing 1 1 completion of message (data frame or remote frame) reception in corresponding mailbox note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1194 of 1484 rej09b0103-0600 rfpr0?remote request register rfpr1?remote request register h'f810 h'fa10 hcan0 hcan1 * 15 rfpr7 0 r/w 14 rfpr6 0 r/w 13 rfpr5 0 r/w 12 rfpr4 0 r/w 11 rfpr3 0 r/w 8 rfpr0 0 r/w 10 rfpr2 0 r/w 9 rfpr1 0 r/w 7 rfpr15 0 r/w 6 rfpr14 0 r/w 5 rfpr13 0 r/w 4 rfpr12 0 r/w 3 rfpr11 0 r/w 0 rfpr8 0 r/w 2 rfpr10 0 r/w 1 rfpr9 0 r/w bit initial value read/write bit initial value read/write remote request register 0 [clearing condition] writing 1 1 completion of remote frame reception in corresponding mailbox note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1195 of 1484 rej09b0103-0600 irr0?interrupt register irr1?interrupt register h'f812 h'fa12 hcan0 hcan1 * note: * this register is not available in the h8s/2635 and h8s/2634. 15 irr7 0 r/w 14 irr6 0 r/w 13 irr5 0 r/w 12 irr4 0 r/w 11 irr3 0 r/w 8 irr0 1 r/w 10 irr2 0 r 9 irr1 0 r bit initial value read/write reset interrupt flag 0 [clearing condition] writing 1 1 hardware reset (hcan module stop * , software standby) [setting condition] when reset processing is completed after a hardware reset (hcan module stop * , software standby) receive message interrupt flag 0 [clearing condition] clearing of all bits in rxpr (receive complete register) of mailbox for which receive interrupt requests are enabled by mbimr 1 data frame or remote frame received and stored in mailbox [setting condition] when data frame or remote frame reception is completed, when corresponding mbimr = 0 remote frame request interrupt flag 0 [clearing condition] clearing of all bits in rfpr (remote request register) of mailbox for which receive interrupt requests are enabled by mbimr 1 remote frame received and stored in mailbox [setting condition] when remote frame reception is completed, when corresponding mbimr = 0 0 [clearing condition] writing 1 1 error warning state caused by transmit error [setting condition] when tec 96 transmit overload warning interrupt flag 0 [clearing condition] writing 1 1 error warning state caused by receive error [setting condition] when rec 96 receive overload warning interrupt flag 0 [clearing condition] writing 1 1 error passive state caused by transmit/receive error [setting condition] when tec 128 or rec 128 error passive interrupt flag 0 [clearing condition] writing 1 1 bus off state caused by transmit error [setting condition] when tec 256 bus off interrupt flag 0 [clearing condition] writing 1 1 overload frame transmission [setting condition] overload frame is transmitted overload frame interrupt flag note: * after reset or hardware standby release, the module stop bit is initialized to 1, and so the hcan enters the module stop state.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1196 of 1484 rej09b0103-0600 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 irr12 0 r/w 3 ? 0 ? 0 irr8 0 r/w 2 ? 0 ? 1 irr9 0 r bit initial value read/write mailbox empty interrupt flag 0 [clearing condition] writing 1 1 0 1 transmit message has been transmitted or aborted, and new message can be stored [setting condition] when txpr (transmit wait register) is cleared by completion of transmission or completion of transmission abort unread interrupt flag [clearing condition] clearing of all bits in umsr (unread message status register) unread message overwrite [setting condition] when umsr (unread message status register) is set 0 1 can bus idle state [clearing condition] writing 1 can bus operation in hcan sleep mode [setting condition] bus operation (dominant bit detection) in hcan sleep mode bus operation interrupt flag
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1197 of 1484 rej09b0103-0600 mbimr0?mailbox interrupt mask register mbimr1?mailbox interrupt mask register h'f814 h'fa14 hcan0 hcan1 * 15 mbimr7 1 r/w 14 mbimr6 1 r/w 13 mbimr5 1 r/w 12 mbimr4 1 r/w 11 mbimr3 1 r/w 8 mbimr0 1 r/w 10 mbimr2 1 r/w 9 mbimr1 1 r/w 7 mbimr15 1 r/w 6 mbimr14 1 r/w 5 mbimr13 1 r/w 4 mbimr12 1 r/w 3 mbimr11 1 r/w 0 mbimr8 1 r/w 2 mbimr10 1 r/w 1 mbimr9 1 r/w bit initial value read/write bit initial value read/write mailbox interrupt mask 0 [transmitting] interrupt request to cpu due to txpr clearing [receiving] interrupt request to cpu due to rxpr setting 1 interrupt requests to cpu disabled note: * this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1198 of 1484 rej09b0103-0600 imr0?interrupt mask register imr1?interrupt mask register h'f816 h'fa16 hcan0 hcan1 * note: * this register is not available in the h8s/2635 and h8s/2634. 15 imr7 1 r/w 14 imr6 1 r/w 13 imr5 1 r/w 12 imr4 1 r/w 11 imr3 1 r/w 8 ? 0 r 10 imr2 1 r/w 9 imr1 1 r/w bit initial value read/write overload frame/bus off recovery interrupt mask bus off interrupt mask 0 bus off interrupt request to cpu by irr6 enabled 1 0 1 bus off interrupt request to cpu by irr6 disabled 0 overload frame/bus off recovery interrupt request to cpu by irr7 enabled 1 overload frame/bus off recovery interrupt request to cpu by irr7 disabled error passive interrupt mask 0 error passive interrupt request to cpu by irr5 enabled 1 error passive interrupt request to cpu by irr5 disabled receive overload warning interrupt mask 0 rec error warning interrupt request (ovr0) to cpu by irr4 enabled 1 rec error warning interrupt request (ovr0) to cpu by irr4 disabled transmit overload warning interrupt mask 0 tec error warning interrupt request (ovr0) to cpu by irr3 enabled 1 tec error warning interrupt request (ovr0) to cpu by irr3 disabled remote frame request interrupt mask 0 remote frame reception interrupt request (ovr0) to cpu by irr2 enabled 1 remote frame reception interrupt request (ovr0) to cpu by irr2 disabled receive message interrupt mask message reception interrupt request (rm1) to cpu by irr1 enabled message reception interrupt request (rm1) to cpu by irr1 disabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1199 of 1484 rej09b0103-0600 7 ? 1 r 6 ? 1 r 5 ? 1 r 4 imr12 1 r/w 3 ? 1 r 0 imr8 1 r/w 2 ? 1 r 1 imr9 1 r/w bit initial value read/write mailbox empty interrupt mask 0 mailbox empty interrupt request (sle0) to cpu by irr8 enabled 1 mailbox empty interrupt request (sle0) to cpu by irr8 disabled unread interrupt mask 0 unread message overwrite interrupt request (ovr0) to cpu by irr9 enabled 1 unread message overwrite interrupt request (ovr0) to cpu by irr9 disabled bus operation interrupt mask 0 bus operation interrupt request (ovr0) to cpu by irr12 enabled 1 bus operation interrupt request (ovr0) to cpu by irr12 disabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1200 of 1484 rej09b0103-0600 rec0?receive error counter rec1?receive error counter h'f818 h'fa18 hcan0 hcan1 * 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write note: * this register is not available in the h8s/2635 and h8s/2634. tec0?transmit error counter tec1?transmit error counter h'f819 h'fa19 hcan0 hcan1 * 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write note: * this register is not available in the h8s/2635 and h8s/2634. umsr0?unread message status register umsr1?unread message status register h'f81a h'fa1a hcan0 hcan1 * 1 15 umsr7 0 r/(w) * 2 14 umsr6 0 r/(w) * 2 13 umsr5 0 r/(w) * 2 12 umsr4 0 r/(w) * 2 11 umsr3 0 r/(w) * 2 8 umsr0 0 r/(w) * 2 10 umsr2 0 r/(w) * 2 9 umsr1 0 r/(w) * 2 7 umsr15 0 r/(w) * 2 6 umsr14 0 r/(w) * 2 5 umsr13 0 r/(w) * 2 4 umsr12 0 r/(w) * 2 3 umsr11 0 r/(w) * 2 0 umsr8 0 r/(w) * 2 2 umsr10 0 r/(w) * 2 1 umsr9 0 r/(w) * 2 bit initial value read/write bit initial value read/write unread message status flags 0 [clearing condition] writing 1 1 unread receive message is overwritten by a new message [setting condition] when a new message is received before rxpr is cleared notes: 1. this register is not available in the h8s/2635 and h8s/2634. 2. only 1 can be written, to clear the flag to 0.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1201 of 1484 rej09b0103-0600 lafml0?local acceptance filter masks l h'f81c hcan0 lafmh0?local acceptance filter masks h h'f81e h can0 lafml1?local acceptance filter masks l h'fa1c hcan1 * lafmh1?local acceptance filter masks h h'fa1e hcan1 * 15 lafml7 0 r/w 14 lafml6 0 r/w 13 lafml5 0 r/w 12 lafml4 0 r/w 11 lafml3 0 r/w 8 lafml0 0 r/w 10 lafml2 0 r/w 9 lafml1 0 r/w 7 lafml15 0 r/w 6 lafml14 0 r/w 5 lafml13 0 r/w 4 lafml12 0 r/w 3 lafml11 0 r/w 0 lafml8 0 r/w 2 lafml10 0 r/w 1 lafml9 0 r/w bit initial value read/write bit initial value read/write 15 lafmh7 0 r/w 14 lafmh6 0 r/w 13 lafmh5 0 r/w 12 ? 0 r 11 ? 0 r 8 lafmh0 0 r/w 10 ? 0 r 9 lafmh1 0 r/w 7 lafmh15 0 r/w 6 lafmh14 0 r/w 5 lafmh13 0 r/w 4 lafmh12 0 r/w 3 lafmh11 0 r/w 0 lafmh8 0 r/w 2 lafmh10 0 r/w 1 lafmh9 0 r/w bit initial value read/write lafmh bit initial value read/write lafmh bits 7 to 0 and 15 to 13 ? 11-bit identifier filter 0 stored in mc0 and md0 (receive-only mailbox) depending on bit match between mc0 message identifier and receive message identifier (care) 1 stored in mc0 and md0 (receive-only mailbox) regardless of bit match between mc0 message identifier and receive message identifier (don't care) lafmh bits 9 and 8, lafml bits 15 to 0 ? 18-bit identifier filter 0 stored in mc0 (receive-only mailbox) depending on bit match between mc0 message identifier and receive message identifier (care) 1 stored in mc0 (receive-only mailbox) regardless of bit match between mc0 message identifier and receive message identifier (don't care) note: * these registers are not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1202 of 1484 rej09b0103-0600 mc0[1]?message control 0[1] h'f820 hcan0 mc0[2]?message control 0[2] h'f821 hcan0 mc0[3]?message control 0[3] h'f822 hcan0 mc0[4]?message control 0[4] h'f823 hcan0 mc0[5]?message control 0[5] h'f824 hcan0 mc0[6]?message control 0[6] h'f825 hcan0 mc0[7]?message control 0[7] h'f826 hcan0 mc0[8]?message control 0[8] h'f827 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc0[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1203 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc0[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc0[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1204 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc0[8] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w bit initial value read/write mc0[7] extended identifier set the identifier (extended identifier) of data frames and remote frames
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1205 of 1484 rej09b0103-0600 mc1[1]?message control 1[1] h'f828 hcan0 mc1[2]?message control 1[2] h'f829 hcan0 mc1[3]?message control 1[3] h'f82a hcan0 mc1[4]?message control 1[4] h'f82b hcan0 mc1[5]?message control 1[5] h'f82c hcan0 mc1[6]?message control 1[6] h'f82d hcan0 mc1[7]?message control 1[7] h'f82e hcan0 mc1[8]?message control 1[8] h'f82f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc1[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1206 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc1[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc1[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1207 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc1[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc1[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1208 of 1484 rej09b0103-0600 mc2[1]?message control 2[1] h'f830 hcan0 mc2[2]?message control 2[2] h'f831 hcan0 mc2[3]?message control 2[3] h'f832 hcan0 mc2[4]?message control 2[4] h'f833 hcan0 mc2[5]?message control 2[5] h'f834 hcan0 mc2[6]?message control 2[6] h'f835 hcan0 mc2[7]?message control 2[7] h'f836 hcan0 mc2[8]?message control 2[8] h'f837 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc2[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1209 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc2[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc2[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1210 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc2[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc2[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1211 of 1484 rej09b0103-0600 mc3[1]?message control 3[1] h'f838 hcan0 mc3[2]?message control 3[2] h'f839 hcan0 mc3[3]?message control 3[3] h'f83a hcan0 mc3[4]?message control 3[4] h'f83b hcan0 mc3[5]?message control 3[5] h'f83c hcan0 mc3[6]?message control 3[6] h'f83d hcan0 mc3[7]?message control 3[7] h'f83e hcan0 mc3[8]?message control 3[8] h'f83f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc3[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1212 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc3[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc3[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1213 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc3[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc3[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1214 of 1484 rej09b0103-0600 mc4[1]?message control 4[1] h'f840 hcan0 mc4[2]?message control 4[2] h'f841 hcan0 mc4[3]?message control 4[3] h'f842 hcan0 mc4[4]?message control 4[4] h'f843 hcan0 mc4[5]?message control 4[5] h'f844 hcan0 mc4[6]?message control 4[6] h'f845 hcan0 mc4[7]?message control 4[7] h'f846 hcan0 mc4[8]?message control 4[8] h'f847 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc4[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1215 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc4[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc4[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1216 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc4[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc4[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1217 of 1484 rej09b0103-0600 mc5[1]?message control 5[1] h'f848 hcan0 mc5[2]?message control 5[2] h'f849 hcan0 mc5[3]?message control 5[3] h'f84a hcan0 mc5[4]?message control 5[4] h'f84b hcan0 mc5[5]?message control 5[5] h'f84c hcan0 mc5[6]?message control 5[6] h'f84d hcan0 mc5[7]?message control 5[7] h'f84e hcan0 mc5[8]?message control 5[8] h'f84f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc5[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1218 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc5[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc5[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1219 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc5[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc5[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1220 of 1484 rej09b0103-0600 mc6[1]?message control 6[1] h'f850 hcan0 mc6[2]?message control 6[2] h'f851 hcan0 mc6[3]?message control 6[3] h'f852 hcan0 mc6[4]?message control 6[4] h'f853 hcan0 mc6[5]?message control 6[5] h'f854 hcan0 mc6[6]?message control 6[6] h'f855 hcan0 mc6[7]?message control 6[7] h'f856 hcan0 mc6[8]?message control 6[8] h'f857 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc6[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1221 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc6[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc6[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1222 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc6[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc6[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1223 of 1484 rej09b0103-0600 mc7[1]?message control 7[1] h'f858 hcan0 mc7[2]?message control 7[2] h'f859 hcan0 mc7[3]?message control 7[3] h'f85a hcan0 mc7[4]?message control 7[4] h'f85b hcan0 mc7[5]?message control 7[5] h'f85c hcan0 mc7[6]?message control 7[6] h'f85d hcan0 mc7[7]?message control 7[7] h'f85e hcan0 mc7[8]?message control 7[8] h'f85f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc7[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1224 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc7[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc7[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1225 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc7[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc7[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1226 of 1484 rej09b0103-0600 mc8[1]?message control 8[1] h'f860 hcan0 mc8[2]?message control 8[2] h'f861 hcan0 mc8[3]?message control 8[3] h'f862 hcan0 mc8[4]?message control 8[4] h'f863 hcan0 mc8[5]?message control 8[5] h'f864 hcan0 mc8[6]?message control 8[6] h'f865 hcan0 mc8[7]?message control 8[7] h'f866 hcan0 mc8[8]?message control 8[8] h'f867 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc8[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1227 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc8[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc8[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1228 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc8[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc8[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1229 of 1484 rej09b0103-0600 mc9[1]?message control 9[1] h'f868 hcan0 mc9[2]?message control 9[2] h'f869 hcan0 mc9[3]?message control 9[3] h'f86a hcan0 mc9[4]?message control 9[4] h'f86b hcan0 mc9[5]?message control 9[5] h'f86c hcan0 mc9[6]?message control 9[6] h'f86d hcan0 mc9[7]?message control 9[7] h'f86e hcan0 mc9[8]?message control 9[8] h'f86f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc9[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1230 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc9[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc9[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1231 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc9[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc9[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1232 of 1484 rej09b0103-0600 mc10[1]?message control 10[1] h'f870 hcan0 mc10[2]?message control 10[2] h'f871 hcan0 mc10[3]?message control 10[3] h'f872 hcan0 mc10[4]?message control 10[4] h'f873 hcan0 mc10[5]?message control 10[5] h'f874 hcan0 mc10[6]?message control 10[6] h'f875 hcan0 mc10[7]?message control 10[7] h'f876 hcan0 mc10[8]?message control 10[8] h'f877 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc10[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1233 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc10[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc10[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1234 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc10[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc10[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1235 of 1484 rej09b0103-0600 mc11[1]?message control 11[1] h'f878 hcan0 mc11[2]?message control 11[2] h'f879 hcan0 mc11[3]?message control 11[3] h'f87a hcan0 mc11[4]?message control 11[4] h'f87b hcan0 mc11[5]?message control 11[5] h'f87c hcan0 mc11[6]?message control 11[6] h'f87d hcan0 mc11[7]?message control 11[7] h'f87e hcan0 mc11[8]?message control 11[8] h'f87f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc11[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1236 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc11[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc11[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1237 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc11[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc11[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1238 of 1484 rej09b0103-0600 mc12[1]?message control 12[1] h'f880 hcan0 mc12[2]?message control 12[2] h'f881 hcan0 mc12[3]?message control 12[3] h'f882 hcan0 mc12[4]?message control 12[4] h'f883 hcan0 mc12[5]?message control 12[5] h'f884 hcan0 mc12[6]?message control 12[6] h'f885 hcan0 mc12[7]?message control 12[7] h'f886 hcan0 mc12[8]?message control 12[8] h'f887 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc12[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1239 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc12[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc12[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1240 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc12[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc12[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1241 of 1484 rej09b0103-0600 mc13[1]?message control 13[1] h'f888 hcan0 mc13[2]?message control 13[2] h'f889 hcan0 mc13[3]?message control 13[3] h'f88a hcan0 mc13[4]?message control 13[4] h'f88b hcan0 mc13[5]?message control 13[5] h'f88c hcan0 mc13[6]?message control 13[6] h'f88d hcan0 mc13[7]?message control 13[7] h'f88e hcan0 mc13[8]?message control 13[8] h'f88f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc13[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1242 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc13[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc13[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1243 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc13[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc13[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1244 of 1484 rej09b0103-0600 mc14[1]?message control 14[1] h'f890 hcan0 mc14[2]?message control 14[2] h'f891 hcan0 mc14[3]?message control 14[3] h'f892 hcan0 mc14[4]?message control 14[4] h'f893 hcan0 mc14[5]?message control 14[5] h'f894 hcan0 mc14[6]?message control 14[6] h'f895 hcan0 mc14[7]?message control 14[7] h'f896 hcan0 mc14[8]?message control 14[8] h'f897 hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc14[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1245 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc14[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc14[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1246 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc14[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc14[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1247 of 1484 rej09b0103-0600 mc15[1]?message control 15[1] h'f898 hcan0 mc15[2]?message control 15[2] h'f899 hcan0 mc15[3]?message control 15[3] h'f89a hcan0 mc15[4]?message control 15[4] h'f89b hcan0 mc15[5]?message control 15[5] h'f89c hcan0 mc15[6]?message control 15[6] h'f89d hcan0 mc15[7]?message control 15[7] h'f89e hcan0 mc15[8]?message control 15[8] h'f89f hcan0 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc15[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1248 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc15[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc15[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1249 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc15[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc15[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1250 of 1484 rej09b0103-0600 md0[1]?message data 0[1] h'f8b0 hcan0 md0[2]?message data 0[2] h'f8b1 hcan0 md0[3]?message data 0[3] h'f8b2 hcan0 md0[4]?message data 0[4] h'f8b3 hcan0 md0[5]?message data 0[5] h'f8b4 hcan0 md0[6]?message data 0[6] h'f8b5 hcan0 md0[7]?message data 0[7] h'f8b6 hcan0 md0[8]?message data 0[8] h'f8b7 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1251 of 1484 rej09b0103-0600 md1[1]?message data 1[1] h'f8b8 hcan0 md1[2]?message data 1[2] h'f8b9 hcan0 md1[3]?message data 1[3] h'f8ba hcan0 md1[4]?message data 1[4] h'f8bb hcan0 md1[5]?message data 1[5] h'f8bc hcan0 md1[6]?message data 1[6] h'f8bd hcan0 md1[7]?message data 1[7] h'f8be hcan0 md1[8]?message data 1[8] h'f8bf hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1252 of 1484 rej09b0103-0600 md2[1]?message data 2[1] h'f8c0 hcan0 md2[2]?message data 2[2] h'f8c1 hcan0 md2[3]?message data 2[3] h'f8c2 hcan0 md2[4]?message data 2[4] h'f8c3 hcan0 md2[5]?message data 2[5] h'f8c4 hcan0 md2[6]?message data 2[6] h'f8c5 hcan0 md2[7]?message data 2[7] h'f8c6 hcan0 md2[8]?message data 2[8] h'f8c7 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1253 of 1484 rej09b0103-0600 md3[1]?message data 3[1] h'f8c8 hcan0 md3[2]?message data 3[2] h'f8c9 hcan0 md3[3]?message data 3[3] h'f8ca hcan0 md3[4]?message data 3[4] h'f8cb hcan0 md3[5]?message data 3[5] h'f8cc hcan0 md3[6]?message data 3[6] h'f8cd hcan0 md3[7]?message data 3[7] h'f8ce hcan0 md3[8]?message data 3[8] h'f8cf hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1254 of 1484 rej09b0103-0600 md4[1]?message data 4[1] h'f8d0 hcan0 md4[2]?message data 4[2] h'f8d1 hcan0 md4[3]?message data 4[3] h'f8d2 hcan0 md4[4]?message data 4[4] h'f8d3 hcan0 md4[5]?message data 4[5] h'f8d4 hcan0 md4[6]?message data 4[6] h'f8d5 hcan0 md4[7]?message data 4[7] h'f8d6 hcan0 md4[8]?message data 4[8] h'f8d7 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1255 of 1484 rej09b0103-0600 md5[1]?message data 5[1] h'f8d8 hcan0 md5[2]?message data 5[2] h'f8d9 hcan0 md5[3]?message data 5[3] h'f8da hcan0 md5[4]?message data 5[4] h'f8db hcan0 md5[5]?message data 5[5] h'f8dc hcan0 md5[6]?message data 5[6] h'f8dd hcan0 md5[7]?message data 5[7] h'f8de hcan0 md5[8]?message data 5[8] h'f8df hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1256 of 1484 rej09b0103-0600 md6[1]?message data 6[1] h'f8e0 hcan0 md6[2]?message data 6[2] h'f8e1 hcan0 md6[3]?message data 6[3] h'f8e2 hcan0 md6[4]?message data 6[4] h'f8e3 hcan0 md6[5]?message data 6[5] h'f8e4 hcan0 md6[6]?message data 6[6] h'f8e5 hcan0 md6[7]?message data 6[7] h'f8e6 hcan0 md6[8]?message data 6[8] h'f8e7 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1257 of 1484 rej09b0103-0600 md7[1]?message data 7[1] h'f8e8 hcan0 md7[2]?message data 7[2] h'f8e9 hcan0 md7[3]?message data 7[3] h'f8ea hcan0 md7[4]?message data 7[4] h'f8eb hcan0 md7[5]?message data 7[5] h'f8ec hcan0 md7[6]?message data 7[6] h'f8ed hcan0 md7[7]?message data 7[7] h'f8ee hcan0 md7[8]?message data 7[8] h'f8ef hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1258 of 1484 rej09b0103-0600 md8[1]?message data 8[1] h'f8f0 hcan0 md8[2]?message data 8[2] h'f8f1 hcan0 md8[3]?message data 8[3] h'f8f2 hcan0 md8[4]?message data 8[4] h'f8f3 hcan0 md8[5]?message data 8[5] h'f8f4 hcan0 md8[6]?message data 8[6] h'f8f5 hcan0 md8[7]?message data 8[7] h'f8f6 hcan0 md8[8]?message data 8[8] h'f8f7 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1259 of 1484 rej09b0103-0600 md9[1]?message data 9[1] h'f8f8 hcan0 md9[2]?message data 9[2] h'f8f9 hcan0 md9[3]?message data 9[3] h'f8fa hcan0 md9[4]?message data 9[4] h'f8fb hcan0 md9[5]?message data 9[5] h'f8fc hcan0 md9[6]?message data 9[6] h'f8fd hcan0 md9[7]?message data 9[7] h'f8fe hcan0 md9[8]?message data 9[8] h'f8ff hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1260 of 1484 rej09b0103-0600 md10[1]?message data 10[1] h'f900 hcan0 md10[2]?message data 10[2] h'f901 hcan0 md10[3]?message data 10[3] h'f902 hcan0 md10[4]?message data 10[4] h'f903 hcan0 md10[5]?message data 10[5] h'f904 hcan0 md10[6]?message data 10[6] h'f905 hcan0 md10[7]?message data 10[7] h'f906 hcan0 md10[8]?message data 10[8] h'f907 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1261 of 1484 rej09b0103-0600 md11[1]?message data 11[1] h'f908 hcan0 md11[2]?message data 11[2] h'f909 hcan0 md11[3]?message data 11[3] h'f90a hcan0 md11[4]?message data 11[4] h'f90b hcan0 md11[5]?message data 11[5] h'f90c hcan0 md11[6]?message data 11[6] h'f90d hcan0 md11[7]?message data 11[7] h'f90e hcan0 md11[8]?message data 11[8] h'f90f hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1262 of 1484 rej09b0103-0600 md12[1]?message data 12[1] h'f910 hcan0 md12[2]?message data 12[2] h'f911 hcan0 md12[3]?message data 12[3] h'f912 hcan0 md12[4]?message data 12[4] h'f913 hcan0 md12[5]?message data 12[5] h'f914 hcan0 md12[6]?message data 12[6] h'f915 hcan0 md12[7]?message data 12[7] h'f916 hcan0 md12[8]?message data 12[8] h'f917 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1263 of 1484 rej09b0103-0600 md13[1]?message data 13[1] h'f918 hcan0 md13[2]?message data 13[2] h'f919 hcan0 md13[3]?message data 13[3] h'f91a hcan0 md13[4]?message data 13[4] h'f91b hcan0 md13[5]?message data 13[5] h'f91c hcan0 md13[6]?message data 13[6] h'f91d hcan0 md13[7]?message data 13[7] h'f91e hcan0 md13[8]?message data 13[8] h'f91f hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1264 of 1484 rej09b0103-0600 md14[1]?message data 14[1] h'f920 hcan0 md14[2]?message data 14[2] h'f921 hcan0 md14[3]?message data 14[3] h'f922 hcan0 md14[4]?message data 14[4] h'f923 hcan0 md14[5]?message data 14[5] h'f924 hcan0 md14[6]?message data 14[6] h'f925 hcan0 md14[7]?message data 14[7] h'f926 hcan0 md14[8]?message data 14[8] h'f927 hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1265 of 1484 rej09b0103-0600 md15[1]?message data 15[1] h'f928 hcan0 md15[2]?message data 15[2] h'f929 hcan0 md15[3]?message data 15[3] h'f92a hcan0 md15[4]?message data 15[4] h'f92b hcan0 md15[5]?message data 15[5] h'f92c hcan0 md15[6]?message data 15[6] h'f92d hcan0 md15[7]?message data 15[7] h'f92e hcan0 md15[8]?message data 15[8] h'f92f hcan0 bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1266 of 1484 rej09b0103-0600 mc0[1]?message control 0[1] h'fa20 hcan1 mc0[2]?message control 0[2] h'fa21 hcan1 mc0[3]?message control 0[3] h'fa22 hcan1 mc0[4]?message control 0[4] h'fa23 hcan1 mc0[5]?message control 0[5] h'fa24 hcan1 mc0[6]?message control 0[6] h'fa25 hcan1 mc0[7]?message control 0[7] h'fa26 hcan1 mc0[8]?message control 0[8] h'fa27 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc0[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1267 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc0[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc0[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc0[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1268 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc0[8] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w bit initial value read/write mc0[7] extended identifier set the identifier (extended identifier) of data frames and remote frames
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1269 of 1484 rej09b0103-0600 mc1[1]?message control 1[1] h'fa28 hcan1 mc1[2]?message control 1[2] h'fa29 hcan1 mc1[3]?message control 1[3] h'fa2a hcan1 mc1[4]?message control 1[4] h'fa2b hcan1 mc1[5]?message control 1[5] h'fa2c hcan1 mc1[6]?message control 1[6] h'fa2d hcan1 mc1[7]?message control 1[7] h'fa2e hcan1 mc1[8]?message control 1[8] h'fa2f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc1[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1270 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc1[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc1[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc1[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1271 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc1[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc1[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1272 of 1484 rej09b0103-0600 mc2[1]?message control 2[1] h'fa30 hcan1 mc2[2]?message control 2[2] h'fa31 hcan1 mc2[3]?message control 2[3] h'fa32 hcan1 mc2[4]?message control 2[4] h'fa33 hcan1 mc2[5]?message control 2[5] h'fa34 hcan1 mc2[6]?message control 2[6] h'fa35 hcan1 mc2[7]?message control 2[7] h'fa36 hcan1 mc2[8]?message control 2[8] h'fa37 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc2[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1273 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc2[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc2[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc2[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1274 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc2[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc2[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1275 of 1484 rej09b0103-0600 mc3[1]?message control 3[1] h'fa38 hcan1 mc3[2]?message control 3[2] h'fa39 hcan1 mc3[3]?message control 3[3] h'fa3a hcan1 mc3[4]?message control 3[4] h'fa3b hcan1 mc3[5]?message control 3[5] h'fa3c hcan1 mc3[6]?message control 3[6] h'fa3d hcan1 mc3[7]?message control 3[7] h'fa3e hcan1 mc3[8]?message control 3[8] h'fa3f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc3[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1276 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc3[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc3[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc3[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1277 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc3[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc3[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1278 of 1484 rej09b0103-0600 mc4[1]?message control 4[1] h'fa40 hcan1 mc4[2]?message control 4[2] h'fa41 hcan1 mc4[3]?message control 4[3] h'fa42 hcan1 mc4[4]?message control 4[4] h'fa43 hcan1 mc4[5]?message control 4[5] h'fa44 hcan1 mc4[6]?message control 4[6] h'fa45 hcan1 mc4[7]?message control 4[7] h'fa46 hcan1 mc4[8]?message control 4[8] h'fa47 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc4[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1279 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc4[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc4[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc4[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1280 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc4[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc4[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1281 of 1484 rej09b0103-0600 mc5[1]?message control 5[1] h'fa48 hcan1 mc5[2]?message control 5[2] h'fa49 hcan1 mc5[3]?message control 5[3] h'fa4a hcan1 mc5[4]?message control 5[4] h'fa4b hcan1 mc5[5]?message control 5[5] h'fa4c hcan1 mc5[6]?message control 5[6] h'fa4d hcan1 mc5[7]?message control 5[7] h'fa4e hcan1 mc5[8]?message control 5[8] h'fa4f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc5[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1282 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc5[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc5[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc5[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1283 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc5[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc5[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1284 of 1484 rej09b0103-0600 mc6[1]?message control 6[1] h'fa50 hcan1 mc6[2]?message control 6[2] h'fa51 hcan1 mc6[3]?message control 6[3] h'fa52 hcan1 mc6[4]?message control 6[4] h'fa53 hcan1 mc6[5]?message control 6[5] h'fa54 hcan1 mc6[6]?message control 6[6] h'fa55 hcan1 mc6[7]?message control 6[7] h'fa56 hcan1 mc6[8]?message control 6[8] h'fa57 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc6[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1285 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc6[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc6[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc6[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1286 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc6[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc6[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1287 of 1484 rej09b0103-0600 mc7[1]?message control 7[1] h'fa58 hcan1 mc7[2]?message control 7[2] h'fa59 hcan1 mc7[3]?message control 7[3] h'fa5a hcan1 mc7[4]?message control 7[4] h'fa5b hcan1 mc7[5]?message control 7[5] h'fa5c hcan1 mc7[6]?message control 7[6] h'fa5d hcan1 mc7[7]?message control 7[7] h'fa5e hcan1 mc7[8]?message control 7[8] h'fa5f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc7[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1288 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc7[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc7[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc7[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1289 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc7[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc7[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1290 of 1484 rej09b0103-0600 mc8[1]?message control 8[1] h'fa60 hcan1 mc8[2]?message control 8[2] h'fa61 hcan1 mc8[3]?message control 8[3] h'fa62 hcan1 mc8[4]?message control 8[4] h'fa63 hcan1 mc8[5]?message control 8[5] h'fa64 hcan1 mc8[6]?message control 8[6] h'fa65 hcan1 mc8[7]?message control 8[7] h'fa66 hcan1 mc8[8]?message control 8[8] h'fa67 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc8[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1291 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc8[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc8[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc8[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1292 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc8[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc8[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1293 of 1484 rej09b0103-0600 mc9[1]?message control 9[1] h'fa68 hcan1 mc9[2]?message control 9[2] h'fa69 hcan1 mc9[3]?message control 9[3] h'fa6a hcan1 mc9[4]?message control 9[4] h'fa6b hcan1 mc9[5]?message control 9[5] h'fa6c hcan1 mc9[6]?message control 9[6] h'fa6d hcan1 mc9[7]?message control 9[7] h'fa6e hcan1 mc9[8]?message control 9[8] h'fa6f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc9[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1294 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc9[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc9[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc9[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1295 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc9[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc9[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1296 of 1484 rej09b0103-0600 mc10[1]?message control 10[1] h'fa70 hcan1 mc10[2]?message control 10[2] h'fa71 hcan1 mc10[3]?message control 10[3] h'fa72 hcan1 mc10[4]?message control 10[4] h'fa73 hcan1 mc10[5]?message control 10[5] h'fa74 hcan1 mc10[6]?message control 10[6] h'fa75 hcan1 mc10[7]?message control 10[7] h'fa76 hcan1 mc10[8]?message control 10[8] h'fa77 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc10[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1297 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc10[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc10[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc10[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1298 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc10[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc10[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1299 of 1484 rej09b0103-0600 mc11[1]?message control 11[1] h'fa78 hcan1 mc11[2]?message control 11[2] h'fa79 hcan1 mc11[3]?message control 11[3] h'fa7a hcan1 mc11[4]?message control 11[4] h'fa7b hcan1 mc11[5]?message control 11[5] h'fa7c hcan1 mc11[6]?message control 11[6] h'fa7d hcan1 mc11[7]?message control 11[7] h'fa7e hcan1 mc11[8]?message control 11[8] h'fa7f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc11[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1300 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc11[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc11[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc11[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1301 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc11[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc11[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1302 of 1484 rej09b0103-0600 mc12[1]?message control 12[1] h'fa80 hcan1 mc12[2]?message control 12[2] h'fa81 hcan1 mc12[3]?message control 12[3] h'fa82 hcan1 mc12[4]?message control 12[4] h'fa83 hcan1 mc12[5]?message control 12[5] h'fa84 hcan1 mc12[6]?message control 12[6] h'fa85 hcan1 mc12[7]?message control 12[7] h'fa86 hcan1 mc12[8]?message control 12[8] h'fa87 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc12[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1303 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc12[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc12[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc12[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1304 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc12[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc12[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1305 of 1484 rej09b0103-0600 mc13[1]?message control 13[1] h'fa88 hcan1 mc13[2]?message control 13[2] h'fa89 hcan1 mc13[3]?message control 13[3] h'fa8a hcan1 mc13[4]?message control 13[4] h'fa8b hcan1 mc13[5]?message control 13[5] h'fa8c hcan1 mc13[6]?message control 13[6] h'fa8d hcan1 mc13[7]?message control 13[7] h'fa8e hcan1 mc13[8]?message control 13[8] h'fa8f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc13[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1306 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc13[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc13[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc13[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1307 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc13[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc13[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1308 of 1484 rej09b0103-0600 mc14[1]?message control 14[1] h'fa90 hcan1 mc14[2]?message control 14[2] h'fa91 hcan1 mc14[3]?message control 14[3] h'fa92 hcan1 mc14[4]?message control 14[4] h'fa93 hcan1 mc14[5]?message control 14[5] h'fa94 hcan1 mc14[6]?message control 14[6] h'fa95 hcan1 mc14[7]?message control 14[7] h'fa96 hcan1 mc14[8]?message control 14[8] h'fa97 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc14[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1309 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc14[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc14[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc14[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1310 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc14[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc14[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1311 of 1484 rej09b0103-0600 mc15[1]?message control 15[1] h'fa98 hcan1 mc15[2]?message control 15[2] h'fa99 hcan1 mc15[3]?message control 15[3] h'fa9a hcan1 mc15[4]?message control 15[4] h'fa9b hcan1 mc15[5]?message control 15[5] h'fa9c hcan1 mc15[6]?message control 15[6] h'fa9d hcan1 mc15[7]?message control 15[7] h'fa9e hcan1 mc15[8]?message control 15[8] h'fa9f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 dlc3 undefined r/w 0 dlc0 undefined r/w 2 dlc2 undefined r/w 1 dlc1 undefined r/w bit initial value read/write mc15[1] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[2] 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[3] data length code 0 data length = 0 bytes data length = 1 byte data length = 2 bytes data length = 3 bytes data length = 4 bytes data length = 5 bytes data length = 6 bytes data length = 7 bytes 1 data length = 8 bytes 0 1 0/1 0 1 0 1 0/1 0 1 0 1 0 1 0 1 0/1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1312 of 1484 rej09b0103-0600 7 std_id2 undefined r/w 6 std_id1 undefined r/w 5 std_id0 undefined r/w 4 rtr undefined r/w 3 ide undefined r/w 0 exd_id16 undefined r/w 2 ? undefined r/w 1 exd_id17 undefined r/w bit initial value read/write mc15[5] 7 std_id10 undefined r/w 6 std_id9 undefined r/w 5 std_id8 undefined r/w 4 std_id7 undefined r/w 3 std_id6 undefined r/w 0 std_id3 undefined r/w 2 std_id5 undefined r/w 1 std_id4 undefined r/w bit initial value read/write mc15[6] standard identifier set the identifier (standard identifier) of data frames and remote frames extended identifier set the identifier (extended identifier) of data frames and remote frames remote transmission request 0 data frame 1 remote frame identifier extension 0 standard format 1 extended format standard identifier set the identifier (standard identifier) of data frames and remote frames 7 ? undefined r/w 6 ? undefined r/w 5 ? undefined r/w 4 ? undefined r/w 3 ? undefined r/w 0 ? undefined r/w 2 ? undefined r/w 1 ? undefined r/w bit initial value read/write mc15[4]
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1313 of 1484 rej09b0103-0600 7 exd_id15 undefined r/w 6 exd_id14 undefined r/w 5 exd_id13 undefined r/w 4 exd_id12 undefined r/w 3 exd_id11 undefined r/w 0 exd_id8 undefined r/w 2 exd_id10 undefined r/w 1 exd_id9 undefined r/w bit initial value read/write mc15[8] extended identifier set the identifier (extended identifier) of data frames and remote frames bit initial value read/write mc15[7] extended identifier set the identifier (extended identifier) of data frames and remote frames 7 exd_id7 undefined r/w 6 exd_id6 undefined r/w 5 exd_id5 undefined r/w 4 exd_id4 undefined r/w 3 exd_id3 undefined r/w 0 exd_id0 undefined r/w 2 exd_id2 undefined r/w 1 exd_id1 undefined r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1314 of 1484 rej09b0103-0600 md0[1]?message data 0[1] h'fab0 hcan1 md0[2]?message data 0[2] h'fab1 hcan1 md0[3]?message data 0[3] h'fab2 hcan1 md0[4]?message data 0[4] h'fab3 hcan1 md0[5]?message data 0[5] h'fab4 hcan1 md0[6]?message data 0[6] h'fab5 hcan1 md0[7]?message data 0[7] h'fab6 hcan1 md0[8]?message data 0[8] h'fab7 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1315 of 1484 rej09b0103-0600 md1[1]?message data 1[1] h'fab8 hcan1 md1[2]?message data 1[2] h'fab9 hcan1 md1[3]?message data 1[3] h'faba hcan1 md1[4]?message data 1[4] h'fabb hcan1 md1[5]?message data 1[5] h'fabc hcan1 md1[6]?message data 1[6] h'fabd hcan1 md1[7]?message data 1[7] h'fabe hcan1 md1[8]?message data 1[8] h'fabf hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1316 of 1484 rej09b0103-0600 md2[1]?message data 2[1] h'fac0 hcan1 md2[2]?message data 2[2] h'fac1 hcan1 md2[3]?message data 2[3] h'fac2 hcan1 md2[4]?message data 2[4] h'fac3 hcan1 md2[5]?message data 2[5] h'fac4 hcan1 md2[6]?message data 2[6] h'fac5 hcan1 md2[7]?message data 2[7] h'fac6 hcan1 md2[8]?message data 2[8] h'fac7 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1317 of 1484 rej09b0103-0600 md3[1]?message data 3[1] h'fac8 hcan1 md3[2]?message data 3[2] h'fac9 hcan1 md3[3]?message data 3[3] h'faca hcan1 md3[4]?message data 3[4] h'facb hcan1 md3[5]?message data 3[5] h'facc hcan1 md3[6]?message data 3[6] h'facd hcan1 md3[7]?message data 3[7] h'face hcan1 md3[8]?message data 3[8] h'facf hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1318 of 1484 rej09b0103-0600 md4[1]?message data 4[1] h'fad0 hcan1 md4[2]?message data 4[2] h'fad1 hcan1 md4[3]?message data 4[3] h'fad2 hcan1 md4[4]?message data 4[4] h'fad3 hcan1 md4[5]?message data 4[5] h'fad4 hcan1 md4[6]?message data 4[6] h'fad5 hcan1 md4[7]?message data 4[7] h'fad6 hcan1 md4[8]?message data 4[8] h'fad7 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1319 of 1484 rej09b0103-0600 md5[1]?message data 5[1] h'fad8 hcan1 md5[2]?message data 5[2] h'fad9 hcan1 md5[3]?message data 5[3] h'fada hcan1 md5[4]?message data 5[4] h'fadb hcan1 md5[5]?message data 5[5] h'fadc hcan1 md5[6]?message data 5[6] h'fadd hcan1 md5[7]?message data 5[7] h'fade hcan1 md5[8]?message data 5[8] h'fadf hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1320 of 1484 rej09b0103-0600 md6[1]?message data 6[1] h'fae0 hcan1 md6[2]?message data 6[2] h'fae1 hcan1 md6[3]?message data 6[3] h'fae2 hcan1 md6[4]?message data 6[4] h'fae3 hcan1 md6[5]?message data 6[5] h'fae4 hcan1 md6[6]?message data 6[6] h'fae5 hcan1 md6[7]?message data 6[7] h'fae6 hcan1 md6[8]?message data 6[8] h'fae7 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1321 of 1484 rej09b0103-0600 md7[1]?message data 7[1] h'fae8 hcan1 md7[2]?message data 7[2] h'fae9 hcan1 md7[3]?message data 7[3] h'faea hcan1 md7[4]?message data 7[4] h'faeb hcan1 md7[5]?message data 7[5] h'faec hcan1 md7[6]?message data 7[6] h'faed hcan1 md7[7]?message data 7[7] h'faee hcan1 md7[8]?message data 7[8] h'faef hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1322 of 1484 rej09b0103-0600 md8[1]?message data 8[1] h'faf0 hcan1 md8[2]?message data 8[2] h'faf1 hcan1 md8[3]?message data 8[3] h'faf2 hcan1 md8[4]?message data 8[4] h'faf3 hcan1 md8[5]?message data 8[5] h'faf4 hcan1 md8[6]?message data 8[6] h'faf5 hcan1 md8[7]?message data 8[7] h'faf6 hcan1 md8[8]?message data 8[8] h'faf7 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1323 of 1484 rej09b0103-0600 md9[1]?message data 9[1] h'faf8 hcan1 md9[2]?message data 9[2] h'faf9 hcan1 md9[3]?message data 9[3] h'fafa hcan1 md9[4]?message data 9[4] h'fafb hcan1 md9[5]?message data 9[5] h'fafc hcan1 md9[6]?message data 9[6] h'fafd hcan1 md9[7]?message data 9[7] h'fafe hcan1 md9[8]?message data 9[8] h'faff hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1324 of 1484 rej09b0103-0600 md10[1]?message data 10[1] h'fb00 hcan1 md10[2]?message data 10[2] h'fb01 hcan1 md10[3]?message data 10[3] h'fb02 hcan1 md10[4]?message data 10[4] h'fb03 hcan1 md10[5]?message data 10[5] h'fb04 hcan1 md10[6]?message data 10[6] h'fb05 hcan1 md10[7]?message data 10[7] h'fb06 hcan1 md10[8]?message data 10[8] h'fb07 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1325 of 1484 rej09b0103-0600 md11[1]?message data 11[1] h'fb08 hcan1 md11[2]?message data 11[2] h'fb09 hcan1 md11[3]?message data 11[3] h'fb0a hcan1 md11[4]?message data 11[4] h'fb0b hcan1 md11[5]?message data 11[5] h'fb0c hcan1 md11[6]?message data 11[6] h'fb0d hcan1 md11[7]?message data 11[7] h'fb0e hcan1 md11[8]?message data 11[8] h'fb0f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1326 of 1484 rej09b0103-0600 md12[1]?message data 12[1] h'fb10 hcan1 md12[2]?message data 12[2] h'fb11 hcan1 md12[3]?message data 12[3] h'fb12 hcan1 md12[4]?message data 12[4] h'fb13 hcan1 md12[5]?message data 12[5] h'fb14 hcan1 md12[6]?message data 12[6] h'fb15 hcan1 md12[7]?message data 12[7] h'fb16 hcan1 md12[8]?message data 12[8] h'fb17 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1327 of 1484 rej09b0103-0600 md13[1]?message data 13[1] h'fb18 hcan1 md13[2]?message data 13[2] h'fb19 hcan1 md13[3]?message data 13[3] h'fb1a hcan1 md13[4]?message data 13[4] h'fb1b hcan1 md13[5]?message data 13[5] h'fb1c hcan1 md13[6]?message data 13[6] h'fb1d hcan1 md13[7]?message data 13[7] h'fb1e hcan1 md13[8]?message data 13[8] h'fb1f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1328 of 1484 rej09b0103-0600 md14[1]?message data 14[1] h'fb20 hcan1 md14[2]?message data 14[2] h'fb21 hcan1 md14[3]?message data 14[3] h'fb22 hcan1 md14[4]?message data 14[4] h'fb23 hcan1 md14[5]?message data 14[5] h'fb24 hcan1 md14[6]?message data 14[6] h'fb25 hcan1 md14[7]?message data 14[7] h'fb26 hcan1 md14[8]?message data 14[8] h'fb27 hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1329 of 1484 rej09b0103-0600 md15[1]?message data 15[1] h'fb28 hcan1 md15[2]?message data 15[2] h'fb29 hcan1 md15[3]?message data 15[3] h'fb2a hcan1 md15[4]?message data 15[4] h'fb2b hcan1 md15[5]?message data 15[5] h'fb2c hcan1 md15[6]?message data 15[6] h'fb2d hcan1 md15[7]?message data 15[7] h'fb2e hcan1 md15[8]?message data 15[8] h'fb2f hcan1 note: these registers are not available in the h8s/2635 and h8s/2634. bit initial value read/write mdx[1] bit initial value read/write mdx[2] bit initial value read/write mdx[3] bit initial value read/write mdx[4] bit initial value read/write mdx[5] bit initial value read/write mdx[6] bit initial value read/write mdx[7] bit initial value read/write mdx[8] * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w 0 * r/w * : undefined x = 0 to 15 1 * r/w 2 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1330 of 1484 rej09b0103-0600 pwcr1?pwm control register 1 h'fc00 pwm1 7 ? 1 ? 6 ? 1 ? 5 ie 0 r/w 4 cmf 0 r/(w) * 3 cst 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write compare match flag 0 [clearing conditions] ? when 0 is written to cmf after reading cmf = 1 ? when the dtc is activated by a compare match interrupt, and the disel bit in the dtc?s mrb register is 0 1 [setting condition] ? when pwcnt = pwcyr note: * only 0 can be written, to clear the flag. * : don't care clock select 0 internal clock: counts on /1 internal clock: counts on /2 0 1 internal clock: counts on /4 0 internal clock: counts on /8 1 0 1 1 internal clock: counts on /16 * * counter start 0 pwcnt is stopped 1 pwcnt is started interrupt enable 0 interrupt disabled 1 interrupt enabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1331 of 1484 rej09b0103-0600 pwocr1?pwm output control register 1 h'fc02 pwm1 7 oe1h 0 r/w 6 oe1g 0 r/w 5 oe1f 0 r/w 4 oe1e 0 r/w 3 oe1d 0 r/w 0 oe1a 0 r/w 2 oe1c 0 r/w 1 oe1b 0 r/w bit initial value read/write output enable 0 pwm output is disabled 1 pwm output is enabled pwpr1?pwm polarity register 1 h'fc04 pwm1 7 ops1h 0 r/w 6 ops1g 0 r/w 5 ops1f 0 r/w 4 ops1e 0 r/w 3 ops1d 0 r/w 0 ops1a 0 r/w 2 ops1c 0 r/w 1 ops1b 0 r/w bit initial value read/write output polarity select 0 pwm direct output 1 pwm inverse output pwcyr1?pwm cycle register 1 h'fc06 pwm1 15 ? 1 ? bit initial value read/write set the pwm conversion cycle 14 ? 1 ? 13 ? 1 ? 12 ? 1 ? 11 ? 1 ? 10 ? 1 ? 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1332 of 1484 rej09b0103-0600 pwbfr1a?pwm buffer register 1a h'fc08 pwm1 pwbfr1c?pwm buffer register 1c h'fc0a pwm1 pwbfr1e?pwm buffer register 1e h'fc0c pwm1 pwbfr1g?pwm buffer register 1g h'fc0e pwm1 15 ? 1 ? bit initial value read/write note: when a pwcyr1 compare match occurs, data is transferred from pwbfr1a to pwdtr1a, from pwbfr1c to pwdtr1c, from pwbfr1e to pwdtr1e, and from pwbfr1g to pwdtr1g. 14 ? 1 ? 13 ? 1 ? 12 ots 0 r/w 11 ? 1 ? 10 ? 1 ? 9 dt9 0 r/w 8 dt8 0 r/w 7 dt7 0 r/w 6 dt6 0 r/w 5 dt5 0 r/w 4 dt4 0 r/w 3 dt3 0 r/w 2 dt2 0 r/w 1 dt1 0 r/w 0 dt0 0 r/w duty bits 9 to 0 comprise the data transferred to bits 9 to 0 in pwdtr1 output terminal select bit 12 is the data transferred to bit 12 of pwdtr1 description pwm1a output selected ots 0 pwm1b output selected 1 pwm1c output selected 0 pwm1d output selected pwm1e output selected 1 0 pwm1f output selected 1 pwm1g output selected register pwdtr1a pwdtr1c pwdtr1e pwdtr1g 0 pwm1h output selected 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1333 of 1484 rej09b0103-0600 pwcr2?pwm control register 2 h'fc10 pwm2 7 ? 1 ? 6 ? 1 ? 5 ie 0 r/w 4 cmf 0 r/(w) * 3 cst 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write compare match flag 0 [clearing conditions] ? when 0 is written to cmf after reading cmf = 1 ? when the dtc is activated by a compare match interrupt, and the disel bit in the dtc ? s mrb register is 0 1 [setting condition] ? when pwcnt = pwcyr note: * only 0 can be written, to clear the flag. * : don't care clock select 0 internal clock: counts on /1 internal clock: counts on /2 0 1 internal clock: counts on /4 0 internal clock: counts on /8 1 0 1 1 internal clock: counts on /16 * * counter start 0 pwcnt is stopped 1 pwcnt is started interrupt enable 0 interrupt disabled 1 interrupt enabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1334 of 1484 rej09b0103-0600 pwocr2?pwm output control register 2 h'fc12 pwm2 7 oe2h 0 r/w 6 oe2g 0 r/w 5 oe2f 0 r/w 4 oe2e 0 r/w 3 oe2d 0 r/w 0 oe2a 0 r/w 2 oe2c 0 r/w 1 oe2b 0 r/w bit initial value read/write output enable 0 pwm output is disabled 1 pwm output is enabled pwpr2?pwm polarity register 2 h'fc14 pwm2 7 ops2h 0 r/w 6 ops2g 0 r/w 5 ops2f 0 r/w 4 ops2e 0 r/w 3 ops2d 0 r/w 0 ops2a 0 r/w 2 ops2c 0 r/w 1 ops2b 0 r/w bit initial value read/write output polarity select 0 pwm direct output 1 pwm inverse output pwcyr2?pwm cycle register 2 h'fc16 pwm2 15 ? 1 ? bit initial value read/write set the pwm conversion cycle 14 ? 1 ? 13 ? 1 ? 12 ? 1 ? 11 ? 1 ? 10 ? 1 ? 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1335 of 1484 rej09b0103-0600 pwbfr2a?pwm buffer register 2a h'fc18 pwm2 pwbfr2b?pwm buffer register 2b h'fc1a pwm2 pwbfr2c?pwm buffer register 2c h'fc1c pwm2 pwbfr2d?pwm buffer register 2d h'fc1e pwm2 15 ? 1 ? bit initial value read/write note: when a pwcyr2 compare match occurs, data is transferred from pwbfr2a to pwdtr2a or pwdtr2e, from pwbfr2b to pwdtr2b or pwdtr2f, from pwbfr2c to pwdtr2c or pwdtr2g, and from pwbfr2d to pwdtr2d or pwdtr2h. 14 ? 1 ? 13 ? 1 ? 12 tds 0 r/w 11 ? 1 ? 10 ? 1 ? 9 dt9 0 r/w 8 dt8 0 r/w 7 dt7 0 r/w 6 dt6 0 r/w 5 dt5 0 r/w 4 dt4 0 r/w 3 dt3 0 r/w 2 dt2 0 r/w 1 dt1 0 r/w 0 dt0 0 r/w duty bits 9 to 0 compromise the data transferred to bits 9 to 0 in pwdtr2 transfer destination select selects the pwdtr2 register to which data is to be transferred description pwdtr2a selected tds 0 pwdtr2e selected 1 pwdtr2b selected 0 pwdtr2f selected pwdtr2c selected 1 0 pwdtr2g selected 1 pwdtr2d selected register pwbfr2a pwbfr2b pwbfr2c pwbfr2d 0 pwdtr2h selected 1 phddr?port h data direction register h'fc20 port 7 ph7ddr 0 w 6 ph6ddr 0 w 5 ph5ddr 0 w 4 ph4ddr 0 w 3 ph3ddr 0 w 0 ph0ddr 0 w 2 ph2ddr 0 w 1 ph1ddr 0 w bit initial value read/write
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1336 of 1484 rej09b0103-0600 pjddr?port j data direction register h'fc21 port 7 pj7ddr 0 w 6 pj6ddr 0 w 5 pj5ddr 0 w 4 pj4ddr 0 w 3 pj3ddr 0 w 0 pj0ddr 0 w 2 pj2ddr 0 w 1 pj1ddr 0 w bit initial value read/write phdr?port h data register h'fc24 port 7 ph7dr 0 r/w 6 ph6dr 0 r/w 5 ph5dr 0 r/w 4 ph4dr 0 r/w 3 ph3dr 0 r/w 0 ph0dr 0 r/w 2 ph2dr 0 r/w 1 ph1dr 0 r/w bit initial value read/write pjdr?port j data register h'fc25 port 7 pj7dr 0 r/w 6 pj6dr 0 r/w 5 pj5dr 0 r/w 4 pj4dr 0 r/w 3 pj3dr 0 r/w 0 pj0dr 0 r/w 2 pj2dr 0 r/w 1 pj1dr 0 r/w bit initial value read/write porth?port h register h'fc28 port 7 ph7 ? * r 6 ph6 ? * r 5 ph5 ? * r 4 ph4 ? * r 3 ph3 ? * r 0 ph0 ? * r 2 ph2 ? * r 1 ph1 ? * r bit initial value read/write note: * determined by the state of ph7 to ph0. portj?port j register h'fc29 port 7 pj7 ? * r 6 pj6 ? * r 5 pj5 ? * r 4 pj4 ? * r 3 pj3 ? * r 0 pj0 ? * r 2 pj2 ? * r 1 pj1 ? * r bit initial value read/write note: * determined by the state of pj7 to pj0.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1337 of 1484 rej09b0103-0600 mstpcrd?module stop control register d h'fc60 system 7 mstpd7 1 r/w 6 mstpd6 1 r/w 5 mstpd5 undefined ? 4 mstpd4 undefined ? 3 mstpd3 undefined ? 0 mstpd0 undefined ? 2 mstpd2 undefined ? 1 mstpd1 undefined ? bit initial value read/write module stop 0 pwm module stop mode is cleared 1 pwm module stop mode is set scrx?serial control register x h'fdb4 iic 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 ? 1 ? 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w i 2 c transfer rate select 1, 0 i 2 c master enable bit initial value r/w : : : 0 disables cpu access of i 2 c bus interface data register and control register 1 enables cpu access of i 2 c bus interface data register and control register note: this register is valid only when an i 2 c bus interface has been added as an h8s/2638, h8s/2639, and h8s/2630 option.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1338 of 1484 rej09b0103-0600 ddcswr?ddc switch register h'fdb5 iic 7 ? 0 r/(w) * 1 6 ? 0 r/(w) * 1 5 ? 0 r/(w) * 1 4 ? 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 reserved bit bit initial value r/w : : : iic clear 3 to 0 clr3 clr2 clr1 clr0 0 0 ? ? 1 0 0 1 1 0 1 1 ? ? ? setting prohibited setting prohibited iic0 internal latch cleared iic1 internal latch cleared iic0 and iic1 internal latches cleared invalid setting notes: this register is valid only when an i 2 c bus interface has been added as an h8s/2638, h8s/2639, and h8s/2630 option. 1. should always be written with 0. 2. always read as 1.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1339 of 1484 rej09b0103-0600 sbycr?standby control register h'fde4 system 7 ssby 0 r/w 6 sts2 1 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ope 1 r/w 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit initial value read/write output port enable 0 in software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance 1 in software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained software standby 0 shifts to sleep mode when the sleep instruction is executed in high-speed mode or medium-speed mode shifts to sub-sleep mode when the sleep instruction is executed in sub-active mode 1 shifts to software standby mode, sub-active mode, and watch mode when the sleep instruction is executed in high-speed mode or medium-speed mode shifts to watch mode or high-speed mode when the sleep instruction is executed in sub-active mode standby timer select 2 to 0 standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states reserved standby time = 16 states (setting prohibited) 0 1 0 1 0 1 0 1 0 1 0 1 0 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1340 of 1484 rej09b0103-0600 syscr?system control register h'fde5 system 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 ? 0 ? 1 ? 0 ? bit initial value read/write ram enable 0 on-chip ram is disabled 1 on-chip ram is enabled 0 control of interrupts by i bit setting prohibited 1 control of interrupts by i2 to i0 bits and ipr setting prohibited 0 1 0 1 0 ? 2 ? nmi edge select 0 an interrupt is requested at the falling edge of nmi input 1 an interrupt is requested at the rising edge of nmi input interrupt control mode 1 and 0 interrupt control mode intm1 intm0 description mac saturation 0 non-saturating calculation for mac instruction 1 saturating calculation for mac instruction
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1341 of 1484 rej09b0103-0600 sckcr?system clock control register h'fde6 system 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value read/write bus master in high-speed mode medium-speed clock is /2 medium-speed clock is /4 medium-speed clock is /8 medium-speed clock is /16 medium-speed clock is /32 ? 0 1 0 1 0 1 frequency multiplication factor switching mode select 0 specified multiplication factor is valid after transition to software standby mode, watch mode * , or subactive mode * 1 specified multiplication factor is valid immediately after stc bits are rewritten clock output disable system clock select 0 1 0 1 0 1 ? ddr pstop hardware standby mode software standby mode, watch mode * , and direct transition sleep mode and subsleep mode * high-speed mode, medium-speed mode, and subactive mode * 0 ? high impedance high impedance high impedance high impedance 1 0 high impedance fixed high output output 1 1 high impedance fixed high fixed high fixed high note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask and w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1342 of 1484 rej09b0103-0600 mdcr?mode control register h'fde7 system 7 ? 1 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? * r 2 mds2 ? * r 1 mds1 ? * r bit initial value read/write mode select 2 to 0 indicate the input levels at pins md2 to md0 note: * determined by pins md2 to md0. mstpcra?module stop control register a h'fde8 system 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value read/write module stop 0 module stop mode is cleared module stop mode is set 1 mstpcrb?module stop control register b h'fde9 system 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value read/write module stop 0 module stop mode is cleared module stop mode is set 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1343 of 1484 rej09b0103-0600 mstpcrc?module stop control register c h'fdea system 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value read/write module stop 0 module stop mode is cleared module stop mode is set 1 pfcr?pin function control register h'fdeb system 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 1 r/w bit initial value read/write note: * in on-chip rom-enabled expansion mode, bits ae3 to ae0 are initialized to b'0000. in on-chip rom-disabled expansion mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1. address output enable 3 to 0 a8 to a23 address output disabled a8 address output enabled; a9 to a23 address output disabled a8, a9 address output enabled; a10 to a23 address output disabled a8 to a10 address output enabled; a11 to a23 address output disabled a8 to a11 address output enabled; a12 to a23 address output disabled a8 to a12 address output enabled; a13 to a23 address output disabled a8 to a13 address output enabled; a14 to a23 address output disabled a8 to a14 address output enabled; a15 to a23 address output disabled a8 to a15 address output enabled; a16 to a23 address output disabled a8 to a16 address output enabled; a17 to a23 address output disabled a8 to a17 address output enabled; a18 to a23 address output disabled a8 to a18 address output enabled; a19 to a23 address output disabled a8 to a19 address output enabled; a20 to a23 address output disabled a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * ) a8 to a21 address output enabled; a22, a23 address output disabled a8 to a23 address output enabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1344 of 1484 rej09b0103-0600 lpwrcr?low-power control register h'fdec system 7 dton * 1 0 r/w 6 lson * 1 0 r/w 5 nesel * 1 0 r/w 4 substp * 1 0 r/w 3 rfcut * 1 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit initial value read/write frequency multiplication factor 0 1 2 4 setting prohibited 0 1 10 1 oscillation circuit feedback resistance control bit 0 when the main clock is oscillating, sets the feedback resistance on. when the main clock is stopped, sets the feedback resistance off 1 sets the feedback resistance off subclock enable 0 enables subclock generation disables subclock generation 1 noise elimination sampling frequency select 0 sampling using 1/32 sampling using 1/4 1 low-speed on flag 0 ? when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * ? when the sleep instruction is executed in sub-active mode, operation shifts to watch mode or shifts directly to high-speed mode ? operation shifts to high-speed mode when watch mode is cancelled ? when the sleep instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode ? when the sleep instruction is executed in sub-active mode, operation shifts to sub- sleep mode or watch mode ? operation shifts to sub-active mode when watch mode is cancelled 1 direct transition on flag 0 ? when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * ? when the sleep instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode ? when the sleep instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode * , or shifts to sleep mode or software standby mode ? when the sleep instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode 1 note: * always set high-speed mode when shifting to watch mode or sub-active mode. note: always set high-speed mode when shifting to watch mode or sub-active mode. * note: 1. bits 7 to 3 in lpwrcr are valid in the u-mask and w-mask versions, and h8s/2635 group; they are reserved bits in all other versions. see sections 23a.2.3, 23b.2.3, low-power control register (lpwrcr), for more information.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1345 of 1484 rej09b0103-0600 bara?break address register a h'fe00 pbc barb?break address register b h'fe04 pbc bit initial value read/write ? ? 31 unde- fined ? ? 24 unde- fined r/w baa 23 23 0 r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w break address 23 to 0 specify the channel a or b break address baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/w 0 baa 0 0 . . . . . . . . . . . . . . . . . . . . . . . . notes: 1. the bit configuration of barb is the same as for bara. 2. these registers are not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1346 of 1484 rej09b0103-0600 bcra?break control register a bcrb?break control register b h'fe08 h'fe09 pbc pbc break condition select 0 instruction fetch is used as break condition data read cycle is used as break condition data write cycle is used as break condition data read/write cycle is used as break condition 0 1 10 1 7 cmfa 0 r/(w) * 6 cda 0 r/w 5 bamra2 0 r/w 4 bamra1 0 r/w 3 bamra0 0 r/w 0 biea 0 r/w 2 csela1 0 r/w 1 csela0 0 r/w bit initial value read/write break address mask register 0 all bara bits are unmasked and included in break conditions baa0 (lowest bit) is masked, and not included in break conditions baa1, baa0 (lower 2 bits) are masked, and not included in break conditions baa2 to baa0 (lower 3 bits) are masked, and not included in break conditions baa3 to baa0 (lower 4 bits) are masked, and not included in break conditions baa7 to baa0 (lower 8 bits) are masked, and not included in break conditions baa11 to baa0 (lower 12 bits) are masked, and not included in break conditions baa15 to baa0 (lower 16 bits) are masked, and not included in break conditions 0 1 0 1 0 1 10 1 0 1 0 1 break interrupt enable 0 pc break interrupts are disabled pc break interrupts are enabled 1 cpu cycle/dtc cycle select a 0 pc break is performed when cpu is bus master pc break is performed when cpu or dtc is bus master 1 condition match flag a 0 [clearing condition] when 0 is written to cmfa after reading cmfa = 1 [setting condition] when a condition set for channel a is satisfied 1 notes: 1. the bit configuration of bcrb is the same as for bcra. 2. these registers are not available in the h8s/2635 and h8s/2634. * only a 0 may be written to this bit to clear the flag.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1347 of 1484 rej09b0103-0600 iscrh?irq sence control register h h'fe12 interrupt controller iscrl?irq sence control register l h'fe13 interrupt controller 15 ? 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value read/write iscrh 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value read/write iscrl irq5 to irq0 sense control a and b description irq5scb to irq0scb irq5sca to irq0sca 0 1 0 1 0 1 interrupt request generated at irq5 to irq0 input at low level interrupt request generated at falling edge of irq5 to irq0 input interrupt request generated at rising edge of irq5 to irq0 input interrupt request generated at both falling and rising edges of irq5 to irq0 input
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1348 of 1484 rej09b0103-0600 ier?irq enable register h'fe14 interrupt controller 7 ? 0 r/w 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value read/write irq5 to irq0 enable (n = 5 to 0) 0 irqn interrupts disabled irqn interrupts enabled 1 isr?irq status register h'fe15 interrupt controller 7 ? 0 r/(w) * 6 ? 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value read/write irq5 to irq0 flags 0 [clearing conditions] ? cleared by reading irqnf when set to 1, then writing 0 in irqnf ? when interrupt exception handling is executed while low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed while falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input while falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input while rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input while both-edge detection is set (irqnscb = irqnsca = 1) note: * only 0 can be written, to clear the flag. (n = 5 to 0)
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1349 of 1484 rej09b0103-0600 dtcera?dtc enable register a dtcerb?dtc enable register b dtcerc?dtc enable register c dtcerd?dtc enable register d dtcere?dtc enable register e dtcerf?dtc enable register f dtcerg?dtc enable register g h'fe16 h'fe17 h'fe18 h'fe19 h'fe1a h'fe1b h'fe1c dtc dtc dtc dtc dtc dtc dtc note: these registers are not available in the h8s/2635 and h8s/2634. 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value read/write dtc activation enable 0 dtc activation by interrupt is disabled [clearing conditions] ? when data transfer ends with the disel bit set to 1 ? when the specified number of transfers end 1 dtc activation by interrupt is enabled [holding condition] ? when the disel bit is 0 and the specified number of transfers have not ended
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1350 of 1484 rej09b0103-0600 dtvecr?dtc vector register h'fe1f dtc 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 bit initial value read/write notes: set vector number for dtc software activation dtc software activation enable 0 dtc software activation is disabled [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 is written to disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu. 1 dtc software activation is enabled [holding conditions] ? when data transfer ends with the disel bit set to 1 ? when the specified number of transfers end ? during software-activated deta transfer this register is not available in the h8s/2635 and h8s/2634. 1. only 1 can be written to the swdte bit. 2. bits dtvec6 to dtvec0 can be written to when swdte = 0.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1351 of 1484 rej09b0103-0600 pcr?ppg output control register h'fe26 ppg 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 0 g0cms0 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w bit initial value read/write group 0 compare match select 0 1 compare match in tpu channel 0 compare match in tpu channel 1 compare match in tpu channel 2 compare match in tpu channel 3 0 1 0 1 group 1 compare match select 0 1 compare match in tpu channel 0 compare match in tpu channel 1 compare match in tpu channel 2 compare match in tpu channel 3 0 1 0 1 group 2 compare match select 0 1 compare match in tpu channel 0 compare match in tpu channel 1 compare match in tpu channel 2 compare match in tpu channel 3 0 1 0 1 group 3 compare match select 0 1 compare match in tpu channel 0 compare match in tpu channel 1 compare match in tpu channel 2 compare match in tpu channel 3 0 1 0 1 note: this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1352 of 1484 rej09b0103-0600 pmr?ppg output mode register h'fe27 ppg 7 g3inv 1 r/w 6 g2inv 1 r/w 5 g1inv 1 r/w 4 g0inv 1 r/w 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w bit initial value read/write group 0 non-overlap 0 normal operation in pulse output group 0 (output values updated at compare match a in the selected tpu channel) non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match a or b in the selected tpu channel) 1 group 1 non-overlap 0 normal operation in pulse output group 1 (output values updated at compare match a in the selected tpu channel) non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match a or b in the selected tpu channel) 1 group 2 non-overlap 0 normal operation in pulse output group 2 (output values updated at compare match a in the selected tpu channel) non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match a or b in the selected tpu channel) 1 group 3 non-overlap 0 normal operation in pulse output group 3 (output values updated at compare match a in the selected tpu channel) non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match a or b in the selected tpu channel) 1 group 3 inversion 0 inverted output for pulse output group 3 (low-level output at pin for a 1 in podrh) direct output for pulse output group 3 (high-level output at pin for a 1 in podrh) 1 group 2 inversion 0 inverted output for pulse output group 2 (low-level output at pin for a 1 in podrh) direct output for pulse output group 2 (high-level output at pin for a 1 in podrh) 1 group 1 inversion 0 inverted output for pulse output group 1 (low-level output at pin for a 1 in podrl) direct output for pulse output group 1 (high-level output at pin for a 1 in podrl) 1 group 0 inversion 0 inverted output for pulse output group 0 (low-level output at pin for a 1 in podrl) direct output for pulse output group 0 (high-level output at pin for a 1 in podrl) 1 note: this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1353 of 1484 rej09b0103-0600 nderh?next data enable register h h'fe28 ppg 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 0 nder8 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w bit initial value read/write next data enable 0 pulse outputs po15 to po8 are disabled (ndr15 to ndr8 are not transferred to pod15 to pod8) pulse outputs po15 to po8 are enabled (ndr15 to ndr8 are transferred to pod15 to pod8) 1 note: this register is not available in the h8s/2635 and h8s/2634. nderl?next data enable register l h'fe29 ppg 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 0 nder0 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w bit initial value read/write next data enable 0 pulse outputs po7 to po0 are disabled (ndr7 to ndr0 are not transferred to pod7 to pod0 pulse outputs po7 to po0 are enabled (ndr7 to ndr0 are transferred to pod7 to pod0) 1 note: this register is not available in the h8s/2635 and h8s/2634. podrh?output data register h h'fe2a ppg 7 pod15 0 r/(w) * 6 pod14 0 r/(w) * 5 pod13 0 r/(w) * 4 pod12 0 r/(w) * 3 pod11 0 r/(w) * 0 pod8 0 r/(w) * 2 pod10 0 r/(w) * 1 pod9 0 r/(w) * bit initial value read/write notes: this register is not available in the h8s/2635 and h8s/2634. * a bit that has been set for pulse output by nder is read-only.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1354 of 1484 rej09b0103-0600 podrl?output data register l h'fe2b ppg 7 pod7 0 r/(w) * 6 pod6 0 r/(w) * 5 pod5 0 r/(w) * 4 pod4 0 r/(w) * 3 pod3 0 r/(w) * 0 pod0 0 r/(w) * 2 pod2 0 r/(w) * 1 pod1 0 r/(w) * bit initial value read/write notes: this register is not available in the h8s/2635 and h8s/2634. * a bit that has been set for pulse output by nder is read-only.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1355 of 1484 rej09b0103-0600 ndrh?next data register h h'fe2c, h'fe2e ppg 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value read/write a ddress h'fe2c 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value read/write a ddress h'fe2e same trigger for pulse output groups 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value read/write a ddress h'fe2c 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value read/write a ddress h'fe2e different triggers for pulse output groups notes: 1. for details, see section 11.2.4, notes on ndr access. 2. this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1356 of 1484 rej09b0103-0600 ndrl?next data register l h'fe2d, h'fe2f ppg 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value read/write a ddress h'fe2d 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value read/write a ddress h'fe2f same trigger for pulse output groups 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value read/write a ddress h'fe2d 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value read/write a ddress h'fe2f different triggers for pulse output groups notes: 1. for details, see section 11.2.4, notes on ndr access. 2. this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1357 of 1484 rej09b0103-0600 p1ddr?port 1 data direction register h'fe30 port 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write specify input or output for each of the pins in port 1 p3ddr?port 3 data direction register h'fe32 port 7 ? undefined ? 6 ? undefined ? 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value read/write specify input or output for each of the pins in port 3 paddr?port a data direction register h'fe39 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value read/write specify input or output for each of the pins in port a pbddr?port b data direction register h'fe3a port 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value read/write specify input or output for each of the pins in port b
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1358 of 1484 rej09b0103-0600 pcddr?port c data direction register h'fe3b port 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value read/write specify input or output for each of the pins in port c pdddr?port d data direction register h'fe3c port 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value read/write specify input or output for each of the pins in port d peddr?port e data direction register h'fe3d port 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value read/write specify input or output for each of the pins in port e
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1359 of 1484 rej09b0103-0600 pfddr?port f data direction register h'fe3e port 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 ? undefined ? undefined ? 1 ? undefined ? undefined ? bit modes 4, 5, 6 initial value read/write mode 7 initial value read/write specify input or output for each of the pins in port f papcr?port a mos pull-up control register h'fe40 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value read/write control the mos input pull-up function incorporated into port a pbpcr?port b mos pull-up control register h'fe41 port 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value read/write control the mos input pull-up function incorporated into port b pcpcr?port c mos pull-up control register h'fe42 port 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value read/write control the mos input pull-up function incorporated into port c
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1360 of 1484 rej09b0103-0600 pdpcr?port d mos pull-up control register h'fe43 port 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value read/write control the mos input pull-up function incorporated into port d pepcr?port e mos pull-up control register h'fe44 port 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value read/write control the mos input pull-up function incorporated into port e p3odr?port 3 open drain control register h'fe46 port 7 ? undefined ? 6 ? undefined ? 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value read/write paodr?port a open drain control register h'fe47 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value read/write
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1361 of 1484 rej09b0103-0600 pbodr?port b open drain control register h'fe48 port 7 pb7odr 0 r/w 6 pb6odr 0 r/w 5 pb5odr 0 r/w 4 pb4odr 0 r/w 3 pb3odr 0 r/w 0 pb0odr 0 r/w 2 pb2odr 0 r/w 1 pb1odr 0 r/w bit initial value read/write pcodr?port c open drain control register h'fe49 port 7 pc7odr 0 r/w 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 0 pc0odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w bit initial value read/write
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1362 of 1484 rej09b0103-0600 tcr3?timer control register 3 h'fe80 tpu3 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write time prescaler 0 internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input internal clock: counts on /1024 internal clock: counts on /256 internal clock: counts on /4096 0 1 0 1 0 1 10 1 0 1 0 1 counter clear 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 0 1 0 1 0 1 10 1 0 1 0 1 notes: 1. 2. synchronous operation setting is performed by setting the sync bit in tsyr to 1. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 ? note: internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1363 of 1484 rej09b0103-0600 tmdr3?timer mode register 3 h'fe81 tpu3 7 ? 1 ? 6 ? 1 ? 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write buffer operation a * : don't care 0 tgra operates normally tgra and tgrc used together for buffer operation 1 buffer operation 0 tgrb operates normally tgrb and tgrd used together for buffer operation 1 notes: 1. 2. md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channel 3. in this case, 0 should always be written to md2. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1364 of 1484 rej09b0103-0600 tior3h?timer i/o control register 3h h'fe82 tpu3 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : don't care tgr3a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down tgr3a is output compare register tgr3a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr3b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 1 tgr3b is output compare register tgr3b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1365 of 1484 rej09b0103-0600 tior3l?timer i/o control register 3l h'fe83 tpu3 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w bit initial value read/write * : don't care tgr3c i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down tgr3c is output compare register * 1 tgr3c is input capture register * 1 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocc3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr3d i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 1 tgr3d is output compare register * 2 tgr3d is input capture register * 2 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * notes: 1. 2. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1366 of 1484 rej09b0103-0600 tier3?timer interrupt enable register 3 h'fe84 tpu3 7 ttge 0 r/w 6 ? 1 ? 5 ? 0 ? 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 tgr interrupt enable c 0 interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled 1 tgr interrupt enable d 0 interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1367 of 1484 rej09b0103-0600 tsr3?timer status register 3h'fe85 tpu3 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register input capture/output compare flag c 0 [clearing conditions] ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register input capture/output compare flag d 0 [clearing conditions] ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1368 of 1484 rej09b0103-0600 tcnt3?timer counter 3h'fe86tpu3 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr3a?timer general register 3a h'fe88 tpu3 tgr3b?timer general register 3b h'fe8a tpu3 tgr3c?timer general register 3c h'fe8c tpu3 tgr3d?timer general register 3d h'fe8e tpu3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1369 of 1484 rej09b0103-0600 tcr4?timer control register 4 h'fe90 tpu4 bit initial value read/write clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 ? time prescaler 0 internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on /1024 counts on tcnt5 overflow/underflow 0 1 0 1 0 1 10 1 0 1 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 0 1 0 1 note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 4 is in phase counting mode. note: this setting is ignored when channel 4 is in phase counting mode. internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 7 ? 0 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1370 of 1484 rej09b0103-0600 tmdr4?timer mode register 4 h'fe91 tpu4 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write * : don't care note: md3 is a reserved bit. in a write, it should always be written with 0. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1371 of 1484 rej09b0103-0600 tior4?timer i/o control register 4h'fe92 tpu4 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : don't care tgr4a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3a compare match/input capture tgr4a is output compare register tgr4a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca4 pin capture input source is tgr3a compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr4b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3c compare match/input capture tgr4b is output compare register tgr4b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb4 pin capture input source is tgr3c compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1372 of 1484 rej09b0103-0600 tier4?timer interrupt enable register 4 h'fe94 tpu4 7 ttge 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 ? 0 ? 0 tgiea 0 r/w 2 ? 0 ? 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 underflow interrupt enable 0 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1373 of 1484 rej09b0103-0600 tsr4?timer status register 4h'fe95 tpu4 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 ? 0 ? 0 tgfa 0 r/(w) * 2 ? 0 ? 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) underflow flag 0 [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 tcnt counts down tcnt counts up 1 note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1374 of 1484 rej09b0103-0600 tcnt4?timer counter 4h'fe96tpu4 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up/down-counter * note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. tgr4a?timer general register 4a h'fe98 tpu4 tgr4b?timer general register 4b h'fe9a tpu4 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1375 of 1484 rej09b0103-0600 tcr5?timer control register 5 h'fea0 tpu5 bit initial value read/write time prescaler 0 internal clock: counts on f /1 internal clock: counts on f /4 internal clock: counts on f /16 internal clock: counts on f /64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on f /256 external clock: counts on tclkd pin input 0 1 0 1 0 1 10 1 0 1 0 1 note: this setting is ignored when channel 5 is in phase counting mode. 7 ? 0 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 0 1 0 1 note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 5 is in phase counting mode. internal clock edge selection is valid when the input clock is f /4 or slower. this setting is ignored if the input clock is f /1, or when overflow/underflow of another channel is selected.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1376 of 1484 rej09b0103-0600 tmdr5?timer mode register 5 h'fea1 tpu5 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write * : dont care note: md3 is a reserved bit. in a write, it should always be written with 0. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1377 of 1484 rej09b0103-0600 tior5?timer i/o control register 5h'fea2 tpu5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : dont care tgr5a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr5a is output compare register tgr5a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * * : dont care tgr5b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr5b is output compare register tgr5b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1378 of 1484 rej09b0103-0600 tier5?timer interrupt enable register 5 h'fea4 tpu5 7 ttge 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 ? 0 ? 0 tgiea 0 r/w 2 ? 0 ? 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 underflow interrupt enable 0 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1379 of 1484 rej09b0103-0600 tsr5?timer status register 5h'fea5 tpu5 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 ? 0 ? 0 tgfa 0 r/(w) * 2 ? 0 ? 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) underflow flag 0 [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 tcnt counts down tcnt counts up 1 note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1380 of 1484 rej09b0103-0600 tcnt5?timer counter 5h'fea6tpu5 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up/down-counter * note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. tgr5a?timer general register 5a h'fea8 tpu5 tgr5b?timer general register 5b h'feaa tpu5 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tstr?timer start register h'feb0 tpu 7 ? 0 ? 6 ? 0 ? 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value read/write (n = 5 to 0) counter start 0 tcntn count operation is stopped tcntn performs count operation 1 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1381 of 1484 rej09b0103-0600 tsyr?timer synchro register h'feb1 tpu 7 ? 0 ? 6 ? 0 ? 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value read/write (n = 5 to 0) timer synchro 0 tcntn operates independently (tcnt presetting/ clearing is unrelated to other channels) tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible 1 notes: 1. 2. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1382 of 1484 rej09b0103-0600 ipra?interrupt priority register a iprb?interrupt priority register b iprc?interrupt priority register c iprd?interrupt priority register d ipre?interrupt priority register e iprf?interrupt priority register f iprg?interrupt priority register g iprh?interrupt priority register h iprj?interrupt priority register j iprk?interrupt priority register k iprl?interrupt priority register l iprm?interrupt priority register m h'fec0 h'fec1 h'fec2 h'fec3 h'fec4 h'fec5 h'fec6 h'fec7 h'fec9 h'feca h'fecb h'fecc int int int int int int int int int int int int 7 ? 0 ? 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 ? 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value read/write correspondence between interrupt sources and ipr settings register ipra iprb iprc iprd ipre iprf iprg iprh iprj iprk iprl iprm bits 6 to 4 irq0 irq2 irq3 ? * 1 watchdog timer 0 pc break * 3 tpu channel 0 tpu channel 2 tpu channel 4 ? * 1 sci channel 1 ? * 1 pwm channel 1, 2, hcan channel 1 * 3 irq1 irq4 irq5 dtc * 3 ? * 1 a/d converter, watchdog timer 1 tpu channel 1 tpu channel 3 tpu channel 5 sci channel 0 sci channel 2 iic (option) * 2 hcan channel 0 2 to 0 notes: 1. 2. 3. reserved. read-only bits, always read as 1. i 2 c bus interface is available as an option in the h8s/2638, h8s/2639, h8s/2630. the iic bit becomes reserved bit when this optional feature is not used. the dtc, pc break, and hcan1 are not implemented in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1383 of 1484 rej09b0103-0600 abwcr?bus width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit modes 5 to 7 initial value read/write mode 4 initial value read/write area 7 to 0 bus width control 0 area n is designated for 16-bit access area n is designated for 8-bit access 1 (n = 7 to 0) astcr?access state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value read/write area 7 to 0 access state control 0 area n is designated for 2-state access wait state insertion in area n external space is disabled area n is designated for 3-state access wait state insertion in area n external space is enabled 1 (n = 7 to 0)
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1384 of 1484 rej09b0103-0600 wcrh?wait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value read/write area 4 wait control 1 and 0 0 program wait not inserted when external space area 4 is accessed 0 1 program wait state inserted when external space area 4 is accessed 1 1 2 program wait states inserted when external space area 4 is accessed 0 3 program wait states inserted when external space area 4 is accessed 1 area 6 wait control 1 and 0 area 7 wait control 1 and 0 0 program wait not inserted when external space area 7 is accessed 0 1 program wait state inserted when external space area 7 is accessed 1 1 2 program wait states inserted when external space area 7 is accessed 0 3 program wait states inserted when external space area 7 is accessed 1 0 program wait not inserted when external space area 6 is accessed 0 1 program wait state inserted when external space area 6 is accessed 1 1 2 program wait states inserted when external space area 6 is accessed 0 3 program wait states inserted when external space area 6 is accessed 1 area 5 wait control 1 and 0 0 program wait not inserted when external space area 5 is accessed 0 1 program wait state inserted when external space area 5 is accessed 1 1 2 program wait states inserted when external space area 5 is accessed 0 3 program wait states inserted when external space area 5 is accessed 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1385 of 1484 rej09b0103-0600 wcrl?wait control register l h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value read/write area 0 wait control 1 and 0 0 program wait not inserted when external space area 0 is accessed 0 1 program wait state inserted when external space area 0 is accessed 1 1 2 program wait states inserted when external space area 0 is accessed 0 3 program wait states inserted when external space area 0 is accessed 1 area 2 wait control 1 and 0 area 3 wait control 1 and 0 0 program wait not inserted when external space area 3 is accessed 0 1 program wait state inserted when external space area 3 is accessed 1 1 2 program wait states inserted when external space area 3 is accessed 0 3 program wait states inserted when external space area 3 is accessed 1 0 program wait not inserted when external space area 2 is accessed 0 1 program wait state inserted when external space area 2 is accessed 1 1 2 program wait states inserted when external space area 2 is accessed 0 3 program wait states inserted when external space area 2 is accessed 1 area 1 wait control 1 and 0 0 program wait not inserted when external space area 1 is accessed 0 1 program wait state inserted when external space area 1 is accessed 1 1 2 program wait states inserted when external space area 1 is accessed 0 3 program wait states inserted when external space area 1 is accessed 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1386 of 1484 rej09b0103-0600 bcrh?bus control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w bit initial value read/write burst cycle select 0 0 max. 4 words in burst access max. 8 words in burst access 1 burst cycle select 1 0 burst cycle comprises 1 state burst cycle comprises 2 states 1 burst rom enable 0 area 0 is basic bus interface area 0 is burst rom interface 1 idle cycle insert 0 0 idle cycle not inserted in case of successive external read and external write cycles idle cycle inserted in case of successive external read and external write cycles 1 0 1 idle cycle insert 1 idle cycle not inserted in case of successive external read cycles in different areas idle cycle inserted in case of successive external read cycles in different areas
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1387 of 1484 rej09b0103-0600 bcrl?bus control register l h'fed5 bus controller 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 ? 4 ? 0 r/w 3 ? 1 r/w 0 ? 0 r/w 2 ? 0 r/w 1 wdbe 0 r/w bit initial value read/write write data buffer enable 0 write data buffer function not used write data buffer function used 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1388 of 1484 rej09b0103-0600 ramer?ram emulation register h'fedb flash memory 7 ? 0 r 6 ? 0 r 5 ? 0 r/w 4 ? 0 r/w 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit initial value read/write ram select 0 emulation not selected program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled flash memory area selection ? h8s/2636 h'ffe000 ? h'ffe3ff h'000000 ? h'0003ff h'000400 ? h'0007ff h'000800 ? h'000bff h'000c00 ? h'000fff ram area 1 kb eb0 (1 kb) eb1 (1 kb) eb2 (1 kb) eb3 (1 kb) ram2 * 0 1 rams 0 1 addresses * : don't care * : don't care block name addresses block name ram1 * 0 1 0 1 ram0 * ? h8s/2638, h8s/2639, h8s/2630 h'ffd000 ? h'ffdfff h'000000 ? h'000fff h'001000 ? h'001fff h'002000 ? h'002fff h'003000 ? h'003fff h'004000 ? h'004fff h'005000 ? h'005fff h'006000 ? h'006fff h'007000 ? h'007fff ram area 4 kb eb0 (4 kb) eb1 (4 kb) eb2 (4 kb) eb3 (4 kb) eb4 (4 kb) eb5 (4 kb) eb6 (4 kb) eb7 (4 kb) rams 0 1 ram2 * 0 1 ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1 * : don't care addresses block name ? h8s/2635 h'ffd800 ? h'ffe7ff h'000000 ? h'000fff h'001000 ? h'001fff h'002000 ? h'002fff h'003000 ? h'003fff h'004000 ? h'004fff h'005000 ? h'005fff h'006000 ? h'006fff h'007000 ? h'007fff ram area 4 kb eb0 (4 kb) eb1 (4 kb) eb2 (4 kb) eb3 (4 kb) eb4 (4 kb) eb5 (4 kb) eb6 (4 kb) eb7 (4 kb) rams 0 1 ram2 * 0 1 ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1389 of 1484 rej09b0103-0600 p1dr?port 1 data register h'ff00 port 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value read/write p3dr?port 3 data register h'ff02 port 7 ? undefined ? 6 ? undefined ? 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value read/write padr?port a data register h'ff09 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value read/write pbdr?port b data register h'ff0a port 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value read/write pcdr?port c data register h'ff0b port 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value read/write
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1390 of 1484 rej09b0103-0600 pddr?port d data register h'ff0c port 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value read/write pedr?port e data register h'ff0d port 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value read/write pfdr?port f data register h'ff0e port 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 ? undefined ? 1 ? undefined ? bit initial value read/write
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1391 of 1484 rej09b0103-0600 tcr0?timer control register 0 h'ff10 tpu0 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write time prescaler 0 internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input external clock: counts on tclkd pin input 0 1 0 1 0 1 10 1 0 1 0 1 counter clear 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 0 1 0 1 0 1 10 1 0 1 0 1 notes: 1. 2. synchronous operation setting is performed by setting the sync bit in tsyr to 1. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 ? note: internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1392 of 1484 rej09b0103-0600 tmdr0?timer mode register 0 h'ff11 tpu0 7 ? 1 ? 6 ? 1 ? 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write buffer operation a * : dont care 0 tgra operates normally tgra and tgrc used together for buffer operation 1 buffer operation 0 tgrb operates normally tgrb and tgrd used together for buffer operation 1 notes: 1. 2. md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channel 0. in this case, 0 should always be written to md2. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1393 of 1484 rej09b0103-0600 tior0h?timer i/o control register 0h h'ff12 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : dont care tgr0a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down tgr0a is output compare register tgr0a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : dont care tgr0b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down * 1 tgr0b is output compare register tgr0b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b000 and f /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1394 of 1484 rej09b0103-0600 tior0l?timer i/o control register 0l h'ff13 tpu0 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w bit initial value read/write * : don't care tgr0c i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down tgr0c is output compare register * 1 tgr0c is input capture register * 1 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocc0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr0d i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down * 1 tgr0d is output compare register * 2 tgr0d is input capture register * 2 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * notes: 1. 2. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1395 of 1484 rej09b0103-0600 tier0?timer interrupt enable register 0 h'ff14 tpu0 7 ttge 0 r/w 6 ? 1 ? 5 ? 0 ? 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 tgr interrupt enable c 0 interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled 1 tgr interrupt enable d 0 interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1396 of 1484 rej09b0103-0600 tsr0?timer status register 0 h'ff15 tpu0 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register input capture/output compare flag c 0 [clearing conditions] ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register input capture/output compare flag d 0 [clearing conditions] ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1397 of 1484 rej09b0103-0600 tcnt0?timer counter 0 h'ff16 tpu0 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr0a?timer general register 0a h'ff18 tpu0 tgr0b?timer general register 0b h'ff1a tpu0 tgr0c?timer general register 0c h'ff1c tpu0 tgr0d?timer general register 0d h'ff1e tpu0 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1398 of 1484 rej09b0103-0600 tcr1?timer control register 1 h'ff20 tpu1 bit initial value read/write clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 ? time prescaler 0 internal clock: counts on f /1 internal clock: counts on f /4 internal clock: counts on f /16 internal clock: counts on f /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input internal clock: counts on f /256 counts on tcnt2 overflow/underflow 0 1 0 1 0 1 10 1 0 1 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 0 1 0 1 note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 1 is in phase counting mode. 7 ? 0 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 1 is in phase counting mode. internal clock edge selection is valid when the input clock is f /4 or slower. this setting is ignored if the input clock is f /1, or when overflow/underflow of another channel is selected.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1399 of 1484 rej09b0103-0600 tmdr1?timer mode register 1 h'ff21 tpu1 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write * : dont care note: md3 is a reserved bit. in a write, it should always be written with 0. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1400 of 1484 rej09b0103-0600 tior1?timer i/o control register 1 h'ff22 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : dont care tgr1a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of channel 0/tgr0a compare match/ input capture tgr1a is output compare register tgr1a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca1 pin capture input source is tgr0a compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : dont care tgr1b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr0c compare match/input capture tgr1b is output compare register tgr1b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb1 pin capture input source is tgr0c compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1401 of 1484 rej09b0103-0600 tier1?timer interrupt enable register 1 h'ff24 tpu1 7 ttge 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 ? 0 ? 0 tgiea 0 r/w 2 ? 0 ? 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 underflow interrupt enable 0 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1402 of 1484 rej09b0103-0600 tsr1?timer status register 1 h'ff25 tpu1 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 ? 0 ? 0 tgfa 0 r/(w) * 2 ? 0 ? 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) underflow flag 0 [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 tcnt counts down tcnt counts up 1 note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1403 of 1484 rej09b0103-0600 tcnt1?timer counter 1 h'ff26 tpu1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up/down-counter * note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. tgr1a?timer general register 1a h'ff28 tpu1 tgr1b?timer general register 1b h'ff2a tpu1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1404 of 1484 rej09b0103-0600 tcr2?timer control register 2 h'ff30 tpu2 bit initial value read/write clock edge 0 1 count at rising edge count at falling edge count at both edges 0 1 ? time prescaler 0 internal clock: counts on f /1 internal clock: counts on f /4 internal clock: counts on f /16 internal clock: counts on f /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input internal clock: counts on f /1024 0 1 0 1 0 1 10 1 0 1 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 0 1 0 1 note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 2 is in phase counting mode. 7 ? 0 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 2 is in phase counting mode. internal clock edge selection is valid when the input clock is f /4 or slower. this setting is ignored if the input clock is f /1, or when overflow/underflow of another channel is selected.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1405 of 1484 rej09b0103-0600 tmdr2?timer mode register 2 h'ff31 tpu2 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write * : dont care note: md3 is a reserved bit. in a write, it should always be written with 0. mode 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 ? 1 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1406 of 1484 rej09b0103-0600 tior2?timer i/o control register 2 h'ff32 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write * : dont care tgr2a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr2a is output compare register tgr2a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * * : dont care tgr2b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr2b is output compare register tgr2b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 *
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1407 of 1484 rej09b0103-0600 tier2?timer interrupt enable register 2 h'ff34 tpu2 7 ttge 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 ? 0 ? 0 tgiea 0 r/w 2 ? 0 ? 1 tgieb 0 r/w bit initial value read/write tgr interrupt enable a 0 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled 1 tgr interrupt enable b 0 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 1 overflow interrupt enable 0 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled 1 underflow interrupt enable 0 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled 1 a/d conversion start request enable 0 a/d conversion start request generation disabled a/d conversion start request generation enabled 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1408 of 1484 rej09b0103-0600 tsr2?timer status register 2 h'ff35 tpu2 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 ? 0 ? 0 tgfa 0 r/(w) * 2 ? 0 ? 1 tgfb 0 r/(w) * bit initial value read/write input capture/output compare flag a 0 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) underflow flag 0 [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 tcnt counts down tcnt counts up 1 note: * can only be written with 0 for flag clearing.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1409 of 1484 rej09b0103-0600 tcnt2?timer counter 2 h'ff36 tpu2 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up/down-counter * note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. tgr2a?timer general register 2a h'ff38 tpu2 tgr2b?timer general register 2b h'ff3a tpu2 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1410 of 1484 rej09b0103-0600 tcsr0?timer control/status register 0 h'ff74(w), h'ff74(r) wdt0 bit initial value read/write clock select 2 to 0 /2 /64 /128 /512 /2048 /8192 /32768 /131072 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 0 cks2 cks1 cks0 clock overflow period * (where = 20 mhz) 1 0 1 0 1 0 1 0 1 0 1 0 1 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 ? 3 ? 1 ? 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: * an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. note: * for details see section 12.2.3, reset control/status register (rstcsr). note: * when interval timer interrupts are disabled and ovf is polled, read the ovf = 1 state at least twice. timer enable 0 tcnt is initialized to h'00 and halted tcnt counts 1 timer mode select 0 interval timer mode: wdt0 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows watchdog timer mode: a reset is issued when the tcnt overflows if the rste bit of rstcsr is set to 1 * 1 overflow flag 0 [clearing conditions] ? write 0 in the tme bit (only applies to wdt1) ? read tcsr * when ovf = 1, then write 0 in ovf [setting condition] ? when tcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset) 1 notes: tcsr0 register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes on register access. * only 0 can be written, to clear the flag.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1411 of 1484 rej09b0103-0600 tcnt0?timer counter 0 h'ff74(w), h'ff75(r) wdt0 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter note: tcnt0 register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes on register access. rstcsr?reset control/status register h'ff76(w), h'ff77(r) wdt0 bit initial value read/write 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 ? 0 ? 3 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? reset enable 0 reset signal is not generated if tcnt overflows * reset signal is generated if tcnt overflows reset select 0 reset do not set 1 1 watchdog overflow flag 0 [clearing condition] ? cleared by reading rstcsr when wovf = 1, then writing 0 to wovf [setting condition] set when tcnt overflows (changed from h'ff to h'00) during watchdog timer operation 1 notes: rstcsr register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes on register access. * can only be written with 0 for flag clearing. note: * the modules within the h8s/2646 are not reset, but tcnt and tcsr within the wdt are reset.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1412 of 1484 rej09b0103-0600 smr0?serial mode register 0 smr1?serial mode register 1 smr2?serial mode register 2 h'ff78 h'ff80 h'ff88 sci0 sci1 sci2 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 1 and 0 0 clock /4 clock /16 clock /64 clock 0 1 10 1 stop bit length 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. 2 stop bits: 1 multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected parity mode 0 even parity * 3 odd parity * 4 1 parity enable 0 parity bit addition and checking disabled parity bit addition and checking enabled * 2 1 character length 0 8-bit data 7-bit data * 1 1 communication mode 0 asynchronous mode synchronous mode 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1413 of 1484 rej09b0103-0600 notes: 1. when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer. 2. when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. 3. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 4. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1414 of 1484 rej09b0103-0600 iccr0?i 2 c bus control register iccr1?i 2 c bus control register h'ff78 h'ff80 iic0 iic1 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 0 r/w 2 bbsy 0 r/w 1 iric 0 r/(w) * bus busy 0 bus is free [clearing condition] ? when a stop condition is detected 1 bus is free [clearing condition] when a stop condition is detected i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress 1 interrupt requested i 2 c bus interface interrupt enable 0 interrupts disabled 1 interrupts enabled i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins set to port function i 2 c bus interface module internal states initialized sar and sarx can be accessed 1 i 2 c bus interface module enabled for transfer operations (pins scl and sca are driving the bus) icmr and icdr can be accessed acknowledge bit judgement selection 0 the value of the acknowledge bit is ignored, and continuous transfer is performed 1 if the acknowledge bit is 1, continuous transfer is interrupted start condition/stop condition prohibit 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored master/slave select, transmit/receive select 0 0 slave receive mode 1 slave transmit mode 1 0 master receive mode 1 master transmit mode note: * for details see section 15.2.5, i 2 c bus control register. note: * for details see section 15.2.5, i 2 c bus control register. notes: this register is valid only on the h8s/2638, h8s/2639, or h8s/2630 with the i 2 c bus interface option added. * only 0 can be written, for flag clearing. bit initial value r/w : : :
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1415 of 1484 rej09b0103-0600 smr0?serial mode register 0 smr1?serial mode register 1 smr2?serial mode register 2 h'ff78 h'ff80 h'ff88 smart card interface 0 smart card interface 1 smart card interface 2 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 1 and 0 0 clock /4 clock /16 clock /64 clock 0 1 10 1 basic clock pulse 0 32 clock periods 64 clock periods 372 clock periods 256 clock periods 0 1 10 1 parity mode 0 even parity * 2 odd parity * 3 1 parity enable 0 parity bit addition and checking disabled parity bit addition and checking enabled * 1 1 block transfer mode 0 normal smart card interface mode operation ? error signal transmission/detection and automatic data retransmission performed ? txi interrupt generated by tend flag ? tend flag set 12.5 etu after start of transmission (11.0 etu in gsm mode) block transfer mode operation ? error signal transmission/detection and automatic data retransmission not performed ? txi interrupt generated by tdre flag ? tend flag set 11.5 etu after start of transmission (11.0 etu in gsm mode) 1 gsm mode 0 normal smart card interface mode operation ? tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit ? clock output on/off control only gsm mode smart card interface mode operation ? tend flag generation 11.0 etu after beginning of start bit ? high/low fixing control possible in addition to clock output on/off control (set by scr) 1 note: etu: elementary time unit (time for transfer of 1 bit) note: etu: elementary time unit (time for transfer of 1 bit)
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1416 of 1484 rej09b0103-0600 notes: when the smart card interface is used, be sure to make the 1 setting shown for bit 5. 1. when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. 2. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 3. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1417 of 1484 rej09b0103-0600 brr0?bit rate register 0 h'ff79 sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write set the serial transmit/receive bit rate note: for details see section 13.2.8, bit rate register (brr).
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1418 of 1484 rej09b0103-0600 icsr0?i 2 c bus status register icsr1?i 2 c bus status register h'ff79 h'ff81 iic0 iic1 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * notes: this register is valid only on the h8s/2638, h8s/2639, or h8s/2630 with the i 2 c bus interface option added. * only 0 can be written to these bits (to clear these flags). error stop condition detection flag 0 no error stop condition [clearings] (1) when 0 written after reading estp=1; (2) when iric flag is cleared to 0. 1 error stop condition detected in slave mode in i 2 c bus format [setting] on detection of stop condition while sending frame. no meaning when in other than slave mode in i 2 c bus format normal end condition detection flag 0 no normal end condition [clearings] (1) when 0 is written after reading stop=1; (2) when iric flag is cleared to 0. 1 normal end condition detected in slave mode in i 2 c bus format [setting] on detection of stop condition on completion of sending frame. no meaning when in other than slave mode in i 2 c bus format i 2 c bus interface continuous transmit and receive interrupt request flag 0 transmit wait state, or transmitting [clearings] (1) when 0 written after reading irtr=1; (2) when iric flag is cleared to 0. 1 continuous transmit state [settings] in i 2 c bus interface slave mode when 1 is set in tdre or rdrf flag when aasx=1. in other than i 2 c bus interface slave mode when tdre or rdrf flag is set to 1. 2nd slave address confirmation flag 0 2nd slave address not confirmed [clearings] (1) when 0 is written after reading aasx=1; (2) when start conditions are detected; (3) in master mode. 1 2nd slave address confirmed [setting] when 2nd slave address is detected in slave receive mode and fsx = 0. arbitration lost flag 0 secure bus. [clearings] (1) when data is written to icdr (when sending), or when data is read (when receiving); (2) when 0 is written after reading al=1. 1 bus arbitration lost [settings] (1) when there is a mismatch between internal sda and sda pin at rise in scl in master transmit mode; (2) when the internal scl level is high at the fall in scl in master transmit mode. slave address confirmation flag 0 slave address or general call address not confirmed [clearings] (1) when data is written to icdr (when sending), or when data is read from icdr (when receiving); (2) when 0 is written after reading aas=1; (3) in master mode. 1 slave address or general call address confirmed [setting] when slave address or general call address is detected in slave receive mode and fs = 0. general call address confirmation flag 0 general call address not confirmed [clearings] (1) when data is written to icdr (when sending), or when data is read from icdr (when receiving); (2) when 0 is written after reading adz=1; (3) in master mode. 1 general call address confirmation [setting] when general call address is detected is in slave receive mode and fsx = 0 or fs = 0). acknowledge bit 0 when receiving, 0 is output at acknowledge output timing. when transmitting, this bit shows that an acknowledge (0) has not been sent from the receiving device. 1 when receiving, 1 is output at acknowledge output timing. when transmitting, this bit shows that an acknowledge (1) has been sent from the receiving device. bit initial value r/w : : :
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1419 of 1484 rej09b0103-0600 scr0?serial control register 0 scr1?serial control register 1 scr2?serial control register 2 h'ff7a h'ff82 h'ff8a sci0 sci1 sci2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write clock enable 1 and 0 0 asynchronous mode clocked synchronous mode 0 asynchronous mode 1 clocked synchronous mode 1 asynchronous mode 0 clocked synchronous mode asynchronous mode 1 clocked synchronous mode internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output * 9 internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input * 10 external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input * 10 external clock/sck pin functions as serial clock input transmit end interrupt enable 0 transmit-end interrupt (tei) request disabled * 8 1 transmit-end interrupt (tei) request enabled * 8 multiprocessor interrupt enable 0 multiprocessor interrupts disabled (normal reception mode) [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received 1 multiprocessor interrupts enabled * 7 receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received receive enable 0 reception disabled * 5 1 reception enabled * 6 transmit enable 0 transmission disabled * 3 1 transmission enabled * 4 receive interrupt enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 2 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled transmit interrupt enable 0 transmit-data-empty interrupt (txi) request disabled * 1 1 transmit-data-empty interrupt (txi) request enabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1420 of 1484 rej09b0103-0600 notes: 1. txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. 2. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. 3. the tdre flag in ssr is fixed at 1. 4. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. 5. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 6. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1. 7. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 8. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. 9. outputs a clock of the same frequency as the bit rate. 10. inputs a clock with a frequency 16 times the bit rate.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1421 of 1484 rej09b0103-0600 scr0?serial control register 0 scr1?serial control register 1 scr2?serial control register 2 h'ff7a h'ff82 h'ff8a smart card interface 0 smart card interface 1 smart card interface 2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write clock enable 1 and 0 scmr smif cke1 cke0 scr setting sck pin function smr c/ a , gm operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin 0 1 see the sci 0 1 0 1 0 1 0 1 1 0 transmit end interrupt enable 0 transmit-end interrupt (tei) request disabled * 8 1 transmit-end interrupt (tei) request enabled * 8 multiprocessor interrupt enable 0 multiprocessor interrupts disabled (normal reception mode) [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received 1 multiprocessor interrupts enabled * 7 receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received receive enable 0 reception disabled * 5 1 reception enabled * 6 transmit enable 0 transmission disabled * 3 1 transmission enabled * 4 receive interrupt enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 2 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled transmit interrupt enable 0 transmit-data-empty interrupt (txi) request disabled * 1 1 transmit-data-empty interrupt (txi) request enabled
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1422 of 1484 rej09b0103-0600 notes: 1. txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. 2. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. 3. the tdre flag in ssr is fixed at 1. 4. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. 5. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 6. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1. 7. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 8. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. tdr0?transmit data register 0 h'ff7b sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write store serial transmit data
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1423 of 1484 rej09b0103-0600 ssr0?serial status register 0 ssr1?serial status register 1 ssr2?serial status register 2 h'ff7c h'ff84 h'ff8c sci0 sci1 sci2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write multiprocessor bit transfer 0 data with a 0 multi-processor bit is transmitted 1 data with a 1 multi-processor bit is transmitted note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. multiprocessor bit 0 [clearing condition] when data with a 0 multiprocessor bit is received * 7 1 [setting condition] when data with a 1 multiprocessor bit is received transmit end 0 [clearing conditions] when 0 is written in tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 [clearing condition] when 0 is written in per after reading per = 1 * 5 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 6 framing error 0 [clearing condition] when 0 is written in fer after reading fer = 1 * 3 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 4 overrun error 0 [clearing condition] when 0 is written in orer after reading orer = 1 * 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 * 2 receive data register full 0 [clearing conditions] when 0 is written in rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 [clearing conditions] when 0 is written in tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written in tdr
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1424 of 1484 rej09b0103-0600 notes: * only 0 can be written, to clear the flag. 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 3. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 5. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 6. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 7. retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1425 of 1484 rej09b0103-0600 ssr0?serial status register 0 ssr1?serial status register 1 ssr2?serial status register 2 h'ff7c h'ff84 h'ff8c smart card interface 0 smart card interface 1 smart card interface 2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write multiprocessor bit transfer 0 data with a 0 multi-processor bit is transmitted 1 data with a 1 multi-processor bit is transmitted multiprocessor bit 0 [clearing condition] when data with a 0 multiprocessor bit is received * 5 1 [setting condition] when data with a 1 multiprocessor bit is received parity error 0 [clearing condition] when 0 is written in per after reading per = 1 * 3 1 overrun error 0 [clearing condition] when 0 is written in orer after reading orer = 1 * 1 1 receive data register full 0 [clearing conditions] when 0 is written in rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr 1 transmit data register empty note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. 0 [clearing conditions] when 0 is written in tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written in tdr note: etu: elementary time unit (time for transfer of 1 bit) transmit end 0 transmission is in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr 1 transmission has ended [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. error signal status 0 normal reception, with no error signal [clearing conditions] upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 1 error signal sent from receiver indicating detection of parity error [setting condition] when the low level of the error signal is sampled [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit * 4 does not match the parity setting (even or odd) specified by the o/ e bit in smr [setting condition] when the next serial reception is completed while rdrf = 1 * 2 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1426 of 1484 rej09b0103-0600 notes: * only 0 can be written, to clear the flag. 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 3. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 5. retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. rdr0?receive data register 0 h'ff7d sci0, smart card interface 0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write store serial receive data
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1427 of 1484 rej09b0103-0600 scmr0?smart card mode register 0 h'ff7e sci0, smart card interface 0 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write smart card interface mode select 0 operates as normal sci (smart card interface function disabled) 1 smart card interface function enabled smart card interface data invert 0 tdr contents are transmitted without modification receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form smart card interface data transfer direction 0 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1428 of 1484 rej09b0103-0600 icdr0?i 2 c bus data register icdr1?i 2 c bus data register h'ff7e h'ff86 iic0 iic1 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r icdrr icdrs icdrt tdre, rdrf (internal flag) 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrs5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w ? rdrf 0 ? ? tdre 0 ? bit initial value r/w : : : bit initial value r/w : : : bit initial value r/w : : : bit initial value r/w : : : bit initial value r/w : : : note: this register is valid only on the h8s/2638, h8s/2639, or h8s/2630 with the i 2 c bus interface option added.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1429 of 1484 rej09b0103-0600 sarx0?2nd slave address register sarx1?2nd slave address register h'ff7e h'ff86 iic0 iic1 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w 2nd slave address format select x bit initial value r/w : : : note: this register is valid only on the h8s/2638, h8s/2639, or h8s/2630 with the i 2 c bus interface option added.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1430 of 1484 rej09b0103-0600 icmr0?i 2 c bus mode register icmr1?i 2 c bus mode register h'ff7f h'ff87 iic0 iic1 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w msb-first/lsb-first select 0 msb first 1 lsb first wait insert bit 0 send data followed by acknowledge bit. 1 insert wait between data and acknowledge bit. transmit clock select scrx bit 5 bit 4 bit 3 clock transfer rate bit 5, 6 iicx cks2 cks1 cks0 = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 0 0 0 /28 179khz 286 khz 357 khz 571 khz * 714 khz * 1 /40 125khz 200 khz 250 khz 400 khz 500 khz * 1 0 /48 104khz 167 khz 208 khz 333 khz 417 khz * 1 /64 78.1khz 125 khz 156 khz 250 khz 313 khz 1 0 0 /80 62.5khz 100 khz 125 khz 200 khz 250 khz 1 /100 50.0khz 80.0 khz 100 khz 160 khz 200 khz 1 0 /112 44.6khz 71.4 khz 89.3 khz 143 khz 179 khz 1 /128 39.1khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 0 /56 89.3khz 143 khz 179 khz 286 khz 357 khz 1 /80 62.5khz 100 khz 125 khz 200 khz 250 khz 1 0 /96 52.1khz 83.3 khz 104 khz 167 khz 208 khz 1 /128 39.1khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 /160 31.3khz 50.0 khz 62.5 khz 100 khz 125 khz 1 /200 25.0khz 40.0 khz 50.0 khz 80.0 khz 100 khz 1 0 /224 22.3khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 /256 19.5khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz bit counter bit 2 bit 1 bit 0 bit/frame bc2 bc1 bc0 clock sync pc bus format serial format 0 0 0 8 9 1 1 2 1 0 2 3 1 3 4 1 0 0 4 5 1 5 6 1 0 6 7 1 7 8 bit initial value r/w : : : note: * these rates are outside the ranges stipulated in the i 2 c bus interface specifications (normal mode: max. 100 khz, high-speed mode: max. 400 khz). note: this register is valid only on the h8s/2638, h8s/2639, or h8s/2630 with the i 2 c bus interface option added.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1431 of 1484 rej09b0103-0600 sar0?slave address register sar1?slave address register h'ff7f h'ff87 iic0 iic1 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w slave address format select ddcswr sar sarx bit 6 bit 0 bit 0 operating mode sw fs fsx 00 0i 2 c bus format sar and sarx slave addresses recognized 1i 2 c bus format (initial value) sar slave address recognized sarx slave address ignored 10i 2 c bus format sar slave address ignored sarx slave address recognized 1 synchronous serial format sar and sarx slave addresses ignored 1 ?? must not be set. bit initial value r/w : : :
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1432 of 1484 rej09b0103-0600 brr1?bit rate register 1 h'ff81 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write set the serial transmit/receive bit rate note: for details see section 13.2.8, bit rate register (brr). tdr1?transmit data register 1 h'ff83 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write store serial transmit data rdr1?receive data register 1 h'ff85 sci1, smart card interface 1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write store serial receive data
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1433 of 1484 rej09b0103-0600 scmr1?smart card mode register 1 h'ff86 sci1, smart card interface 1 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write smart card interface mode select 0 operates as normal sci (smart card interface function disabled) 1 smart card interface function enabled smart card interface data invert 0 tdr contents are transmitted without modification receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form smart card data interface transfer direction 0 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first brr2?bit rate register 2 h'ff89 sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write set the serial transmit/receive bit rate note: for details see section 13.2.8, bit rate register (brr).
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1434 of 1484 rej09b0103-0600 tdr2?transmit data register 2 h'ff8b sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write store serial transmit data rdr2?receive data register 2 h'ff8d sci2, smart card interface 2 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write store serial receive data
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1435 of 1484 rej09b0103-0600 scmr2?smart card mode register 2 h'ff8e sci2, smart card interface 2 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write smart card interface mode select 0 operates as normal sci (smart card interface function disabled) 1 smart card interface function enabled smart card interface data invert 0 tdr contents are transmitted without modification receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form smart card interface data transfer direction 0 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first addra?a/d data register a h'ff90 a/d converter addrb?a/d data register b h'ff92 a/d converter addrc?a/d data register c h'ff94 a/d converter addrd?a/d data register d h'ff96 a/d converter 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 8 ad2 0 r 10 ad4 0 r 9 ad3 0 r bit initial value read/write 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 ? 0 r 2 ? 0 r 1 ? 0 r
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1436 of 1484 rej09b0103-0600 adcsr?a/d control/status register h'ff98 a/d converter 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * bit initial value read/write note: * only 0 can be written, to clear the flag. scan mode 0 single mode 1 scan mode a/d interrupt enable 0 a/d conversion end interrupt (adi) request disabled 1 a/d conversion end interrupt (adi) request enabled a/d end flag 0 [clearing conditions] ? when 0 is written in the to adf flag after reading adf = 1 ? when the dtc is activated by an adi interrupt, and addr is read 1 [setting conditions] ? single mode: when a/d conversion ends ? scan mode: when a/d conversion ends on all specified channels a/d start 0 a/d conversion stopped 1 ? single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends ? scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode channel select 2 to 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 setting prohibited setting prohibited setting prohibited setting prohibited an0 an0, an1 an0 to an2 an0 to an3 an4 an4, an5 an4 to an6 an4 to an7 an8 an8, an9 an8 to an10 an8 to an11 setting prohibited setting prohibited setting prohibited setting prohibited ch1 ch0 single mode (scan = 0) scan mode (scan = 1) ch3 0 1 ch2 0 1 0 1 channel select 3 0 an8 to an11 are group 0 analog input pins 1 an0 to an3 are group 0 analog input pins, an4 to an7 are group 1 analog input pins
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1437 of 1484 rej09b0103-0600 adcr?a/d control register h'ff99 a/d converter 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 ? 4 ? 1 ? 3 cks1 0 r/w 0 ? 1 ? 2 cks0 0 r/w 1 ? 1 ? bit initial value read/write timer trigger select 0 a/d conversion start by software is enabled a/d conversion start by tpu conversion start trigger is enabled setting prohibited a/d conversion start by external trigger pin ( adtrg ) is enabled 0 1 10 1 clock select 0 conversion time = 530 states (max.) conversion time = 266 states (max.) conversion time = 134 states (max.) conversion time = 68 states (max.) 0 1 10 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1438 of 1484 rej09b0103-0600 tcsr1?timer control/status register 1 h'ffa2(w), h'ffa2(r) wdt1 bit initial value read/write 7 ovf 0 r/(w) * 1 6 wt/ it 0 r/w 5 tme 0 r/w 4 pss * 2 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w timer enable 0 tcnt is initialized to h'00 and halted tcnt counts 1 overflow flag 0 1 timer mode select 0 interval timer mode: wdt1 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows watchdog timer mode: wdt1 requests a reset or an nmi interrupt from the cpu when the tcnt overflows 1 prescaler select 0 the tcnt counts frequency-division clock pulses of the based prescaler (psm) the tcnt counts frequency-division clock pulses of the sub * -based prescaler (pss) 1 reset or nmi 0 nmi request internal reset request 1 clock select 2 to 0 /2 /64 /128 /512 /2048 /8192 /32768 /131072 sub/2 * 2 sub/4 * 2 sub/8 * 2 sub/16 * 2 sub/32 * 2 sub/64 * 2 sub/128 * 2 sub/256 * 2 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 15.6 ms 31.3 ms 62.5 ms 125 ms 250 ms 500 ms 1 s 2 s 0 cks2 0 pss cks1 cks0 clock overflow period * 1 (where = 20 mhz) (where sub * 2 = 32.768 khz) 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 01 1 0 1 0 1 0 1 0 1 1 0 1 note: * subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only. these functions cannot be used with the other versions, and in them the pss bit is reserved. only 0 should be written to this bit. [clearing conditions] ? write 0 in the tme bit (only applies to wdt1) ? read tcsr * when ovf = 1, then write 0 in ovf [setting condition] ? when tcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset ) notes: 1. an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only, but are not available in the other versions. notes: tcsr1 register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes o n register access. 1. only 0 can be written, to clear the flag. 2. subclock functions (subactive mode, subsleep mode, and watch mode) are available in the u-mask, w-mask versions, and h8s/2635 group only. note: * when interval timer interrupts are disabled and ovf is polled, read the ovf = 1 state at least twice.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1439 of 1484 rej09b0103-0600 tcnt1?timer counter 1 h'ffa2(w), h'ffa3(r) wdt1 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter note: tcnt1 register differs from other registers in being more difficult to write to. for details see section 12.2.4, notes on register access. dadr0? d/a data register 0 dadr1? d/a data register 1 h'ffa4 h'ffa5 d/a0, 1 d/a0, 1 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write store data to be converted note: these registers are not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1440 of 1484 rej09b0103-0600 dacr01? d/a control register 01 h'ffa6 d/a0, 1 bit initial value read/write d/a enable disabled on channels 0 and 1 enabled on channel 0 disabled on channel 1 enabled on channels 0 and 1 disabled on channel 0enabled on channel 1 enabled on channels 0 and 1 enabled on channels 0 and 1 0 1 0 1 0 1 * 0 1 0 1 * 7 daoe1 0 r/(w) * 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? d/a output enable 1 0 analog output da1 is disabled d/a conversion is enabled on channel 1. analog output da1 is enabled 1 d/a output enable 0 0 analog output da0 is disabled d/a conversion is enabled on channel 0. analog output da0 is enabled 1 * : don?t care note: this register is not available in the h8s/2635 and h8s/2634.
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1441 of 1484 rej09b0103-0600 flmcr1?flash memory control register 1 h'ffa8 flash memory 7 fwe ? * r 6 swe 0 r/w 5 esu 0 r/w 4 psu 0 r/w 3 ev 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w bit initial value read/write program 0 program mode cleared 1 transition to program mode [setting condition] ? when fwe = 1, swe = 1, and psu = 1 erase 0 erase mode cleared 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 program-verify 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 erase-verify 0 erase-verify mode cleared 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 note: * determined by the state of the fwe pin. program setup 0 program setup cleared program setup [setting condition] when fwe = 1 and swe = 1 1 erase setup 0 erase setup cleared erase setup [setting condition] when fwe = 1 and swe = 1 1 software write enable bit 0 writes disabled writes enabled [setting condition] when fwe = 1 1 flash write enable bit 0 when a low level is input to the fwe pin (hardware-protected state) when a high level is input to the fwe pin 1
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1442 of 1484 rej09b0103-0600 flmcr2?flash memory control register 2 h'ffa9 flash memory 7 fler 0 r 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit initial value read/write flash memory error 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] power-on reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 21a.10.3, 21b.10.3, error protection
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1443 of 1484 rej09b0103-0600 ebr1?erase block register 1 h'ffaa flash memory ebr2?erase block register 2 h'ffab flash memory 15 eb7 0 r/w 14 eb6 0 r/w 13 eb5 0 r/w 12 eb4 0 r/w 11 eb3 0 r/w 8 eb0 0 r/w 10 eb2 0 r/w 9 eb1 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 eb13 * 3 0 r/w 4 eb12 * 3 0 r/w 3 eb11 * 2 0 r/w 0 eb8 0 r/w 2 eb10 * 1 0 r/w 1 eb9 0 r/w bit initial value read/write ebr1 bit initial value read/write notes: 1. on the h8s/2636, these bits are reserved. 2. reserved in the h8s/2636 and h8s/2635. 3. reserved in the h8s/2638, h8s/2639, and h8s/2635. ebr2 specify the flash memory erase area block (size) ? h8s/2636 ? h8s/2638, h8s/2639 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) eb11 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff h'030000 to h'03ffff block (size) ? h8s/2635 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff block (size) ? h8s/2630 addresses eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes) eb8 (32 kbytes) eb9 (64 kbytes) eb10 (64 kbytes) eb11 (64 kbytes) eb12 (64 kbytes) eb13 (64 kbytes) h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff h'008000 to h'00ffff h'010000 to h'01ffff h'020000 to h'02ffff h'030000 to h'03ffff h'040000 to h'04ffff h'050000 to h'05ffff block (size) addresses eb0 (1 kbyte) eb1 (1 kbyte) eb2 (1 kbyte) eb3 (1 kbyte) eb4 (28 kbytes) eb5 (16 kbytes) eb6 (8 kbytes) eb7 (8 kbytes) eb8 (32 kbytes) eb9 (32 kbytes) h'000000 to h'0003ff h'000400 to h'0007ff h'000800 to h'000bff h'000c00 to h'000fff h'001000 to h'007fff h'008000 to h'00bfff h'00c000 to h'00dfff h'00e000 to h'00ffff h'010000 to h'017fff h'018000 to h'01ffff
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1444 of 1484 rej09b0103-0600 flpwcr?flash memory power control register h'ffac flash memory 7 pdwnd 0 r/w 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 ? 0 r 2 ? 0 r 1 ? 0 r bit initial value read/write power-down disable 0 transition to flash memory power-down mode enabled 1 transition to flash memory power-down mode disabled port1?port 1 register h'ffb0 port 7 p17 ? * r 6 p16 ? * r 5 p15 ? * r 4 p14 ? * r 3 p13 ? * r 0 p10 ? * r 2 p12 ? * r 1 p11 ? * r bit initial value read/write note: * determined by state of pins p17 to p10. state of the port 1 pins port3?port 3 register h'ffb2 port 7 ? undefined ? 6 ? undefined ? 5 p35 ? * r 4 p34 ? * r 3 p33 ? * r 0 p30 ? * r 2 p32 ? * r 1 p31 ? * r bit initial value read/write note: * determined by state of pins p35 to p30. state of the port 3 pins
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1445 of 1484 rej09b0103-0600 port4?port 4 register h'ffb3 port 7 p47 ? * r 6 p46 ? * r 5 p45 ? * r 4 p44 ? * r 3 p43 ? * r 0 p40 ? * r 2 p42 ? * r 1 p41 ? * r bit initial value read/write note: * determined by state of pins p47 to p40. state of the port 4 pins port9?port 9 register h'ffb8 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 p93 ? * r 0 p90 ? * r 2 p92 ? * r 1 p91 ? * r bit initial value read/write note: * determined by state of pins p93 to p90. state of the port 9 pins porta?port a register h'ffb9 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3 ? * r 0 pa0 ? * r 2 pa2 ? * r 1 pa1 ? * r bit initial value read/write note: * determined by state of pins pa3 to pa0. state of the port a pins
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1446 of 1484 rej09b0103-0600 portb?port b register h'ffba port 7 pb7 ? * r 6 pb6 ? * r 5 pb5 ? * r 4 pb4 ? * r 3 pb3 ? * r 0 pb0 ? * r 2 pb2 ? * r 1 pb1 ? * r bit initial value read/write note: * determined by state of pins pb7 to pb0. state of the port b pins portc?port c register h'ffbb port 7 pc7 ? * r 6 pc6 ? * r 5 pc5 ? * r 4 pc4 ? * r 3 pc3 ? * r 0 pc0 ? * r 2 pc2 ? * r 1 pc1 ? * r bit initial value read/write note: * determined by state of pins pc7 to pc0. state of the port c pins portd?port d register h'ffbc port 7 pd7 ? * r 6 pd6 ? * r 5 pd5 ? * r 4 pd4 ? * r 3 pd3 ? * r 0 pd0 ? * r 2 pd2 ? * r 1 pd1 ? * r bit initial value read/write note: * determined by state of pins pd7 to pd0. state of the port d pins
appendix b internal i/o register rev. 6.00 feb 22, 2005 page 1447 of 1484 rej09b0103-0600 porte?port e register h'ffbd port 7 pe7 ? * r 6 pe6 ? * r 5 pe5 ? * r 4 pe4 ? * r 3 pe3 ? * r 0 pe0 ? * r 2 pe2 ? * r 1 pe1 ? * r bit initial value read/write note: * determined by state of pins pe7 to pe0. state of the port e pins portf?port f register h'ffbe port 7 pf7 ? * r 6 pf6 ? * r 5 pf5 ? * r 4 pf4 ? * r 3 pf3 ? * r 0 pf0 ? * r 2 ? undefined ? 1 ? undefined ? bit initial value read/write note: * determined by state of pins pf7 to pf3, pf0. state of the port f pins
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1448 of 1484 rej09b0103-0600 appendix c i/o port block diagrams c.1 port 1 block diagrams r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr c qd p1n * 1 rdr1 rpor1 ppg module * 2 system controller from internal address bus tpu module pulse output enable pulse output address output enable output compare output/pwm output enable output compare output/ pwm output input capture input wddr1: wdr1: rdr1: rpor1: n = 0 or 1 notes: 1. 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. write to p1ddr write to p1dr read p1dr read port 1 legend: priority order: address output > output compare output > pwm output pulse output > dr output figure c-1 (a) port 1 block diagram (pins p10 and p11)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1449 of 1484 rej09b0103-0600 r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 ppg module * 2 tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output external clock input input capture input legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 n = 2 or 3 notes: 1. priority order: address output > output compare output/pwm output > pulse output > dr output 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. internal data bus internal address bus system controller address output enable * 1 figure c-1 (b) port 1 block diagram (pins p12 and p13)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1450 of 1484 rej09b0103-0600 r p14ddr c qd reset wddr1 reset wdr1 r p14dr c qd p14 rdr1 rpor1 ppg module * 2 tpu module pulse output enable interrupt controller irq0 interrupt input output compare output / pwm output enable output compare output / pwm output pulse output input capture input legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 notes: 1. priority order: output compare output/pwm output > pulse output > dr output 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. internal data bus * 1 figure c-1 (c) port 1 block diagram (pin p14)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1451 of 1484 rej09b0103-0600 r p15ddr c qd reset wddr1 reset wdr1 r p15dr c qd p15 rdr1 rpor1 ppg module * 2 tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output input capture input external clock input legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 notes: 1. priority order: output compare output/pwm output > pulse output > dr output 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. internal data bus * 1 figure c-1 (d) port 1 block diagram (pin p15)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1452 of 1484 rej09b0103-0600 r p16ddr c qd reset wddr1 reset internal data bus wdr1 r p16dr c qd p16 rdr1 rpor1 ppg module * 2 tpu module pulse output enable output compare output/pwm output enable output compare output/ pwm output pulse output input capture input input controller irq1 interrupt input legend: wddr1: wdr1: rdr1: rpor1: write to p1ddr write to p1dr read p1dr read port 1 notes: 1. priority order: output compare output/pwm output > pulse output > dr output 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. * 1 figure c-1 (e) port 1 block diagram (pin p16)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1453 of 1484 rej09b0103-0600 r p17ddr c qd reset wddr1 reset internal data bus wdr1 r p17dr c qd p17 rdr1 rpor1 ppg module * 2 tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output input capture input external clock input legend: wddr1: wdr1: rdr1: rpor1: write to p1ddr write to p1dr read p1dr read port 1 notes: 1. priority order: output compare output/pwm output > pulse output > dr output 2. the ppg module is not implemented in the h8s/2635 and h8s/2634. * 1 figure c-1 (f) port 1 block diagram (pin p17)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1454 of 1484 rej09b0103-0600 c.2 port 3 block diagrams r p30ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p30 rdr3 rodr3 rpor3 txd0 sci module serial transmit enable serial transmit data notes: 1. output enable signal 2. open drain control signal p30dr reset wodr3 r c qd p30odr * 1 * 2 legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c-2 (a) port 3 block diagram (pin p30)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1455 of 1484 rej09b0103-0600 r p31ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p31 rdr3 rodr3 rpor3 sci module serial receive data enable serial receive data rxd0 p31dr reset wodr3 r c qd p31odr * 1 * 2 notes: 1. output enable signal 2. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c-2 (b) port 3 block diagram (pin p31)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1456 of 1484 rej09b0103-0600 r p32ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p32 rdr3 rodr3 rpor3 sci module serial clock output enable serial clock input enable serial clock output iic1 module sda1 output iic1 output enable sda1 input interrupt controller irq4 interrupt input p32dr reset wodr3 r c qd p32odr * 2 * 3 * 4 * 1 serial clock input notes: 1. priority order: iic output > serial clock output > dr output 2. output enable signal 3. open drain control signal 4. the iic1 module is available as an option in the h8s/2638, h8s/2639, h8s/2630. legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c-2 (c) port 3 block diagram (pin p32)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1457 of 1484 rej09b0103-0600 r p33ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p33 rdr3 rodr3 rpor3 sci module serial transmit enable serial transmit data p33dr reset wodr3 r c qd p33odr * 1 * 2 * 3 txd1 iic1 module scl1 output iic1 output enable scl1 input notes: 1. output enable signal 2. open drain control signal 3. the iic1 module is available as an option in the h8s/2638, h8s/2639, h8s/2630. legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c-2 (d) port 3 block diagram (pin p33)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1458 of 1484 rej09b0103-0600 r p34ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p34 rdr3 rodr3 rpor3 sci module iic0 module sda0 output sda0 input iic0 output enable serial receive data enable serial receive data rxd1 p34dr reset wodr3 r c qd p34odr * 1 * 2 * 4 * 3 notes: 1. output enable signal 2. open drain control signal 3. priority order: iic output > dr output 4. the iic0 module is available as an option in the h8s/2638, h8s/2639, h8s/2630. legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c-2 (e) port 3 block diagram (pin p34)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1459 of 1484 rej09b0103-0600 r p35ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p35 rdr3 rodr3 rpor3 sci module iic0 module scl0 output scl0 input iic0 output enable irq5 interrupt input interrupt controller serial clock output enable serial clock output serial clock input enable p35dr reset wodr3 r c qd p35odr * 2 * 3 * 1 serial clock input notes: 1. priority order: iic output > serial clock output > dr output 2. output enable signal 3. open drain control signal 4. the iic0 module is available as an option in the h8s/2638, h8s/2639, h8s/2630. legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr * 4 figure c-2 (f) port 3 block diagram (pin p35)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1460 of 1484 rej09b0103-0600 c.3 port 4 block diagram p4n rpor4 internal data bus a/d converter module analog input legend: rpor4: read port 4 n = 0 to 5 figure c-3 (a) port 4 block diagram (pins p40 to p45) p4n rpor4 internal data bus a/d converter module analog input output enable d/a converter module * analog output legend: rpor4: read port 4 notes: * the d/a converter is not implemented in the h8s/2635 and h8s/2634. n = 6, 7 figure c-3 (b) port 4 block diagram (pins p46, p47)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1461 of 1484 rej09b0103-0600 c.4 port 9 block diagram p9n rpor9 internal data bus a/d converter module analog input legend: rpor9: read port 9 n = 0 to 3 figure c-4 port 9 block diagram (pins p90 to p93)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1462 of 1484 rej09b0103-0600 c.5 port a block diagram r pa0pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa0 rdra rodra rpora pa0dr reset wddra r c qd pa0ddr reset wodra rpcra r c qd pa0odr * 1 * 2 modes 4/5/6 address enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: write to paddr write to padr write to paodr write to papcr read padr read port a read paodr read papcr legend: figure c-5 (a) port a block diagram (pin pa0)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1463 of 1484 rej09b0103-0600 r pa1pcr c qd reset internal address bus internal data bus wpcra reset wdra r c qd pa1 rdra rodra rpora pa1dr reset smart card mode signal txd output txd output enable wddra r c qd pa1ddr reset wodra rpcra r c qd pa1odr * 1 * 2 modes 4/5/6 address enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: write to paddr write to padr write to paodr write to papcr read padr read port a read paodr read papcr legend: figure c-5 (b) port a block diagram (pin pa1)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1464 of 1484 rej09b0103-0600 r pa2pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa2 rdra rodra rpora pa2dr reset rxd input enable rxd input wddra r c qd pa2ddr reset wodra rpcra r c qd pa2odr * 1 * 2 modes 4/5/6 address enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: write to paddr write to padr write to paodr write to papcr read padr read port a read paodr read papcr legend: figure c-5 (c) port a block diagram (pin pa2)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1465 of 1484 rej09b0103-0600 r pa3pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa 3 rdra rodra rpora pa3dr reset sck input enable sck output sck input sck output enable wddra r c qd pa3ddr reset wodra rpcra r c qd pa3odr * 1 * 2 modes 4/5/6 address enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: write to paddr write to padr write to paodr write to papcr read padr read port a read paodr read papcr legend: figure c-5 (d) port a block diagram (pin pa3)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1466 of 1484 rej09b0103-0600 c.6 port b block diagram r pbnpcr c qd reset internal address bus internal data bus wpcrb reset wdrb r c qd pbn rdrb rodrb rporb pbndr reset wddrb r c qd pbnddr reset wodrb rpcrb r c qd pbnodr * 1 * 2 modes 4/5/6 (output compare) tpu output tpu output enable tpu input (input capture) address enable notes: 1. output enable signal 2. open drain control signal wddrb: wdrb: wodrb: wpcrb: rdrb: rporb: rodrb: rpcrb: n = 0 to 7 write to pbddr write to pbdr write to pbodr write to pbpcr read pbdr read port b read pbodr read pbpcr legend: figure c-6 port b block diagram (pins pb0 to pb7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1467 of 1484 rej09b0103-0600 c.7 port c block diagram r pcnpcr c qd reset internal address bus internal data bus wpcrc reset wdra r c qd pcn rdrc rodrc rporc pcndr reset wddra r c qd pcnddr reset wodrc rpcrc r c qd pcnodr * 1 * 2 modes 4/5 mode 6 notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: n = 0 to 7 write to pcddr write to pcdr write to pcodr write to pcpcr read pcdr read port a read pcodr read pcpcr legend: figure c-7 port c block diagram (pins pc0 to pc7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1468 of 1484 rej09b0103-0600 c.8 port d block diagram r pdnpcr c qd reset internal upper data bus wpcrd reset wdrd external address upper write r c qd pdn rdrd rpord pdndr wddrd c qd pdnddr rpcrd mode 7 modes 4/5/6 external address write reset r external address upper read wddrd: wdrd: wpcrd: rdrd: rpord: rpcrd: n = 0 to 7 write to pdddr write to pddr write to pdpcr read pddr read port d read pdpcr legend: figure c-8 port d block diagram (pins pd0 to pd7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1469 of 1484 rej09b0103-0600 c.9 port e block diagram r penpcr c qd reset internal upper data bus internal lower data bus wpcre reset wdre r c qd pen rdre rpore pendr wddre c qd penddr rpcre mode 7 modes 4/5/6 external address write reset r external addres lower read wddre: wdre: wpcre: rdre: rpore: rpcre: n = 0 to 7 write to peddr write to pedr write to pepcr read pedr read port e read pepcr legend: figure c-9 port e block diagram (pins pe0 to pe7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1470 of 1484 rej09b0103-0600 c.10 port f block diagrams r pf0ddr c qd reset internal data bus wddrf reset wdrf r c qd pf0 rdrf rporf irq interrupt input pf0dr wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (a) port f block diagram (pin pf0)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1471 of 1484 rej09b0103-0600 r pf3ddr c qd reset internal data bus wddrf reset wdrf r pf3dr c qd pf3 rdrf rporf bus controller adtrg input irq3 interrupt input lwr output modes 4/5/6 wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (b) port f block diagram (pin pf3)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1472 of 1484 rej09b0103-0600 r pf4ddr c qd reset internal data bus modes 4/5/6 wddrf reset wdrf r pf4dr c qd pf4 rdrf rporf bus controlle r hwr output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (c) port f block diagram (pin pf4)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1473 of 1484 rej09b0103-0600 r pf5ddr c qd reset internal data bus wddrf reset modes 4/5/6 wdrf r pf5dr c qd pf5 rdrf rporf bus controlle r rd output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (d) port f block diagram (pin pf5)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1474 of 1484 rej09b0103-0600 r pf6ddr c qd reset internal data bus wddrf reset modes 4/5/6 wdrf r pf6dr c qd pf6 rdrf rporf bus controlle r as output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (e) port f block diagram (pin pf6)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1475 of 1484 rej09b0103-0600 d wddrf reset wdrf r pf7dr c qd pf7 rdrf rporf reset internal data bus r modes 4/5/6 s c qd pf7ddr note: * set priority * wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c-10 (f) port f block diagram (pin pf7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1476 of 1484 rej09b0103-0600 c.11 port h block diagram r phnddr c qd reset internal data bus wddrh reset wdrh r c qd phn rdrh rporh pwm module pwm output enable pwm output phndr wddrh: wdrh: rdrh: rporh: n = 0 to 7 write to phddr write to phdr read phdr read port h legend: figure c-11 port h block diagram (pins ph0 to ph7)
appendix c i/o port block diagrams rev. 6.00 feb 22, 2005 page 1477 of 1484 rej09b0103-0600 c.12 port j block diagram r pjnddr c qd reset wddrj reset wdrj r c qd pjn rdrj rporj pjndr internal data bus pwm module pwm output enable pwm output wddrj: wdrj: rdrj: rporj: n = 0 to 7 write to pjddr write to pjdr read pjdr read port j legend: figure c-12 port j block diagram (pins pj0 to pj7)
appendix d pin states rev. 6.00 feb 22, 2005 page 1478 of 1484 rej09b0103-0600 appendix d pin states d.1 port states in each mode table d-1 i/o port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode port 1 4, 5 t t p10 to p13 p10 to p13 6 [address output, ope = 0] t [address output, ope = 1] kept [otherwise] kept p14 to p17 kept [address output] a20 to a23 [otherwise] i/o port p14 to p17 i/o port 7 kept p10 to p17 i/o port port 3 4 to 7 t t kept i/o port port 4 4 to 7 t t t input port port 9 4 to 7 t t t input port port a 4, 5 6 l t t t [address output, ope = 0] t [address output, ope = 1] kept [otherwise] kept [address output] a19 to a17 [otherwise] i/o port 7 t t kept i/o port port b 4, 5 6 l t t t [address output, ope = 0] t [address output, ope = 1] kept [otherwise] kept [address output] a15 to a8 [otherwise] i/o port 7 t t kept i/o port
appendix d pin states rev. 6.00 feb 22, 2005 page 1479 of 1484 rej09b0103-0600 port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode port c 4, 5 l t [ope = 0] t [ope = 1] kept a7 to a0 6 t t [ddr = 1, ope = 0] t [ddr = 1, ope = 1] kept [ddr = 0] kept [ddr = 1] a7 to a0 [ddr = 0] i/o port 7 t t kept i/o port port d 4 to 6 t t t data bus 7 t t kept i/o port port e 4 to 6 8 bit bus t t kept i/o port 16 bit bus t t t data bus 7 t t kept i/o port pf7/ 4 to 6 clock output t [ddr = 0] t [ddr = 1] h [ddr = 0] t [ddr = 1] clock output 7 t t [ddr = 0] t [ddr = 1] h [ddr = 0] t [ddr = 1] clock output pf6/ as 4 to 6 h t [ope = 0] t [ope = 1] h as 7 t t kept i/o port pf5/ rd pf4/ hwr 4 to 6 h t [ope = 0] t [ope = 1] h rd, hwr 7 t t kept i/o port
appendix d pin states rev. 6.00 feb 22, 2005 page 1480 of 1484 rej09b0103-0600 port name pin name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode pf3/ lwr 4 to 6 h t [ope = 0] t [ope = 1] h lwr 7 t t kept i/o port pf0 4 to 7 t t kept i/o port port h 4 to 7 t t kept i/o port port j 4 to 7 t t kept i/o port htxd0, htxd1 4 to 7 h t h tx output hrxd0, hrxd1 4 to 7 input t t rx output legend: h: high level l: low level t: high impedance kept: input port becomes high-impedance, output port retains state ddr: data direction register ope: output port enable
appendix e timing of transition to and recovery from hardware standby mode rev. 6.00 feb 22, 2005 page 1481 of 1484 rej09b0103-0600 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low at least 10 states before the stby signal goes low, as shown below. res must remain low until stby signal goes low (delay from stby low to res high: 0 ns or more). stby res t 2 0 ns t 1 10 t cyc figure e-1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode drive the res signal low and the nmi signal high approximately 100 ns or more before stby goes high to execute a reset. t osc t nmirh t 100 ns nmi stby res figure e-2 timing of recovery from hardware standby mode
appendix f product code lineup rev. 6.00 feb 22, 2005 page 1482 of 1484 rej09b0103-0600 appendix f product code lineup table f-1 h8s/2636, h8s/2638, h8s/2639, and h8s/2630 product code lineup product type product code mark code functions packages h8s/2636 f-ztat version hd64f2636 hd64f2636f no subclock function 128-pin qfp (fp-128b) hd64f2636uf subclock function 128-pin qfp (fp-128b) mask rom version hd6432636 hd6432636f no subclock function 128-pin qfp (fp-128b) hd6432636uf subclock function 128-pin qfp (fp-128b) h8s/2638 f-ztat version hd64f2638 hd64f2638f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd64f2638uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd64f2638wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432638 hd6432638f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd6432638uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432638wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) h8s/2639 f-ztat version hd64f2639 hd64f2639uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd64f2639wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432639 hd6432639uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432639wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b)
appendix f product code lineup rev. 6.00 feb 22, 2005 page 1483 of 1484 rej09b0103-0600 product type product code mark code functions packages h8s/2630 f-ztat version hd64f2630 hd64f2630f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd64f2630uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd64f2630wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432630 hd6432630f no subclock function or i 2 c bus interface 128-pin qfp (fp-128b) hd6432630uf subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432630wf subclock function and i 2 c bus interface 128-pin qfp (fp-128b) h8s/2635 f-ztat version hd64f2635 hd64f2635f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) mask rom version hd6432635 * hd6432635f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) hd6432634 * hd6432634f subclock function, no i 2 c bus interface 128-pin qfp (fp-128b) note: * under development
appendix g package dimensions rev. 6.00 feb 22, 2005 page 1484 of 1484 rej09b0103-0600 appendix g package dimensions figure g-1 shows the package dimensions of the h8s/2636, h8s/2638, h8s/2639, h8s/2630, h8s/2635, and h8s/2634. prqp0128kb-a p-qfp128-14x20-0.50 0.75 0.75 15.8 16.0 16.2 0.10 0.7 0.5 0.3 0.15 0.20 14 2.70 22.2 22.0 21.8 3.15 0.25 0.10 0.00 0.27 0.22 0.17 0.22 0.17 0.12 0.5 8 0 0.10 1.0 20 fp-128b/fp-128bv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 1.7g mass[typ.] 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e l h index mark * 1 * 2 * 3 128 1 ymx f 38 39 103 102 64 65 d e d e p z z b h d h e detail f 1 1 2 c l a a a l 1 1 p terminal cross section b c c b note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure g-1 fp-128b package dimensions
renesas 16-bit single-chip microcomputer hardware manual h8s/2639, h8s/2638, h8s/2636, h8s/2630, h8s/2635 group publication date: 1st edition, december 1999 rev.6.00, february 22, 2005 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ? 2005. renesas technology corp. all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices colophon 2.0
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